* [PATCH 001/138] drm/amd/powerplay: add new smu ip block
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 002/138] drm/amd/powerplay: add smu11 sub block for SMU IP Huang Rui
` (137 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch add amdgpu_smu ip block skeleton as placeholder.
We plan use new smu ip block from Vega20.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 166 +++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 45 +++++++
4 files changed, 216 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d67f8b1..e4ff186 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -83,6 +83,7 @@
#include "amdgpu_gem.h"
#include "amdgpu_doorbell.h"
#include "amdgpu_amdkfd.h"
+#include "amdgpu_smu.h"
#define MAX_GPU_INSTANCE 16
@@ -843,6 +844,9 @@ struct amdgpu_device {
struct amd_powerplay powerplay;
bool pp_force_state_enabled;
+ /* smu */
+ struct smu_context smu;
+
/* dpm */
struct amdgpu_pm pm;
u32 cg_flags;
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
index 231785a..a2ebda4 100644
--- a/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
include $(AMD_POWERPLAY)
-POWER_MGR = amd_powerplay.o
+POWER_MGR = amd_powerplay.o amdgpu_smu.o
AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
new file mode 100644
index 0000000..291cc31
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "pp_debug.h"
+#include <linux/firmware.h>
+#include <drm/drmP.h>
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "soc15_common.h"
+
+static int smu_set_funcs(struct amdgpu_device *adev)
+{
+ return 0;
+}
+
+static int smu_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
+ int ret;
+
+ ret = smu_set_funcs(adev);
+ if (ret)
+ return ret;
+
+ smu->adev = adev;
+ mutex_init(&smu->mutex);
+
+ return 0;
+}
+
+static int smu_sw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
+ int ret;
+
+ if (adev->asic_type < CHIP_VEGA20)
+ return -EINVAL;
+
+ ret = smu_init_microcode(smu);
+ if (ret) {
+ pr_err("Failed to load smu firmware!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int smu_sw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (adev->asic_type < CHIP_VEGA20)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int smu_hw_init(void *handle)
+{
+ int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
+
+ if (adev->asic_type < CHIP_VEGA20)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ /* TODO */
+
+ mutex_unlock(&smu->mutex);
+
+ pr_info("SMU is initialized successfully!\n");
+
+ return 0;
+}
+
+static int smu_hw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
+
+ if (adev->asic_type < CHIP_VEGA20)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int smu_suspend(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ if (adev->asic_type < CHIP_VEGA20)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int smu_resume(void *handle)
+{
+ int ret;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
+
+ if (adev->asic_type < CHIP_VEGA20)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ /* TODO */
+
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+}
+
+static int smu_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+{
+ return 0;
+}
+
+static int smu_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
+{
+ return 0;
+}
+
+const struct amd_ip_funcs smu_ip_funcs = {
+ .name = "smu",
+ .early_init = smu_early_init,
+ .late_init = NULL,
+ .sw_init = smu_sw_init,
+ .sw_fini = smu_sw_fini,
+ .hw_init = smu_hw_init,
+ .hw_fini = smu_hw_fini,
+ .suspend = smu_suspend,
+ .resume = smu_resume,
+ .is_idle = NULL,
+ .check_soft_reset = NULL,
+ .wait_for_idle = NULL,
+ .soft_reset = NULL,
+ .set_clockgating_state = smu_set_clockgating_state,
+ .set_powergating_state = smu_set_powergating_state,
+};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
new file mode 100644
index 0000000..5fb685c
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __AMDGPU_SMU_H__
+#define __AMDGPU_SMU_H__
+
+#include "amdgpu.h"
+
+struct smu_context
+{
+ struct amdgpu_device *adev;
+
+ const struct smu_funcs *funcs;
+ struct mutex mutex;
+};
+
+struct smu_funcs
+{
+ int (*init_microcode)(struct smu_context *smu);
+};
+
+#define smu_init_microcode(smu) \
+ ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+
+extern const struct amd_ip_funcs smu_ip_funcs;
+
+#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 002/138] drm/amd/powerplay: add smu11 sub block for SMU IP
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2019-01-25 10:23 ` [PATCH 001/138] drm/amd/powerplay: add new smu ip block Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 003/138] drm/amd/powerplay: add firmware loading interface Huang Rui
` (136 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch add smu11 sub ip block skeleton as placeholder
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 20 ++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 30 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 42 ++++++++++++++++++++++++++
5 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v11_0.c
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
index a2ebda4..1221da8 100644
--- a/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
include $(AMD_POWERPLAY)
-POWER_MGR = amd_powerplay.o amdgpu_smu.o
+POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o
AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 291cc31..247cd63 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -26,9 +26,20 @@
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "soc15_common.h"
+#include "smu_v11_0.h"
static int smu_set_funcs(struct amdgpu_device *adev)
{
+ struct smu_context *smu = &adev->smu;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ smu_v11_0_set_smu_funcs(smu);
+ break;
+ default:
+ return -EINVAL;
+ }
+
return 0;
}
@@ -164,3 +175,12 @@ const struct amd_ip_funcs smu_ip_funcs = {
.set_clockgating_state = smu_set_clockgating_state,
.set_powergating_state = smu_set_powergating_state,
};
+
+const struct amdgpu_ip_block_version smu_v11_0_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 11,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &smu_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 5fb685c..f655224 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -42,4 +42,6 @@ struct smu_funcs
extern const struct amd_ip_funcs smu_ip_funcs;
+extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
new file mode 100644
index 0000000..b5c5bca
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V11_0_H__
+#define __SMU_V11_0_H__
+
+#include "amdgpu_smu.h"
+
+void smu_v11_0_set_smu_funcs(struct smu_context *smu);
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
new file mode 100644
index 0000000..7fafc67
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "pp_debug.h"
+#include <linux/firmware.h>
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+
+static int smu_v11_0_init_microcode(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ return 0;
+}
+
+static const struct smu_funcs smu_v11_0_funcs = {
+ .init_microcode = smu_v11_0_init_microcode,
+};
+
+void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+{
+ smu->funcs = &smu_v11_0_funcs;
+}
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 003/138] drm/amd/powerplay: add firmware loading interface
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2019-01-25 10:23 ` [PATCH 001/138] drm/amd/powerplay: add new smu ip block Huang Rui
2019-01-25 10:23 ` [PATCH 002/138] drm/amd/powerplay: add smu11 sub block for SMU IP Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 004/138] drm/amd/powerplay: add fw load checking interface Huang Rui
` (135 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds firmware loading interface for smu.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++++++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 247cd63..afdef54 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -96,6 +96,12 @@ static int smu_hw_init(void *handle)
if (adev->asic_type < CHIP_VEGA20)
return -EINVAL;
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ ret = smu_load_microcode(smu);
+ if (ret)
+ return ret;
+ }
+
mutex_lock(&smu->mutex);
/* TODO */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index f655224..ab1deb5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -35,10 +35,13 @@ struct smu_context
struct smu_funcs
{
int (*init_microcode)(struct smu_context *smu);
+ int (*load_microcode)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+#define smu_load_microcode(smu) \
+ ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7fafc67..c50c8cb 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -32,8 +32,14 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_load_microcode(struct smu_context *smu)
+{
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
+ .load_microcode = smu_v11_0_load_microcode,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 004/138] drm/amd/powerplay: add fw load checking interface
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 003/138] drm/amd/powerplay: add firmware loading interface Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 005/138] drm/amd/powerplay: add interface to read pptable from vbios Huang Rui
` (134 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds fw load checking interface for smu.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++++++
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index afdef54..b781252 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -102,6 +102,12 @@ static int smu_hw_init(void *handle)
return ret;
}
+ ret = smu_check_fw_status(smu);
+ if (ret) {
+ pr_err("SMC firmware status is not correct\n");
+ return ret;
+ }
+
mutex_lock(&smu->mutex);
/* TODO */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ab1deb5..923a923 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -36,12 +36,15 @@ struct smu_funcs
{
int (*init_microcode)(struct smu_context *smu);
int (*load_microcode)(struct smu_context *smu);
+ int (*check_fw_status)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
#define smu_load_microcode(smu) \
((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
+#define smu_check_fw_status(smu) \
+ ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c50c8cb..a4fdc54 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -24,6 +24,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "smu_v11_0.h"
static int smu_v11_0_init_microcode(struct smu_context *smu)
{
@@ -37,9 +38,15 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_check_fw_status(struct smu_context *smu)
+{
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
+ .check_fw_status = smu_v11_0_check_fw_status,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 005/138] drm/amd/powerplay: add interface to read pptable from vbios
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 004/138] drm/amd/powerplay: add fw load checking interface Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 006/138] drm/amd/powerplay: add placeholder of smu_initialize_pptable Huang Rui
` (133 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to read pptable from vbios for smu.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 ++++++++++++++++++-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b781252..145435f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -87,6 +87,17 @@ static int smu_sw_fini(void *handle)
return 0;
}
+static int smu_smc_table_hw_init(struct smu_context *smu)
+{
+ int ret;
+
+ ret = smu_read_pptable_from_vbios(smu);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int smu_hw_init(void *handle)
{
int ret;
@@ -110,13 +121,19 @@ static int smu_hw_init(void *handle)
mutex_lock(&smu->mutex);
- /* TODO */
+ ret = smu_smc_table_hw_init(smu);
+ if (ret)
+ goto failed;
mutex_unlock(&smu->mutex);
pr_info("SMU is initialized successfully!\n");
return 0;
+
+failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
}
static int smu_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 923a923..1e5a784 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -37,6 +37,7 @@ struct smu_funcs
int (*init_microcode)(struct smu_context *smu);
int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
+ int (*read_pptable_from_vbios)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -45,6 +46,8 @@ struct smu_funcs
((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
#define smu_check_fw_status(smu) \
((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
+#define smu_read_pptable_from_vbios(smu) \
+ ((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 006/138] drm/amd/powerplay: add placeholder of smu_initialize_pptable
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 005/138] drm/amd/powerplay: add interface to read pptable from vbios Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 007/138] drm/amd/powerplay: add interface to init smc tables (v2) Huang Rui
` (132 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds placeholder of smu_initialize_pptable for smu.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 145435f..d6ecd63 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -59,6 +59,25 @@ static int smu_early_init(void *handle)
return 0;
}
+static int smu_initialize_pptable(struct smu_context *smu)
+{
+ /* TODO */
+ return 0;
+}
+
+static int smu_smc_table_sw_init(struct smu_context *smu)
+{
+ int ret;
+
+ ret = smu_initialize_pptable(smu);
+ if (ret) {
+ pr_err("Failed to init smu_initialize_pptable!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int smu_sw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -74,6 +93,12 @@ static int smu_sw_init(void *handle)
return ret;
}
+ ret = smu_smc_table_sw_init(smu);
+ if (ret) {
+ pr_err("Failed to sw init smc table!\n");
+ return ret;
+ }
+
return 0;
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 007/138] drm/amd/powerplay: add interface to init smc tables (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 006/138] drm/amd/powerplay: add placeholder of smu_initialize_pptable Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 008/138] drm/amd/powerplay: add interface to init power (v2) Huang Rui
` (131 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to init smc tables for smu. It is to create smu_table
structure, and init smc tables such as TABLE_PPTABLE, TABLE_WATERMARKS,
TABLE_SMU_METRICS, and etc.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d6ecd63..71da3dc 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -75,6 +75,16 @@ static int smu_smc_table_sw_init(struct smu_context *smu)
return ret;
}
+ /**
+ * Create smu_table structure, and init smc tables such as
+ * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
+ */
+ ret = smu_init_smc_tables(smu);
+ if (ret) {
+ pr_err("Failed to init smc tables!\n");
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 1e5a784..8ca9835 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -35,6 +35,7 @@ struct smu_context
struct smu_funcs
{
int (*init_microcode)(struct smu_context *smu);
+ int (*init_smc_tables)(struct smu_context *smu);
int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
int (*read_pptable_from_vbios)(struct smu_context *smu);
@@ -42,6 +43,8 @@ struct smu_funcs
#define smu_init_microcode(smu) \
((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+#define smu_init_smc_tables(smu) \
+ ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
#define smu_load_microcode(smu) \
((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
#define smu_check_fw_status(smu) \
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 008/138] drm/amd/powerplay: add interface to init power (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 007/138] drm/amd/powerplay: add interface to init smc tables (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 009/138] drm/amd/powerplay: add interface to get vbios bootup values (v2) Huang Rui
` (130 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to init power function for smu.
It's to create smu_power_context structure, and allocate smu_dpm_context and
context size to fill the smu_power_context data.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 ++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 71da3dc..10316a2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -85,6 +85,16 @@ static int smu_smc_table_sw_init(struct smu_context *smu)
return ret;
}
+ /**
+ * Create smu_power_context structure, and allocate smu_dpm_context and
+ * context size to fill the smu_power_context data.
+ */
+ ret = smu_init_power(smu);
+ if (ret) {
+ pr_err("Failed to init smu_init_power!\n");
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8ca9835..d6cb895 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -36,6 +36,7 @@ struct smu_funcs
{
int (*init_microcode)(struct smu_context *smu);
int (*init_smc_tables)(struct smu_context *smu);
+ int (*init_power)(struct smu_context *smu);
int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
int (*read_pptable_from_vbios)(struct smu_context *smu);
@@ -45,6 +46,8 @@ struct smu_funcs
((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
#define smu_init_smc_tables(smu) \
((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+#define smu_init_power(smu) \
+ ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
#define smu_load_microcode(smu) \
((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
#define smu_check_fw_status(smu) \
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 009/138] drm/amd/powerplay: add interface to get vbios bootup values (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 008/138] drm/amd/powerplay: add interface to init power (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 010/138] drm/amd/powerplay: add interface to check pptable (v2) Huang Rui
` (129 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to get vbios bootup values for smu.
It's to get boot_values from vbios to set revision, gfxclk, and etc.
v2: add detailed info to describe this function.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 +++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 10316a2..d022388 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -140,6 +140,11 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /* get boot_values from vbios to set revision, gfxclk, and etc. */
+ ret = smu_get_vbios_bootup_values(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index d6cb895..10888c6 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -40,6 +40,7 @@ struct smu_funcs
int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
int (*read_pptable_from_vbios)(struct smu_context *smu);
+ int (*get_vbios_bootup_values)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -54,6 +55,8 @@ struct smu_funcs
((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
#define smu_read_pptable_from_vbios(smu) \
((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
+#define smu_get_vbios_bootup_values(smu) \
+ ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 010/138] drm/amd/powerplay: add interface to check pptable (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 009/138] drm/amd/powerplay: add interface to get vbios bootup values (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 011/138] drm/amd/powerplay: add interface to init fb allocations (v2) Huang Rui
` (128 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to check pptable function for smu.
It's to check if the format_revision in vbios is up to pptable header version,
and the structure size is not 0.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d022388..d7d40bf 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -145,6 +145,14 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * check if the format_revision in vbios is up to pptable header
+ * version, and the structure size is not 0.
+ */
+ ret = smu_check_pptable(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 10888c6..4015963 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -41,6 +41,7 @@ struct smu_funcs
int (*check_fw_status)(struct smu_context *smu);
int (*read_pptable_from_vbios)(struct smu_context *smu);
int (*get_vbios_bootup_values)(struct smu_context *smu);
+ int (*check_pptable)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -57,6 +58,8 @@ struct smu_funcs
((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+#define smu_check_pptable(smu) \
+ ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 011/138] drm/amd/powerplay: add interface to init fb allocations (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 010/138] drm/amd/powerplay: add interface to check pptable (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 012/138] drm/amd/powerplay: add interface to parse pptable (v2) Huang Rui
` (127 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to init fb allocations for smu.
It's to allocate vram bos to store smc table contents.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d7d40bf..931343c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -132,6 +132,12 @@ static int smu_sw_fini(void *handle)
return 0;
}
+static int smu_init_fb_allocations(struct smu_context *smu)
+{
+ /* TODO */
+ return 0;
+}
+
static int smu_smc_table_hw_init(struct smu_context *smu)
{
int ret;
@@ -153,6 +159,13 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * allocate vram bos to store smc table contents.
+ */
+ ret = smu_init_fb_allocations(smu);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 012/138] drm/amd/powerplay: add interface to parse pptable (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 011/138] drm/amd/powerplay: add interface to init fb allocations (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 013/138] drm/amd/powerplay: add interface to populate smc " Huang Rui
` (126 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to parse pptable for smu.
It's to parse pptable format and fill PPTable_t smc_pptable to smu_table_context
structure. And read the smc_dpm_table from vbios, then fill it into smc_pptable.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 931343c..323db7d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -166,6 +166,15 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * Parse pptable format and fill PPTable_t smc_pptable to
+ * smu_table_context structure. And read the smc_dpm_table from vbios,
+ * then fill it into smc_pptable.
+ */
+ ret = smu_parse_pptable(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 4015963..fcdbade4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -42,6 +42,7 @@ struct smu_funcs
int (*read_pptable_from_vbios)(struct smu_context *smu);
int (*get_vbios_bootup_values)(struct smu_context *smu);
int (*check_pptable)(struct smu_context *smu);
+ int (*parse_pptable)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -60,6 +61,9 @@ struct smu_funcs
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_check_pptable(smu) \
((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+#define smu_parse_pptable(smu) \
+ ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 013/138] drm/amd/powerplay: add interface to populate smc pptable (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 012/138] drm/amd/powerplay: add interface to parse pptable (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 014/138] drm/amd/powerplay: add interface to check fw version (v2) Huang Rui
` (125 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to populate smc pptable for smu.
It's to set initialized values (get from vbios) to dpm tables context such as
gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each type of
clks.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 323db7d..b40a3c1 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -175,6 +175,15 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * Set initialized values (get from vbios) to dpm tables context such as
+ * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
+ * type of clks.
+ */
+ ret = smu_populate_smc_pptable(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index fcdbade4..da79777 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -43,6 +43,7 @@ struct smu_funcs
int (*get_vbios_bootup_values)(struct smu_context *smu);
int (*check_pptable)(struct smu_context *smu);
int (*parse_pptable)(struct smu_context *smu);
+ int (*populate_smc_pptable)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -63,6 +64,8 @@ struct smu_funcs
((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+#define smu_populate_smc_pptable(smu) \
+ ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 014/138] drm/amd/powerplay: add interface to check fw version (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 013/138] drm/amd/powerplay: add interface to populate smc " Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 015/138] drm/amd/powerplay: add interface to write pptable (v2) Huang Rui
` (124 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to check fw version for smu.
It's to send msg GetDriverIfVersion to check if the return value is equal with
DRIVER_IF_VERSION of smc header.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b40a3c1..5196825 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -184,6 +184,14 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * Send msg GetDriverIfVersion to check if the return value is equal
+ * with DRIVER_IF_VERSION of smc header.
+ */
+ ret = smu_check_fw_version(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index da79777..9525265 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -44,6 +44,7 @@ struct smu_funcs
int (*check_pptable)(struct smu_context *smu);
int (*parse_pptable)(struct smu_context *smu);
int (*populate_smc_pptable)(struct smu_context *smu);
+ int (*check_fw_version)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -66,6 +67,8 @@ struct smu_funcs
((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
#define smu_populate_smc_pptable(smu) \
((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
+#define smu_check_fw_version(smu) \
+ ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 015/138] drm/amd/powerplay: add interface to write pptable (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 014/138] drm/amd/powerplay: add interface to check fw version (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 016/138] drm/amd/powerplay: add interface to set min dcef deep sleep (v2) Huang Rui
` (123 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to write pptable for smu.
It's to copy pptable bo in the vram to smc with SMU MSGs such as
SetDriverDramAddr and TransferTableDram2Smu.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5196825..747b6b7 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -192,6 +192,14 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * Copy pptable bo in the vram to smc with SMU MSGs such as
+ * SetDriverDramAddr and TransferTableDram2Smu.
+ */
+ ret = smu_write_pptable(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 9525265..e7e9fec 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -45,6 +45,7 @@ struct smu_funcs
int (*parse_pptable)(struct smu_context *smu);
int (*populate_smc_pptable)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
+ int (*write_pptable)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -69,6 +70,8 @@ struct smu_funcs
((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
#define smu_check_fw_version(smu) \
((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+#define smu_write_pptable(smu) \
+ ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 016/138] drm/amd/powerplay: add interface to set min dcef deep sleep (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 015/138] drm/amd/powerplay: add interface to write pptable (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 017/138] drm/amd/powerplay: add interface to set tool table location (v2) Huang Rui
` (122 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to set min dcef deep sleep for smu.
It's to set min deep sleep dce fclk with bootup value from vbios via
SetMinDeepSleepDcefclk MSG.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 747b6b7..5e22b15 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -200,6 +200,14 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /*
+ * Set min deep sleep dce fclk with bootup value from vbios via
+ * SetMinDeepSleepDcefclk MSG.
+ */
+ ret = smu_set_min_dcef_deep_sleep(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index e7e9fec..90e80cd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -46,6 +46,7 @@ struct smu_funcs
int (*populate_smc_pptable)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
int (*write_pptable)(struct smu_context *smu);
+ int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -72,6 +73,8 @@ struct smu_funcs
((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
#define smu_write_pptable(smu) \
((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
+#define smu_set_min_dcef_deep_sleep(smu) \
+ ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 017/138] drm/amd/powerplay: add interface to set tool table location (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 016/138] drm/amd/powerplay: add interface to set min dcef deep sleep (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 018/138] drm/amd/powerplay: add interface to allocate memory pool (v2) Huang Rui
` (121 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to set tool table location for smu.
Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 ++++++-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5e22b15..87c46cf 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -208,7 +208,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
- return 0;
+ /*
+ * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
+ */
+ ret = smu_set_tool_table_location(smu);
+
+ return ret;
}
static int smu_hw_init(void *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 90e80cd..213c0bc 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -47,6 +47,7 @@ struct smu_funcs
int (*check_fw_version)(struct smu_context *smu);
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+ int (*set_tool_table_location)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -75,6 +76,8 @@ struct smu_funcs
((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
#define smu_set_min_dcef_deep_sleep(smu) \
((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
+#define smu_set_tool_table_location(smu) \
+ ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 018/138] drm/amd/powerplay: add interface to allocate memory pool (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 017/138] drm/amd/powerplay: add interface to set tool table location (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 019/138] drm/amd/powerplay: add interface to notify memory pool location (v2) Huang Rui
` (120 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to allocate memory pool for smu.
This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr and
DramLogSetDramAddr can notify it changed.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 87c46cf..4f61ee9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -216,6 +216,21 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
return ret;
}
+/**
+ * smu_alloc_memory_pool - allocate memory pool in the system memory
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
+ * and DramLogSetDramAddr can notify it changed.
+ *
+ * Returns 0 on success, error on failure.
+ */
+static int smu_alloc_memory_pool(struct smu_context *smu)
+{
+ return 0;
+}
+
static int smu_hw_init(void *handle)
{
int ret;
@@ -243,6 +258,10 @@ static int smu_hw_init(void *handle)
if (ret)
goto failed;
+ ret = smu_alloc_memory_pool(smu);
+ if (ret)
+ goto failed;
+
mutex_unlock(&smu->mutex);
pr_info("SMU is initialized successfully!\n");
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 019/138] drm/amd/powerplay: add interface to notify memory pool location (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 018/138] drm/amd/powerplay: add interface to allocate memory pool (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 020/138] drm/amd/powerplay: add interfaces for smu resume Huang Rui
` (119 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to notify memory pool location for smu.
It's to use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify pool
location.
v2: add detailed info to describe this function
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4f61ee9..e0a5597 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -262,6 +262,14 @@ static int smu_hw_init(void *handle)
if (ret)
goto failed;
+ /*
+ * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
+ * pool location.
+ */
+ ret = smu_notify_memory_pool_location(smu);
+ if (ret)
+ goto failed;
+
mutex_unlock(&smu->mutex);
pr_info("SMU is initialized successfully!\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 213c0bc..46f0d17 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -48,6 +48,7 @@ struct smu_funcs
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
+ int (*notify_memory_pool_location)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -78,6 +79,8 @@ struct smu_funcs
((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
#define smu_set_tool_table_location(smu) \
((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
+#define smu_notify_memory_pool_location(smu) \
+ ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 020/138] drm/amd/powerplay: add interfaces for smu resume
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 019/138] drm/amd/powerplay: add interface to notify memory pool location (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 021/138] drm/amd/powerplay: add resume sequence placeholder for smu ip block Huang Rui
` (118 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
SMU resume needs three more interfaces such as write_watermarks_table,
set_last_dcef_min_deep_sleep_clk, and system_features_control.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 46f0d17..b08c0c9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -49,6 +49,9 @@ struct smu_funcs
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
int (*notify_memory_pool_location)(struct smu_context *smu);
+ int (*write_watermarks_table)(struct smu_context *smu);
+ int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
+ int (*system_features_control)(struct smu_context *smu, bool en);
};
#define smu_init_microcode(smu) \
@@ -81,6 +84,12 @@ struct smu_funcs
((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
#define smu_notify_memory_pool_location(smu) \
((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+#define smu_write_watermarks_table(smu) \
+ ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
+#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+ ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+#define smu_system_features_control(smu, en) \
+ ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 021/138] drm/amd/powerplay: add resume sequence placeholder for smu ip block
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 020/138] drm/amd/powerplay: add interfaces for smu resume Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 022/138] drm/amdgpu: enable new smu ip block for vega20 Huang Rui
` (117 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds resume sequence placeholder for smu ip block.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 39 +++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e0a5597..a6f19b5 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -311,13 +311,50 @@ static int smu_resume(void *handle)
if (adev->asic_type < CHIP_VEGA20)
return -EINVAL;
+ pr_info("SMU is resuming...\n");
+
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ ret = smu_load_microcode(smu);
+ if (ret)
+ return ret;
+ }
+
+ ret = smu_check_fw_status(smu);
+ if (ret) {
+ pr_err("SMC firmware status is not correct\n");
+ return ret;
+ }
+
mutex_lock(&smu->mutex);
- /* TODO */
+ ret = smu_set_tool_table_location(smu);
+ if (ret)
+ goto failed;
+
+ ret = smu_write_pptable(smu);
+ if (ret)
+ goto failed;
+
+ ret = smu_write_watermarks_table(smu);
+ if (ret)
+ goto failed;
+
+ ret = smu_set_last_dcef_min_deep_sleep_clk(smu);
+ if (ret)
+ goto failed;
+
+ ret = smu_system_features_control(smu, true);
+ if (ret)
+ goto failed;
mutex_unlock(&smu->mutex);
+ pr_info("SMU is resumed successfully!\n");
+
return 0;
+failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
}
static int smu_set_clockgating_state(void *handle,
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 022/138] drm/amdgpu: enable new smu ip block for vega20
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 021/138] drm/amd/powerplay: add resume sequence placeholder for smu ip block Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 023/138] drm/amd/powerplay: init microcode for smu11 Huang Rui
` (116 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
Switch to new smu ip block since vega20.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index dd81721..0e60496 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -63,6 +63,7 @@
#include "vcn_v1_0.h"
#include "dce_virtual.h"
#include "mxgpu_ai.h"
+#include "amdgpu_smu.h"
#define mmMP0_MISC_CGTT_CTRL0 0x01b9
#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
@@ -603,8 +604,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
}
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
- if (!amdgpu_sriov_vf(adev))
- amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
+ if (!amdgpu_sriov_vf(adev)) {
+ if (amdgpu_dpm == 1 && adev->asic_type >= CHIP_VEGA20)
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
+ }
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 023/138] drm/amd/powerplay: init microcode for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 022/138] drm/amdgpu: enable new smu ip block for vega20 Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 024/138] drm/amd/powerplay: add new ppsmc header for smu11 (v2) Huang Rui
` (115 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function of init mircrocode for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 47 ++++++++++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index a4fdc54..57cd3b9 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -26,11 +26,56 @@
#include "amdgpu_smu.h"
#include "smu_v11_0.h"
+MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
+
static int smu_v11_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
+ const char *chip_name;
+ char fw_name[30];
+ int err = 0;
+ const struct smc_firmware_header_v1_0 *hdr;
+ const struct common_firmware_header *header;
+ struct amdgpu_firmware_info *ucode = NULL;
- return 0;
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ chip_name = "vega20";
+ break;
+ default:
+ BUG();
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
+
+ err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+ err = amdgpu_ucode_validate(adev->pm.fw);
+ if (err)
+ goto out;
+
+ hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
+ amdgpu_ucode_print_smc_hdr(&hdr->header);
+ adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
+ ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
+ ucode->fw = adev->pm.fw;
+ header = (const struct common_firmware_header *)ucode->fw->data;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+ }
+
+out:
+ if (err) {
+ DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
+ fw_name);
+ release_firmware(adev->pm.fw);
+ adev->pm.fw = NULL;
+ }
+ return err;
}
static int smu_v11_0_load_microcode(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 024/138] drm/amd/powerplay: add new ppsmc header for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 023/138] drm/amd/powerplay: init microcode for smu11 Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 025/138] drm/amd/powerplay: implement smu send message functions for smu11 (v3) Huang Rui
` (114 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This header will be used for smc message handling.
v2: add a license to the top of the header file (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
.../gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 128 +++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
2 files changed, 129 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
new file mode 100644
index 0000000..f466f62
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_V11_0_PPSMC_H
+#define SMU_V11_0_PPSMC_H
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+// Message Definitions:
+// BASIC
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4
+#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5
+#define PPSMC_MSG_EnableAllSmuFeatures 0x6
+#define PPSMC_MSG_DisableAllSmuFeatures 0x7
+#define PPSMC_MSG_EnableSmuFeaturesLow 0x8
+#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9
+#define PPSMC_MSG_DisableSmuFeaturesLow 0xA
+#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB
+#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xC
+#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xD
+#define PPSMC_MSG_SetDriverDramAddrHigh 0xE
+#define PPSMC_MSG_SetDriverDramAddrLow 0xF
+#define PPSMC_MSG_SetToolsDramAddrHigh 0x10
+#define PPSMC_MSG_SetToolsDramAddrLow 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram 0x12
+#define PPSMC_MSG_TransferTableDram2Smu 0x13
+#define PPSMC_MSG_UseDefaultPPTable 0x14
+#define PPSMC_MSG_UseBackupPPTable 0x15
+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x16
+#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x17
+
+//BACO/BAMACO/BOMACO
+#define PPSMC_MSG_EnterBaco 0x18
+#define PPSMC_MSG_ExitBaco 0x19
+
+//DPM
+#define PPSMC_MSG_SetSoftMinByFreq 0x1A
+#define PPSMC_MSG_SetSoftMaxByFreq 0x1B
+#define PPSMC_MSG_SetHardMinByFreq 0x1C
+#define PPSMC_MSG_SetHardMaxByFreq 0x1D
+#define PPSMC_MSG_GetMinDpmFreq 0x1E
+#define PPSMC_MSG_GetMaxDpmFreq 0x1F
+#define PPSMC_MSG_GetDpmFreqByIndex 0x20
+#define PPSMC_MSG_OverridePcieParameters 0x21
+#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x22
+#define PPSMC_MSG_SetWorkloadMask 0x23
+#define PPSMC_MSG_SetUclkFastSwitch 0x24
+#define PPSMC_MSG_GetAvfsVoltageByDpm 0x25
+#define PPSMC_MSG_SetVideoFps 0x26
+#define PPSMC_MSG_GetDcModeMaxDpmFreq 0x27
+
+//Power Gating
+#define PPSMC_MSG_AllowGfxOff 0x28
+#define PPSMC_MSG_DisallowGfxOff 0x29
+#define PPSMC_MSG_PowerUpVcn 0x2A
+#define PPSMC_MSG_PowerDownVcn 0x2B
+#define PPSMC_MSG_PowerUpJpeg 0x2C
+#define PPSMC_MSG_PowerDownJpeg 0x2D
+//reserve 0x2A to 0x2F for PG harvesting TBD
+
+//I2C Interface
+#define PPSMC_RequestI2cTransaction 0x30
+
+//Resets
+#define PPSMC_MSG_SoftReset 0x31 //FIXME Need confirmation from driver
+#define PPSMC_MSG_PrepareMp1ForUnload 0x32
+#define PPSMC_MSG_PrepareMp1ForReset 0x33
+#define PPSMC_MSG_PrepareMp1ForShutdown 0x34
+
+//ACDC Power Source
+#define PPSMC_MSG_SetPptLimit 0x35
+#define PPSMC_MSG_GetPptLimit 0x36
+#define PPSMC_MSG_ReenableAcDcInterrupt 0x37
+#define PPSMC_MSG_NotifyPowerSource 0x38
+//#define PPSMC_MSG_GfxDeviceDriverReset 0x39 //FIXME mode1 and 2 resets will go directly go PSP
+
+//BTC
+#define PPSMC_MSG_RunBtc 0x3A
+
+//Debug
+#define PPSMC_MSG_DramLogSetDramAddrHigh 0x3B
+#define PPSMC_MSG_DramLogSetDramAddrLow 0x3C
+#define PPSMC_MSG_DramLogSetDramSize 0x3D
+#define PPSMC_MSG_GetDebugData 0x3E
+
+//Others
+#define PPSMC_MSG_ConfigureGfxDidt 0x3F
+#define PPSMC_MSG_NumOfDisplays 0x40
+
+#define PPSMC_MSG_SetMemoryChannelConfig 0x41
+#define PPSMC_MSG_SetGeminiMode 0x42
+#define PPSMC_MSG_SetGeminiApertureHigh 0x43
+#define PPSMC_MSG_SetGeminiApertureLow 0x44
+
+#define PPSMC_Message_Count 0x45
+
+typedef uint32_t PPSMC_Result;
+typedef uint32_t PPSMC_Msg;
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 57cd3b9..761bfb1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_v11_0.h"
+#include "smu_v11_0_ppsmc.h"
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 025/138] drm/amd/powerplay: implement smu send message functions for smu11 (v3)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 024/138] drm/amd/powerplay: add new ppsmc header for smu11 (v2) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 026/138] drm/amd/powerplay: implement check_fw_status function for smu11 Huang Rui
` (113 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Add function of smu send message for smu11
v2: fix the missing ) in define of smu_send_smc_msg_with_param
v3: Use adev usec timeout for smu as well, the origin time 10 us is not enough. (Ray)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 ++-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 84 ++++++++++++++++++++++++++
2 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b08c0c9..9e467d3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -52,6 +52,9 @@ struct smu_funcs
int (*write_watermarks_table)(struct smu_context *smu);
int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
int (*system_features_control)(struct smu_context *smu, bool en);
+ int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
+ int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
+
};
#define smu_init_microcode(smu) \
@@ -90,7 +93,10 @@ struct smu_funcs
((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
#define smu_system_features_control(smu, en) \
((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
-
+#define smu_send_smc_msg(smu, msg) \
+ ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+#define smu_send_smc_msg_with_param(smu, msg, param) \
+ ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
extern const struct amd_ip_funcs smu_ip_funcs;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 761bfb1..feee3e8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -26,9 +26,91 @@
#include "amdgpu_smu.h"
#include "smu_v11_0.h"
#include "smu_v11_0_ppsmc.h"
+#include "soc15_common.h"
+
+#include "asic_reg/thm/thm_11_0_2_offset.h"
+#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
+#include "asic_reg/mp/mp_9_0_offset.h"
+#include "asic_reg/mp/mp_9_0_sh_mask.h"
+#include "asic_reg/nbio/nbio_7_4_offset.h"
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
+static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
+ uint16_t msg)
+{
+ struct amdgpu_device *adev = smu->adev;
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
+ return 0;
+}
+
+static int smu_v11_0_wait_for_response(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t cur_value, i;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+ if (i == adev->usec_timeout)
+ return -ETIME;
+
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == PPSMC_Result_OK ? 0:-EIO;
+}
+
+static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+
+ smu_v11_0_wait_for_response(smu);
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+
+ smu_v11_0_send_msg_without_waiting(smu, msg);
+
+ ret = smu_v11_0_wait_for_response(smu);
+
+ if (ret)
+ pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
+ ret);
+
+ return ret;
+
+}
+
+static int
+smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ uint32_t param)
+{
+
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+
+ ret = smu_v11_0_wait_for_response(smu);
+ if (ret)
+ pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
+ ret);
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
+
+ smu_v11_0_send_msg_without_waiting(smu, msg);
+
+ ret = smu_v11_0_wait_for_response(smu);
+ if (ret)
+ pr_err("Failed to send message 0x%x, response 0x%x\n", msg,
+ ret);
+
+ return ret;
+}
+
static int smu_v11_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -93,6 +175,8 @@ static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
.check_fw_status = smu_v11_0_check_fw_status,
+ .send_smc_msg = smu_v11_0_send_msg,
+ .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 026/138] drm/amd/powerplay: implement check_fw_status function for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 025/138] drm/amd/powerplay: implement smu send message functions for smu11 (v3) Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 027/138] drm/amd/powerplay: implement check_fw_version " Huang Rui
` (112 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Add function of check firmware status funtions for smu11
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 11 +++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 13 ++++++++++++-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index b5c5bca..6ba5bde 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -25,6 +25,17 @@
#include "amdgpu_smu.h"
+/* MP Apertures */
+#define MP0_Public 0x03800000
+#define MP0_SRAM 0x03900000
+#define MP1_Public 0x03b00000
+#define MP1_SRAM 0x03c00004
+
+/* address block */
+#define smnMP1_FIRMWARE_FLAGS 0x3010024
+#define smnMP0_FW_INTF 0x30101c0
+#define smnMP1_PUB_CTRL 0x3010b14
+
void smu_v11_0_set_smu_funcs(struct smu_context *smu);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index feee3e8..142ad1d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -168,7 +168,18 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
static int smu_v11_0_check_fw_status(struct smu_context *smu)
{
- return 0;
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t mp1_fw_flags;
+
+ WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
+ (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
+
+ mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
+
+ if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+ MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
+ return 0;
+ return -EIO;
}
static const struct smu_funcs smu_v11_0_funcs = {
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 027/138] drm/amd/powerplay: implement check_fw_version function for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 026/138] drm/amd/powerplay: implement check_fw_status function for smu11 Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 028/138] drm/amd/powerplay: add pptable header " Huang Rui
` (111 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Add function of check firmware version for smu11
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 142ad1d..5809144 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -26,6 +26,7 @@
#include "amdgpu_smu.h"
#include "smu_v11_0.h"
#include "smu_v11_0_ppsmc.h"
+#include "smu11_driver_if.h"
#include "soc15_common.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
@@ -44,6 +45,14 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
return 0;
}
+static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ return 0;
+}
+
static int smu_v11_0_wait_for_response(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -182,10 +191,30 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
return -EIO;
}
+static int smu_v11_0_check_fw_version(struct smu_context *smu)
+{
+ uint32_t smu_version = 0xff;
+ int ret = 0;
+
+ ret = smu_send_smc_msg(smu, PPSMC_MSG_GetDriverIfVersion);
+ if (ret)
+ goto err;
+
+ ret = smu_v11_0_read_arg(smu, &smu_version);
+ if (ret)
+ goto err;
+
+ if (smu_version == SMU11_DRIVER_IF_VERSION)
+ return 0;
+err:
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
.check_fw_status = smu_v11_0_check_fw_status,
+ .check_fw_version = smu_v11_0_check_fw_version,
.send_smc_msg = smu_v11_0_send_msg,
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 028/138] drm/amd/powerplay: add pptable header for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 027/138] drm/amd/powerplay: implement check_fw_version " Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 029/138] drm/amdgpu: update atomfirmware " Huang Rui
` (110 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds the pptable header for smu11.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
.../gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h | 147 +++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
2 files changed, 148 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
new file mode 100644
index 0000000..45aed6f
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef SMU_11_0_PPTABLE_H
+#define SMU_11_0_PPTABLE_H
+
+
+#define SMU_11_0_TABLE_FORMAT_REVISION 12
+
+//// POWERPLAYTABLE::ulPlatformCaps
+#define SMU_11_0_PP_PLATFORM_CAP_POWERPLAY 0x1
+#define SMU_11_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
+#define SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC 0x4
+#define SMU_11_0_PP_PLATFORM_CAP_BACO 0x8
+#define SMU_11_0_PP_PLATFORM_CAP_MACO 0x10
+#define SMU_11_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20
+
+// SMU_11_0_PP_THERMALCONTROLLER - Thermal Controller Type
+#define SMU_11_0_PP_THERMALCONTROLLER_NONE 0
+
+#define SMU_11_0_PP_OVERDRIVE_VERSION 0x0800
+#define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION 0x0100
+
+enum SMU_11_0_ODFEATURE_ID {
+ SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 0, //GFXCLK Limit feature
+ SMU_11_0_ODFEATURE_GFXCLK_CURVE, //GFXCLK Curve feature
+ SMU_11_0_ODFEATURE_UCLK_MAX, //UCLK Limit feature
+ SMU_11_0_ODFEATURE_POWER_LIMIT, //Power Limit feature
+ SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature
+ SMU_11_0_ODFEATURE_FAN_SPEED_MIN, //Minimum Fan Speed feature
+ SMU_11_0_ODFEATURE_TEMPERATURE_FAN, //Fan Target Temperature Limit feature
+ SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature
+ SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE, //AC Timing Tuning feature
+ SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL, //Zero RPM feature
+ SMU_11_0_ODFEATURE_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature
+ SMU_11_0_ODFEATURE_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature
+ SMU_11_0_ODFEATURE_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature
+ SMU_11_0_ODFEATURE_COUNT,
+};
+#define SMU_11_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
+
+enum SMU_11_0_ODSETTING_ID {
+ SMU_11_0_ODSETTING_GFXCLKFMAX = 0,
+ SMU_11_0_ODSETTING_GFXCLKFMIN,
+ SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
+ SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
+ SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
+ SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
+ SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
+ SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
+ SMU_11_0_ODSETTING_UCLKFMAX,
+ SMU_11_0_ODSETTING_POWERPERCENTAGE,
+ SMU_11_0_ODSETTING_FANRPMMIN,
+ SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT,
+ SMU_11_0_ODSETTING_FANTARGETTEMPERATURE,
+ SMU_11_0_ODSETTING_OPERATINGTEMPMAX,
+ SMU_11_0_ODSETTING_ACTIMING,
+ SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL,
+ SMU_11_0_ODSETTING_AUTOUVENGINE,
+ SMU_11_0_ODSETTING_AUTOOCENGINE,
+ SMU_11_0_ODSETTING_AUTOOCMEMORY,
+ SMU_11_0_ODSETTING_COUNT,
+};
+#define SMU_11_0_MAX_ODSETTING 32 //Maximum Number of ODSettings
+
+struct smu_11_0_overdrive_table
+{
+ uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION
+ uint8_t reserve[3]; //Zero filled field reserved for future use
+ uint32_t feature_count; //Total number of supported features
+ uint32_t setting_count; //Total number of supported settings
+ uint8_t cap[SMU_11_0_MAX_ODFEATURE]; //OD feature support flags
+ uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings
+ uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings
+};
+
+enum SMU_11_0_PPCLOCK_ID {
+ SMU_11_0_PPCLOCK_GFXCLK = 0,
+ SMU_11_0_PPCLOCK_VCLK,
+ SMU_11_0_PPCLOCK_DCLK,
+ SMU_11_0_PPCLOCK_ECLK,
+ SMU_11_0_PPCLOCK_SOCCLK,
+ SMU_11_0_PPCLOCK_UCLK,
+ SMU_11_0_PPCLOCK_DCEFCLK,
+ SMU_11_0_PPCLOCK_DISPCLK,
+ SMU_11_0_PPCLOCK_PIXCLK,
+ SMU_11_0_PPCLOCK_PHYCLK,
+ SMU_11_0_PPCLOCK_COUNT,
+};
+#define SMU_11_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
+
+struct smu_11_0_power_saving_clock_table
+{
+ uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
+ uint8_t reserve[3]; //Zero filled field reserved for future use
+ uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
+ uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
+ uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
+};
+
+struct smu_11_0_powerplay_table
+{
+ struct atom_common_table_header header;
+ uint8_t table_revision;
+ uint32_t table_size; //Driver portion table size. The offset to smc_pptable including header size
+ uint32_t golden_pp_id;
+ uint32_t golden_revision;
+ uint16_t format_id;
+ uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
+
+ uint8_t thermal_controller_type; //one of SMU_11_0_PP_THERMALCONTROLLER
+
+ uint16_t small_power_limit1;
+ uint16_t small_power_limit2;
+ uint16_t boost_power_limit;
+ uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning.
+ uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
+ uint16_t software_shutdown_temp;
+
+ uint16_t reserve[6]; //Zero filled field reserved for future use
+
+ struct smu_11_0_power_saving_clock_table power_saving_clock;
+ struct smu_11_0_overdrive_table overdrive_table;
+
+ PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 5809144..84ce624 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -28,6 +28,7 @@
#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
#include "soc15_common.h"
+#include "smu_v11_0_pptable.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 029/138] drm/amdgpu: update atomfirmware header for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 028/138] drm/amd/powerplay: add pptable header " Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 030/138] drm/amdgpu: update new members in atomfirmware Huang Rui
` (109 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch updates atomfirmware header on smu11 for future use.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/atomfirmware.h | 44 +++++++++++++++++++++++++-----
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 8eb0bb2..efdff6a 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -528,6 +528,35 @@ struct atom_firmware_info_v3_2 {
uint32_t reserved2[3];
};
+struct atom_firmware_info_v3_3
+{
+ struct atom_common_table_header table_header;
+ uint32_t firmware_revision;
+ uint32_t bootup_sclk_in10khz;
+ uint32_t bootup_mclk_in10khz;
+ uint32_t firmware_capability; // enum atombios_firmware_capability
+ uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
+ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
+ uint16_t bootup_vddc_mv;
+ uint16_t bootup_vddci_mv;
+ uint16_t bootup_mvddc_mv;
+ uint16_t bootup_vddgfx_mv;
+ uint8_t mem_module_id;
+ uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
+ uint8_t reserved1[2];
+ uint32_t mc_baseaddr_high;
+ uint32_t mc_baseaddr_low;
+ uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
+ uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
+ uint8_t board_i2c_feature_slave_addr;
+ uint8_t reserved3;
+ uint16_t bootup_mvddq_mv;
+ uint16_t bootup_mvpp_mv;
+ uint32_t zfbstartaddrin16mb;
+ uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
+ uint32_t reserved2[2];
+};
+
/*
***************************************************************************
Data Table lcd_info structure
@@ -1226,16 +1255,17 @@ struct atom_gfx_info_v2_3 {
uint32_t rm21_sram_vmin_value;
};
-struct atom_gfx_info_v2_4 {
+struct atom_gfx_info_v2_4
+{
struct atom_common_table_header table_header;
uint8_t gfxip_min_ver;
uint8_t gfxip_max_ver;
- uint8_t gc_num_se;
- uint8_t max_tile_pipes;
- uint8_t gc_num_cu_per_sh;
- uint8_t gc_num_sh_per_se;
- uint8_t gc_num_rb_per_se;
- uint8_t gc_num_tccs;
+ uint8_t max_shader_engines;
+ uint8_t reserved;
+ uint8_t max_cu_per_sh;
+ uint8_t max_sh_per_se;
+ uint8_t max_backends_per_se;
+ uint8_t max_texture_channel_caches;
uint32_t regaddr_cp_dma_src_addr;
uint32_t regaddr_cp_dma_src_addr_hi;
uint32_t regaddr_cp_dma_dst_addr;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 84ce624..a2a0ee1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -24,6 +24,7 @@
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
+#include "atomfirmware.h"
#include "smu_v11_0.h"
#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 030/138] drm/amdgpu: update new members in atomfirmware
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 029/138] drm/amdgpu: update atomfirmware " Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 031/138] drm/amd/powerplay: add smu table context structure Huang Rui
` (108 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch updates new members for fields to meet new atomfirmware header.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b61e1dc..46ffbc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -346,11 +346,11 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
(mode_info->atom_context->bios + data_offset);
switch (crev) {
case 4:
- adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se;
- adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh;
- adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se;
- adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se;
- adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs;
+ adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
+ adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
+ adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
+ adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
+ adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 031/138] drm/amd/powerplay: add smu table context structure
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 030/138] drm/amdgpu: update new members in atomfirmware Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:23 ` [PATCH 032/138] drm/amd/powerplay: add get atom data table helper Huang Rui
` (107 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds smu table context.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 9e467d3..215902f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -24,12 +24,20 @@
#include "amdgpu.h"
+struct smu_table_context
+{
+ void *power_play_table;
+ uint32_t power_play_table_size;
+};
+
struct smu_context
{
struct amdgpu_device *adev;
const struct smu_funcs *funcs;
struct mutex mutex;
+
+ struct smu_table_context smu_table;
};
struct smu_funcs
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 032/138] drm/amd/powerplay: add get atom data table helper
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (30 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 031/138] drm/amd/powerplay: add smu table context structure Huang Rui
@ 2019-01-25 10:23 ` Huang Rui
2019-01-25 10:24 ` [PATCH 033/138] drm/amdgpu: move get_index_into_master_table macro into atomfirmware header Huang Rui
` (106 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds get atom data table helper for smu future use.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 17 +++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index a6f19b5..901c99f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -27,6 +27,7 @@
#include "amdgpu_smu.h"
#include "soc15_common.h"
#include "smu_v11_0.h"
+#include "atom.h"
static int smu_set_funcs(struct amdgpu_device *adev)
{
@@ -59,6 +60,22 @@ static int smu_early_init(void *handle)
return 0;
}
+int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ uint16_t *size, uint8_t *frev, uint8_t *crev,
+ uint8_t **addr)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint16_t data_start;
+
+ if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
+ size, frev, crev, &data_start))
+ return -EINVAL;
+
+ *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
+
+ return 0;
+}
+
static int smu_initialize_pptable(struct smu_context *smu)
{
/* TODO */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 215902f..88eee63 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -106,6 +106,10 @@ struct smu_funcs
#define smu_send_smc_msg_with_param(smu, msg, param) \
((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ uint16_t *size, uint8_t *frev, uint8_t *crev,
+ uint8_t **addr);
+
extern const struct amd_ip_funcs smu_ip_funcs;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 033/138] drm/amdgpu: move get_index_into_master_table macro into atomfirmware header
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (31 preceding siblings ...)
2019-01-25 10:23 ` [PATCH 032/138] drm/amd/powerplay: add get atom data table helper Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 034/138] drm/amd/powerplay: implement read_pptable_from_vbios function for smu11 Huang Rui
` (105 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patchs move get_index_into_master_table macro into atomfirmware header for
future use on smu.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 ++
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 46ffbc8..ea917d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -28,8 +28,6 @@
#include "atom.h"
#include "atombios.h"
-#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
-
bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
{
int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index 20f158f..f8ea77d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -24,6 +24,8 @@
#ifndef __AMDGPU_ATOMFIRMWARE_H__
#define __AMDGPU_ATOMFIRMWARE_H__
+#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
+
bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);
void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 034/138] drm/amd/powerplay: implement read_pptable_from_vbios function for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (32 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 033/138] drm/amdgpu: move get_index_into_master_table macro into atomfirmware header Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 035/138] drm/amd/powerplay: implement smu_init[fini]_smc_tables " Huang Rui
` (104 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch implements the function of read_pptable_from_vbios for smu11.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index a2a0ee1..efc3e4b 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
@@ -212,6 +213,27 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_read_pptable_from_vbios(struct smu_context *smu)
+{
+ int ret, index;
+ uint16_t size;
+ uint8_t frev, crev;
+ struct smu_11_0_powerplay_table *table;
+
+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ powerplayinfo);
+
+ ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
+ (uint8_t **)&table);
+ if (ret)
+ return ret;
+
+ smu->smu_table.power_play_table = table;
+ smu->smu_table.power_play_table_size = size;
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -219,6 +241,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.check_fw_version = smu_v11_0_check_fw_version,
.send_smc_msg = smu_v11_0_send_msg,
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_pptable_from_vbios = smu_v11_0_read_pptable_from_vbios,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 035/138] drm/amd/powerplay: implement smu_init[fini]_smc_tables for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (33 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 034/138] drm/amd/powerplay: implement read_pptable_from_vbios function for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 036/138] drm/amd/powerplay: implement smu dpm context functions " Huang Rui
` (103 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Each SMU IP may have a different number of SMU tables, so these tables
are allocated using dynamic memory
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 21 +++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 22 +++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 43 ++++++++++++++++++++++++++
3 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 901c99f..f79a125 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -115,6 +115,19 @@ static int smu_smc_table_sw_init(struct smu_context *smu)
return 0;
}
+static int smu_smc_table_sw_fini(struct smu_context *smu)
+{
+ int ret;
+
+ ret = smu_fini_smc_tables(smu);
+ if (ret) {
+ pr_err("Failed to smu_fini_smc_tables!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int smu_sw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -142,10 +155,18 @@ static int smu_sw_init(void *handle)
static int smu_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct smu_context *smu = &adev->smu;
+ int ret;
if (adev->asic_type < CHIP_VEGA20)
return -EINVAL;
+ ret = smu_smc_table_sw_fini(smu);
+ if (ret) {
+ pr_err("Failed to sw fini smc table!\n");
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 88eee63..16f11a4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -24,10 +24,29 @@
#include "amdgpu.h"
+#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
+ do { \
+ tables[table_id].size = s; \
+ tables[table_id].align = a; \
+ tables[table_id].domain = d; \
+ } while (0)
+
+struct smu_table {
+ uint64_t size;
+ uint32_t align;
+ uint8_t domain;
+ uint64_t mc_address;
+ void *cpu_addr;
+ struct amdgpu_bo *bo;
+
+};
+
struct smu_table_context
{
void *power_play_table;
uint32_t power_play_table_size;
+ struct smu_table *tables;
+ uint32_t table_count;
};
struct smu_context
@@ -44,6 +63,7 @@ struct smu_funcs
{
int (*init_microcode)(struct smu_context *smu);
int (*init_smc_tables)(struct smu_context *smu);
+ int (*fini_smc_tables)(struct smu_context *smu);
int (*init_power)(struct smu_context *smu);
int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
@@ -69,6 +89,8 @@ struct smu_funcs
((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
#define smu_init_smc_tables(smu) \
((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+#define smu_fini_smc_tables(smu) \
+ ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
#define smu_init_power(smu) \
((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
#define smu_load_microcode(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index efc3e4b..a2794ce 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -234,6 +234,47 @@ static int smu_v11_0_read_pptable_from_vbios(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_init_smc_tables(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = NULL;
+
+ if (smu_table->tables || smu_table->table_count != 0)
+ return -EINVAL;
+
+ tables = kcalloc(TABLE_COUNT, sizeof(struct smu_table), GFP_KERNEL);
+ if (!tables)
+ return -ENOMEM;
+
+ smu_table->tables = tables;
+ smu_table->table_count = TABLE_COUNT;
+
+ SMU_TABLE_INIT(tables, TABLE_PPTABLE, sizeof(PPTable_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, TABLE_WATERMARKS, sizeof(Watermarks_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+
+ return 0;
+}
+
+static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ if (!smu_table->tables || smu_table->table_count == 0)
+ return -EINVAL;
+
+ kfree(smu_table->tables);
+ smu_table->tables = NULL;
+ smu_table->table_count = 0;
+
+ return 0;
+
+}
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -242,6 +283,8 @@ static const struct smu_funcs smu_v11_0_funcs = {
.send_smc_msg = smu_v11_0_send_msg,
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
.read_pptable_from_vbios = smu_v11_0_read_pptable_from_vbios,
+ .init_smc_tables = smu_v11_0_init_smc_tables,
+ .fini_smc_tables = smu_v11_0_fini_smc_tables,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 036/138] drm/amd/powerplay: implement smu dpm context functions for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (34 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 035/138] drm/amd/powerplay: implement smu_init[fini]_smc_tables " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 037/138] drm/amd/powerplay: implement smu_init[fini]_power function " Huang Rui
` (102 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements smu dpm context functions for smu v11.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++++
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 26 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 ++++++++++++++++++++++++++
3 files changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 16f11a4..0fce87c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -49,6 +49,11 @@ struct smu_table_context
uint32_t table_count;
};
+struct smu_dpm_context {
+ void *dpm_context;
+ uint32_t dpm_context_size;
+};
+
struct smu_context
{
struct amdgpu_device *adev;
@@ -57,6 +62,7 @@ struct smu_context
struct mutex mutex;
struct smu_table_context smu_table;
+ struct smu_dpm_context smu_dpm;
};
struct smu_funcs
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 6ba5bde..c7fccce 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -36,6 +36,32 @@
#define smnMP0_FW_INTF 0x30101c0
#define smnMP1_PUB_CTRL 0x3010b14
+
+struct smu_11_0_dpm_table {
+ uint32_t min; /* MHz */
+ uint32_t max; /* MHz */
+};
+
+struct smu_11_0_dpm_tables {
+ struct smu_11_0_dpm_table soc_table;
+ struct smu_11_0_dpm_table gfx_table;
+ struct smu_11_0_dpm_table uclk_table;
+ struct smu_11_0_dpm_table eclk_table;
+ struct smu_11_0_dpm_table vclk_table;
+ struct smu_11_0_dpm_table dclk_table;
+ struct smu_11_0_dpm_table dcef_table;
+ struct smu_11_0_dpm_table pixel_table;
+ struct smu_11_0_dpm_table display_table;
+ struct smu_11_0_dpm_table phy_table;
+ struct smu_11_0_dpm_table fclk_table;
+};
+
+struct smu_11_0_dpm_context {
+ struct smu_11_0_dpm_tables dpm_tables;
+ uint32_t workload_policy_mask;
+ uint32_t dcef_min_ds_clk;
+};
+
void smu_v11_0_set_smu_funcs(struct smu_context *smu);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index a2794ce..64125ee 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -234,10 +234,40 @@ static int smu_v11_0_read_pptable_from_vbios(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_init_dpm_context(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
+ return -EINVAL;
+
+ smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), GFP_KERNEL);
+ if (!smu_dpm->dpm_context)
+ return -ENOMEM;
+ smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
+
+ return 0;
+}
+
+static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
+ return -EINVAL;
+
+ kfree(smu_dpm->dpm_context);
+ smu_dpm->dpm_context = NULL;
+ smu_dpm->dpm_context_size = 0;
+
+ return 0;
+}
+
static int smu_v11_0_init_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *tables = NULL;
+ int ret = 0;
if (smu_table->tables || smu_table->table_count != 0)
return -EINVAL;
@@ -258,12 +288,17 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
SMU_TABLE_INIT(tables, TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ ret = smu_v11_0_init_dpm_context(smu);
+ if (ret)
+ return ret;
+
return 0;
}
static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
+ int ret = 0;
if (!smu_table->tables || smu_table->table_count == 0)
return -EINVAL;
@@ -272,6 +307,9 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
smu_table->tables = NULL;
smu_table->table_count = 0;
+ ret = smu_v11_0_fini_dpm_context(smu);
+ if (ret)
+ return ret;
return 0;
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 037/138] drm/amd/powerplay: implement smu_init[fini]_power function for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (35 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 036/138] drm/amd/powerplay: implement smu dpm context functions " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 038/138] drm/amd/powerplay: implement smu_init(fini)_fb_allocations function Huang Rui
` (101 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements smu_init[fini]_power function for smu v11.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 +++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +++++++
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 14 +++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 33 ++++++++++++++++++++++++++
4 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f79a125..b275139 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -167,6 +167,12 @@ static int smu_sw_fini(void *handle)
return ret;
}
+ ret = smu_fini_power(smu);
+ if (ret) {
+ pr_err("Failed to init smu_fini_power!\n");
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 0fce87c..a12af78 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -54,6 +54,11 @@ struct smu_dpm_context {
uint32_t dpm_context_size;
};
+struct smu_power_context {
+ void *power_context;
+ uint32_t power_context_size;
+};
+
struct smu_context
{
struct amdgpu_device *adev;
@@ -63,6 +68,7 @@ struct smu_context
struct smu_table_context smu_table;
struct smu_dpm_context smu_dpm;
+ struct smu_power_context smu_power;
};
struct smu_funcs
@@ -71,6 +77,7 @@ struct smu_funcs
int (*init_smc_tables)(struct smu_context *smu);
int (*fini_smc_tables)(struct smu_context *smu);
int (*init_power)(struct smu_context *smu);
+ int (*fini_power)(struct smu_context *smu);
int (*load_microcode)(struct smu_context *smu);
int (*check_fw_status)(struct smu_context *smu);
int (*read_pptable_from_vbios)(struct smu_context *smu);
@@ -99,6 +106,8 @@ struct smu_funcs
((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
#define smu_init_power(smu) \
((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+#define smu_fini_power(smu) \
+ ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
#define smu_load_microcode(smu) \
((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
#define smu_check_fw_status(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index c7fccce..2853ab7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -62,6 +62,20 @@ struct smu_11_0_dpm_context {
uint32_t dcef_min_ds_clk;
};
+enum smu_11_0_power_state {
+ SMU_11_0_POWER_STATE__D0 = 0,
+ SMU_11_0_POWER_STATE__D1,
+ SMU_11_0_POWER_STATE__D3, /* Sleep*/
+ SMU_11_0_POWER_STATE__D4, /* Hibernate*/
+ SMU_11_0_POWER_STATE__D5, /* Power off*/
+};
+
+struct smu_11_0_power_context {
+ uint32_t power_source;
+ uint8_t in_power_limit_boost_mode;
+ enum smu_11_0_power_state power_state;
+};
+
void smu_v11_0_set_smu_funcs(struct smu_context *smu);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 64125ee..ff8a32d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -313,6 +313,37 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
return 0;
}
+
+static int smu_v11_0_init_power(struct smu_context *smu)
+{
+ struct smu_power_context *smu_power = &smu->smu_power;
+
+ if (smu_power->power_context || smu_power->power_context_size != 0)
+ return -EINVAL;
+
+ smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
+ GFP_KERNEL);
+ if (!smu_power->power_context)
+ return -ENOMEM;
+ smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
+
+ return 0;
+}
+
+static int smu_v11_0_fini_power(struct smu_context *smu)
+{
+ struct smu_power_context *smu_power = &smu->smu_power;
+
+ if (!smu_power->power_context || smu_power->power_context_size == 0)
+ return -EINVAL;
+
+ kfree(smu_power->power_context);
+ smu_power->power_context = NULL;
+ smu_power->power_context_size = 0;
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -323,6 +354,8 @@ static const struct smu_funcs smu_v11_0_funcs = {
.read_pptable_from_vbios = smu_v11_0_read_pptable_from_vbios,
.init_smc_tables = smu_v11_0_init_smc_tables,
.fini_smc_tables = smu_v11_0_fini_smc_tables,
+ .init_power = smu_v11_0_init_power,
+ .fini_power = smu_v11_0_fini_power,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 038/138] drm/amd/powerplay: implement smu_init(fini)_fb_allocations function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (36 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 037/138] drm/amd/powerplay: implement smu_init[fini]_power function " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 039/138] drm/amd/powerplay: remove header of smu_v11_0_pptable Huang Rui
` (100 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements smu_init_fb_allocations/smu_fini_fb_allocations function
for smu to reserve the BOs for smc tables.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 60 +++++++++++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b275139..ef377ef 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -178,10 +178,63 @@ static int smu_sw_fini(void *handle)
static int smu_init_fb_allocations(struct smu_context *smu)
{
- /* TODO */
+ struct amdgpu_device *adev = smu->adev;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = smu_table->tables;
+ uint32_t table_count = smu_table->table_count;
+ uint32_t i = 0;
+ int32_t ret = 0;
+
+ if (table_count <= 0)
+ return -EINVAL;
+
+ for (i = 0 ; i < table_count; i++) {
+ if (tables[i].size == 0)
+ continue;
+ ret = amdgpu_bo_create_kernel(adev,
+ tables[i].size,
+ tables[i].align,
+ tables[i].domain,
+ &tables[i].bo,
+ &tables[i].mc_address,
+ &tables[i].cpu_addr);
+ if (ret)
+ goto failed;
+ }
+
return 0;
+failed:
+ for (; i > 0; i--) {
+ if (tables[i].size == 0)
+ continue;
+ amdgpu_bo_free_kernel(&tables[i].bo,
+ &tables[i].mc_address,
+ &tables[i].cpu_addr);
+
+ }
+ return ret;
}
+static int smu_fini_fb_allocations(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = smu_table->tables;
+ uint32_t table_count = smu_table->table_count;
+ uint32_t i = 0;
+
+ if (table_count == 0 || tables == NULL)
+ return -EINVAL;
+
+ for (i = 0 ; i < table_count; i++) {
+ if (tables[i].size == 0)
+ continue;
+ amdgpu_bo_free_kernel(&tables[i].bo,
+ &tables[i].mc_address,
+ &tables[i].cpu_addr);
+ }
+
+ return 0;
+}
static int smu_smc_table_hw_init(struct smu_context *smu)
{
int ret;
@@ -329,10 +382,15 @@ static int smu_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
+ int ret = 0;
if (adev->asic_type < CHIP_VEGA20)
return -EINVAL;
+ ret = smu_fini_fb_allocations(smu);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 039/138] drm/amd/powerplay: remove header of smu_v11_0_pptable
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (37 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 038/138] drm/amd/powerplay: implement smu_init(fini)_fb_allocations function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 040/138] drm/amd/powerplay: update pptable header for smu11 Huang Rui
` (99 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
different ASICs have different pptables, so the header will move
to asic source code to implement.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <Ray.Huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ff8a32d..a68d0a0 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -30,7 +30,6 @@
#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
#include "soc15_common.h"
-#include "smu_v11_0_pptable.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
@@ -218,7 +217,7 @@ static int smu_v11_0_read_pptable_from_vbios(struct smu_context *smu)
int ret, index;
uint16_t size;
uint8_t frev, crev;
- struct smu_11_0_powerplay_table *table;
+ void *table;
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
powerplayinfo);
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 040/138] drm/amd/powerplay: update pptable header for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (38 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 039/138] drm/amd/powerplay: remove header of smu_v11_0_pptable Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 041/138] drm/amd/powerplay: add data structure of bootup values Huang Rui
` (98 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch updates pptable header for smu v11.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
.../gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h | 30 +++++++++++-----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
index 45aed6f..e8a654b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
@@ -18,7 +18,6 @@
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
- *
*/
#ifndef SMU_11_0_PPTABLE_H
#define SMU_11_0_PPTABLE_H
@@ -41,20 +40,21 @@
#define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION 0x0100
enum SMU_11_0_ODFEATURE_ID {
- SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 0, //GFXCLK Limit feature
- SMU_11_0_ODFEATURE_GFXCLK_CURVE, //GFXCLK Curve feature
- SMU_11_0_ODFEATURE_UCLK_MAX, //UCLK Limit feature
- SMU_11_0_ODFEATURE_POWER_LIMIT, //Power Limit feature
- SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature
- SMU_11_0_ODFEATURE_FAN_SPEED_MIN, //Minimum Fan Speed feature
- SMU_11_0_ODFEATURE_TEMPERATURE_FAN, //Fan Target Temperature Limit feature
- SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature
- SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE, //AC Timing Tuning feature
- SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL, //Zero RPM feature
- SMU_11_0_ODFEATURE_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature
- SMU_11_0_ODFEATURE_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature
- SMU_11_0_ODFEATURE_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature
- SMU_11_0_ODFEATURE_COUNT,
+ SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 1 << 0, //GFXCLK Limit feature
+ SMU_11_0_ODFEATURE_GFXCLK_CURVE = 1 << 1, //GFXCLK Curve feature
+ SMU_11_0_ODFEATURE_UCLK_MAX = 1 << 2, //UCLK Limit feature
+ SMU_11_0_ODFEATURE_POWER_LIMIT = 1 << 3, //Power Limit feature
+ SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << 4, //Fan Acoustic RPM feature
+ SMU_11_0_ODFEATURE_FAN_SPEED_MIN = 1 << 5, //Minimum Fan Speed feature
+ SMU_11_0_ODFEATURE_TEMPERATURE_FAN = 1 << 6, //Fan Target Temperature Limit feature
+ SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << 7, //Operating Temperature Limit feature
+ SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << 8, //AC Timing Tuning feature
+ SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << 9, //Zero RPM feature
+ SMU_11_0_ODFEATURE_AUTO_UV_ENGINE = 1 << 10, //Auto Under Volt GFXCLK feature
+ SMU_11_0_ODFEATURE_AUTO_OC_ENGINE = 1 << 11, //Auto Over Clock GFXCLK feature
+ SMU_11_0_ODFEATURE_AUTO_OC_MEMORY = 1 << 12, //Auto Over Clock MCLK feature
+ SMU_11_0_ODFEATURE_FAN_CURVE = 1 << 13, //VICTOR TODO
+ SMU_11_0_ODFEATURE_COUNT = 14,
};
#define SMU_11_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 041/138] drm/amd/powerplay: add data structure of bootup values
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (39 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 040/138] drm/amd/powerplay: update pptable header for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 042/138] drm/amd/powerplay: implement get_vbios_bootup_values function for smu11 (v2) Huang Rui
` (97 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds data structures for bootup values.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a12af78..6d0db61 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -38,13 +38,29 @@ struct smu_table {
uint64_t mc_address;
void *cpu_addr;
struct amdgpu_bo *bo;
+};
+struct smu_bios_boot_up_values
+{
+ uint32_t revision;
+ uint32_t gfxclk;
+ uint32_t uclk;
+ uint32_t socclk;
+ uint32_t dcefclk;
+ uint16_t vddc;
+ uint16_t vddci;
+ uint16_t mvddc;
+ uint16_t vdd_gfx;
+ uint8_t cooling_id;
+ uint32_t pp_table_id;
};
struct smu_table_context
{
void *power_play_table;
uint32_t power_play_table_size;
+
+ struct smu_bios_boot_up_values boot_values;
struct smu_table *tables;
uint32_t table_count;
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 042/138] drm/amd/powerplay: implement get_vbios_bootup_values function for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (40 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 041/138] drm/amd/powerplay: add data structure of bootup values Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 043/138] drm/amd/powerplay: implement get_clk_info_from_vbios " Huang Rui
` (96 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch implements get_vbios_bootup_values function for smu11 to fetach
firmwareinfo member from atombios.
v2: use switch statement based on the content revision (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 59 +++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index a68d0a0..f036313 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -343,6 +343,64 @@ static int smu_v11_0_fini_power(struct smu_context *smu)
return 0;
}
+int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
+{
+ int ret, index;
+ uint16_t size;
+ uint8_t frev, crev;
+ struct atom_common_table_header *header;
+ struct atom_firmware_info_v3_3 *v_3_3;
+ struct atom_firmware_info_v3_1 *v_3_1;
+
+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ firmwareinfo);
+
+ ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
+ (uint8_t **)&header);
+ if (ret)
+ return ret;
+
+ if (header->format_revision != 3) {
+ pr_err("unknown atom_firmware_info version! for smu11\n");
+ return -EINVAL;
+ }
+
+ switch (header->content_revision) {
+ case 0:
+ case 1:
+ case 2:
+ v_3_1 = (struct atom_firmware_info_v3_1 *)header;
+ smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
+ smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
+ smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
+ smu->smu_table.boot_values.socclk = 0;
+ smu->smu_table.boot_values.dcefclk = 0;
+ smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
+ smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
+ smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
+ smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
+ smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
+ smu->smu_table.boot_values.pp_table_id = 0;
+ break;
+ case 3:
+ default:
+ v_3_3 = (struct atom_firmware_info_v3_3 *)header;
+ smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
+ smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
+ smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
+ smu->smu_table.boot_values.socclk = 0;
+ smu->smu_table.boot_values.dcefclk = 0;
+ smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
+ smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
+ smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
+ smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
+ smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
+ smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
+ }
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -355,6 +413,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.fini_smc_tables = smu_v11_0_fini_smc_tables,
.init_power = smu_v11_0_init_power,
.fini_power = smu_v11_0_fini_power,
+ .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 043/138] drm/amd/powerplay: implement get_clk_info_from_vbios function for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (41 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 042/138] drm/amd/powerplay: implement get_vbios_bootup_values function for smu11 (v2) Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 044/138] drm/amd/powerplay: implement smu_alloc[free]_memory pool function Huang Rui
` (95 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch implements the get_clk_info_from_vbios function for smu11.
We can do execute_vbios_cmd_table to fetch the clk value from vbios.
v2: use the proper cpu_to_le[32|16]() and le[32|16]_to_cpu() macros to handle
endianness. (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39 ++++++++++++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index ef377ef..f31b628 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -248,10 +248,18 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_get_clk_info_from_vbios(smu);
+ if (ret)
+ return ret;
+
/*
* check if the format_revision in vbios is up to pptable header
* version, and the structure size is not 0.
*/
+ ret = smu_get_clk_info_from_vbios(smu);
+ if (ret)
+ return ret;
+
ret = smu_check_pptable(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 6d0db61..57572ff4d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -98,6 +98,7 @@ struct smu_funcs
int (*check_fw_status)(struct smu_context *smu);
int (*read_pptable_from_vbios)(struct smu_context *smu);
int (*get_vbios_bootup_values)(struct smu_context *smu);
+ int (*get_clk_info_from_vbios)(struct smu_context *smu);
int (*check_pptable)(struct smu_context *smu);
int (*parse_pptable)(struct smu_context *smu);
int (*populate_smc_pptable)(struct smu_context *smu);
@@ -132,6 +133,8 @@ struct smu_funcs
((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+#define smu_get_clk_info_from_vbios(smu) \
+ ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
#define smu_check_pptable(smu) \
((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f036313..adae5a7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -30,6 +30,7 @@
#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
#include "soc15_common.h"
+#include "atom.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
@@ -401,6 +402,43 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+{
+ int ret, index;
+ struct amdgpu_device *adev = smu->adev;
+ struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
+ struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
+
+ input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
+ input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+ index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+ getsmuclockinfo);
+
+ ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+ (uint32_t *)&input);
+ if (ret)
+ return -EINVAL;
+
+ output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+ smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+ memset(&input, 0, sizeof(input));
+ input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
+ input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+ index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+ getsmuclockinfo);
+
+ ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+ (uint32_t *)&input);
+ if (ret)
+ return -EINVAL;
+
+ output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+ smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -414,6 +452,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.init_power = smu_v11_0_init_power,
.fini_power = smu_v11_0_fini_power,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+ .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 044/138] drm/amd/powerplay: implement smu_alloc[free]_memory pool function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (42 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 043/138] drm/amd/powerplay: implement get_clk_info_from_vbios " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 045/138] drm/amd/powerplay: implement notify_memory_pool_location function for smu11 Huang Rui
` (94 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements smu_alloc[free]_memory pool function to reserve the memory
pool bo.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 55 +++++++++++++++++++++++++-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 11 ++++++
2 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f31b628..926d0f8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -137,6 +137,8 @@ static int smu_sw_init(void *handle)
if (adev->asic_type < CHIP_VEGA20)
return -EINVAL;
+ smu->pool_size = adev->pm.smu_prv_buffer_size;
+
ret = smu_init_microcode(smu);
if (ret) {
pr_err("Failed to load smu firmware!\n");
@@ -333,9 +335,56 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
*/
static int smu_alloc_memory_pool(struct smu_context *smu)
{
- return 0;
+ struct amdgpu_device *adev = smu->adev;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *memory_pool = &smu_table->memory_pool;
+ uint64_t pool_size = smu->pool_size;
+ int ret = 0;
+
+ if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
+ return ret;
+
+ memory_pool->size = pool_size;
+ memory_pool->align = PAGE_SIZE;
+ memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
+
+ switch (pool_size) {
+ case SMU_MEMORY_POOL_SIZE_256_MB:
+ case SMU_MEMORY_POOL_SIZE_512_MB:
+ case SMU_MEMORY_POOL_SIZE_1_GB:
+ case SMU_MEMORY_POOL_SIZE_2_GB:
+ ret = amdgpu_bo_create_kernel(adev,
+ memory_pool->size,
+ memory_pool->align,
+ memory_pool->domain,
+ &memory_pool->bo,
+ &memory_pool->mc_address,
+ &memory_pool->cpu_addr);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
}
+static int smu_free_memory_pool(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *memory_pool = &smu_table->memory_pool;
+ int ret = 0;
+
+ if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
+ return ret;
+
+ amdgpu_bo_free_kernel(&memory_pool->bo,
+ &memory_pool->mc_address,
+ &memory_pool->cpu_addr);
+
+ memset(memory_pool, 0, sizeof(struct smu_table));
+
+ return ret;
+}
static int smu_hw_init(void *handle)
{
int ret;
@@ -399,6 +448,10 @@ static int smu_hw_fini(void *handle)
if (ret)
return ret;
+ ret = smu_free_memory_pool(smu);
+ if (ret)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 57572ff4d..dab1011 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -24,6 +24,15 @@
#include "amdgpu.h"
+enum smu_memory_pool_size
+{
+ SMU_MEMORY_POOL_SIZE_ZERO = 0,
+ SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
+ SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
+ SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
+ SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
+};
+
#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
do { \
tables[table_id].size = s; \
@@ -63,6 +72,7 @@ struct smu_table_context
struct smu_bios_boot_up_values boot_values;
struct smu_table *tables;
uint32_t table_count;
+ struct smu_table memory_pool;
};
struct smu_dpm_context {
@@ -81,6 +91,7 @@ struct smu_context
const struct smu_funcs *funcs;
struct mutex mutex;
+ uint64_t pool_size;
struct smu_table_context smu_table;
struct smu_dpm_context smu_dpm;
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 045/138] drm/amd/powerplay: implement notify_memory_pool_location function for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (43 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 044/138] drm/amd/powerplay: implement smu_alloc[free]_memory pool function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 046/138] drm/amd/powerplay: add vega20 pptable function file Huang Rui
` (93 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements the notify_memory_pool_location function to send memory
address to smc for dram logging.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 47 +++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index adae5a7..810435d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -439,6 +439,52 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *memory_pool = &smu_table->memory_pool;
+ int ret = 0;
+ uint64_t address;
+ uint32_t address_low, address_high;
+
+ if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
+ return ret;
+
+ address = (uint64_t)memory_pool->cpu_addr;
+ address_high = (uint32_t)upper_32_bits(address);
+ address_low = (uint32_t)lower_32_bits(address);
+
+ ret = smu_send_smc_msg_with_param(smu,
+ PPSMC_MSG_SetSystemVirtualDramAddrHigh,
+ address_high);
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu,
+ PPSMC_MSG_SetSystemVirtualDramAddrLow,
+ address_low);
+ if (ret)
+ return ret;
+
+ address = memory_pool->mc_address;
+ address_high = (uint32_t)upper_32_bits(address);
+ address_low = (uint32_t)lower_32_bits(address);
+
+ ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_DramLogSetDramAddrHigh,
+ address_high);
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_DramLogSetDramAddrLow,
+ address_low);
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_DramLogSetDramSize,
+ (uint32_t)memory_pool->size);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -453,6 +499,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.fini_power = smu_v11_0_fini_power,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+ .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 046/138] drm/amd/powerplay: add vega20 pptable function file
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (44 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 045/138] drm/amd/powerplay: implement notify_memory_pool_location function for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 047/138] drm/amd/powerplay: add function to parse pptable for smu11 Huang Rui
` (92 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds the vega20_ppt.c to support ATOM_Vega20_POWERPLAYTABLE format
for vega20 on smu11. It will be used to implement to asic specific pptable
helpers.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 11 ++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 51 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 28 ++++++++++++++
6 files changed, 97 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/vega20_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/vega20_ppt.h
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
index 1221da8..ec87b34 100644
--- a/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
include $(AMD_POWERPLAY)
-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o
+POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o
AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 926d0f8..c853166 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -48,16 +48,11 @@ static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
- int ret;
-
- ret = smu_set_funcs(adev);
- if (ret)
- return ret;
smu->adev = adev;
mutex_init(&smu->mutex);
- return 0;
+ return smu_set_funcs(adev);
}
int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index dab1011..437d0ad 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -90,6 +90,7 @@ struct smu_context
struct amdgpu_device *adev;
const struct smu_funcs *funcs;
+ const struct pptable_funcs *ppt_funcs;
struct mutex mutex;
uint64_t pool_size;
@@ -98,6 +99,10 @@ struct smu_context
struct smu_power_context smu_power;
};
+struct pptable_funcs {
+ int (*store_powerplay_table)(struct smu_context *smu);
+};
+
struct smu_funcs
{
int (*init_microcode)(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 810435d..65e5641 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -31,6 +31,7 @@
#include "smu11_driver_if.h"
#include "soc15_common.h"
#include "atom.h"
+#include "vega20_ppt.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
@@ -504,5 +505,15 @@ static const struct smu_funcs smu_v11_0_funcs = {
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->funcs = &smu_v11_0_funcs;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ vega20_set_ppt_funcs(smu);
+ break;
+ default:
+ pr_warn("Unknow asic for smu11\n");
+ }
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
new file mode 100644
index 0000000..7522cc7
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "pp_debug.h"
+#include <linux/firmware.h>
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "smu_v11_0.h"
+#include "smu_v11_0_ppsmc.h"
+#include "smu11_driver_if.h"
+#include "soc15_common.h"
+#include "atom.h"
+#include "vega20_ppt.h"
+#include "vega20_pptable.h"
+#include "vega20_ppt.h"
+
+static int vega20_store_powerplay_table(struct smu_context *smu)
+{
+ return 0;
+}
+
+static const struct pptable_funcs vega20_ppt_funcs = {
+ .store_powerplay_table = vega20_store_powerplay_table,
+};
+
+void vega20_set_ppt_funcs(struct smu_context *smu)
+{
+ smu->ppt_funcs = &vega20_ppt_funcs;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
new file mode 100644
index 0000000..b597596
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __VEGA20_PPT_H__
+#define __VEGA20_PPT_H__
+
+extern void vega20_set_ppt_funcs(struct smu_context *smu);
+
+#endif
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 047/138] drm/amd/powerplay: add function to parse pptable for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (45 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 046/138] drm/amd/powerplay: add vega20 pptable function file Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 048/138] drm/amd/powerplay: add function to check " Huang Rui
` (91 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_parse_pptable function for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 ++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 11 +++++++++++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 437d0ad..c6774e35 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -70,6 +70,7 @@ struct smu_table_context
uint32_t power_play_table_size;
struct smu_bios_boot_up_values boot_values;
+ void *driver_pptable;
struct smu_table *tables;
uint32_t table_count;
struct smu_table memory_pool;
@@ -177,6 +178,8 @@ struct smu_funcs
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+#define smu_store_powerplay_table(smu) \
+ ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 65e5641..826fd6e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -486,6 +486,25 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_parse_pptable(struct smu_context *smu)
+{
+ int ret;
+
+ struct smu_table_context *table_context = &smu->smu_table;
+
+ if (table_context->driver_pptable)
+ return -EINVAL;
+
+ table_context->driver_pptable = kzalloc(sizeof(PPTable_t), GFP_KERNEL);
+
+ if (!table_context->driver_pptable)
+ return -ENOMEM;
+
+ ret = smu_store_powerplay_table(smu);
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -501,6 +520,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .parse_pptable = smu_v11_0_parse_pptable,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 7522cc7..292f18c 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -38,6 +38,17 @@
static int vega20_store_powerplay_table(struct smu_context *smu)
{
+ ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
+ struct smu_table_context *table_context = &smu->smu_table;
+
+ if (!table_context->power_play_table)
+ return -EINVAL;
+
+ powerplay_table = table_context->power_play_table;
+
+ memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
+ sizeof(PPTable_t));
+
return 0;
}
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 048/138] drm/amd/powerplay: add function to check pptable for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (46 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 047/138] drm/amd/powerplay: add function to parse pptable for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 049/138] drm/amd/powerplay: update hw fini function to relase some memory Huang Rui
` (90 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_check_pptable function for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 9 +++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 21 +++++++++++++++++++++
3 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c6774e35..a034a15 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -102,6 +102,7 @@ struct smu_context
struct pptable_funcs {
int (*store_powerplay_table)(struct smu_context *smu);
+ int (*check_powerplay_table)(struct smu_context *smu);
};
struct smu_funcs
@@ -180,6 +181,8 @@ struct smu_funcs
((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
+#define smu_check_powerplay_table(smu) \
+ ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 826fd6e..f24cd7d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -486,6 +486,14 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_check_pptable(struct smu_context *smu)
+{
+ int ret;
+
+ ret = smu_check_powerplay_table(smu);
+ return ret;
+}
+
static int smu_v11_0_parse_pptable(struct smu_context *smu)
{
int ret;
@@ -520,6 +528,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ .check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
};
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 292f18c..7bc3e4e 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -52,8 +52,29 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
return 0;
}
+static int vega20_check_powerplay_table(struct smu_context *smu)
+{
+ ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
+ struct smu_table_context *table_context = &smu->smu_table;
+
+ powerplay_table = table_context->power_play_table;
+
+ if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
+ pr_err("Unsupported PPTable format!");
+ return -EINVAL;
+ }
+
+ if (!powerplay_table->sHeader.structuresize) {
+ pr_err("Invalid PowerPlay Table!");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.store_powerplay_table = vega20_store_powerplay_table,
+ .check_powerplay_table = vega20_check_powerplay_table,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 049/138] drm/amd/powerplay: update hw fini function to relase some memory
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (47 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 048/138] drm/amd/powerplay: add function to check " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 050/138] drm/amd/powerplay: add function to populate smc pptable for smu11 Huang Rui
` (89 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Release memory of table_context->driver_pptable and
table_context->ppt_information when smu hw fini.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c853166..e4da464 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -434,11 +434,16 @@ static int smu_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
+ struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
if (adev->asic_type < CHIP_VEGA20)
return -EINVAL;
+ if (!table_context->driver_pptable)
+ return -EINVAL;
+ kfree(table_context->driver_pptable);
+
ret = smu_fini_fb_allocations(smu);
if (ret)
return ret;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 050/138] drm/amd/powerplay: add function to populate smc pptable for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (48 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 049/138] drm/amd/powerplay: update hw fini function to relase some memory Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 051/138] drm/amd/powerplay: add function to write pptable for smu11 (v2) Huang Rui
` (88 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_populate_smc_pptable function for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 42 +++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f24cd7d..cea8651 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -513,6 +513,47 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ PPTable_t *driver_ppt = (PPTable_t *)&(smu->smu_table.tables[TABLE_PPTABLE]);
+ struct smu_11_0_dpm_context *dpm_context = (struct smu_11_0_dpm_context *)smu_dpm->dpm_context;
+
+ if (dpm_context && driver_ppt) {
+ dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
+ dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
+ dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
+ dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
+ dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
+ dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
+ dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
+ dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
+ dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
+
+ dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+ dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -530,6 +571,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
.check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
+ .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 051/138] drm/amd/powerplay: add function to write pptable for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (49 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 050/138] drm/amd/powerplay: add function to populate smc pptable for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 052/138] drm/amd/powerplay: add function to set min dcef deep sleep " Huang Rui
` (87 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_write_pptable and smu_v11_0_copy_table_to_smc function for smu11.
v2: fix the build warning. (Ray)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 60 +++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index cea8651..742876c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -554,6 +554,65 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
return -EINVAL;
}
+static int smu_v11_0_copy_table_to_smc(struct smu_context *smu,
+ uint32_t table_id)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_table *driver_pptable = &smu->smu_table.tables[table_id];
+ int ret = 0;
+
+ if (table_id >= TABLE_COUNT) {
+ pr_err("Invalid SMU Table ID for smu11!");
+ return -EINVAL;
+ }
+
+ if (!driver_pptable->cpu_addr) {
+ pr_err("Invalid virtual address for smu11!");
+ return -EINVAL;
+ }
+ if (!driver_pptable->mc_address) {
+ pr_err("Invalid MC address for smu11!");
+ return -EINVAL;
+ }
+ if (!driver_pptable->size) {
+ pr_err("Invalid SMU Table size for smu11!");
+ return -EINVAL;
+ }
+
+ memcpy(driver_pptable->cpu_addr, table_context->driver_pptable,
+ driver_pptable->size);
+
+ ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_SetDriverDramAddrHigh,
+ upper_32_bits(driver_pptable->mc_address));
+ if (ret) {
+ pr_err("[CopyTableToSMC] Attempt to Set Dram Addr High Failed!");
+ return ret;
+ }
+ ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_SetDriverDramAddrLow,
+ lower_32_bits(driver_pptable->mc_address));
+ if (ret) {
+ pr_err("[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!");
+ return ret;
+ }
+ ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_TransferTableDram2Smu,
+ table_id);
+ if (ret) {
+ pr_err("[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int smu_v11_0_write_pptable(struct smu_context *smu)
+{
+ int ret = 0;
+
+ ret = smu_v11_0_copy_table_to_smc(smu, TABLE_PPTABLE);
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -572,6 +631,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
+ .write_pptable = smu_v11_0_write_pptable,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 052/138] drm/amd/powerplay: add function to set min dcef deep sleep for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (50 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 051/138] drm/amd/powerplay: add function to write pptable for smu11 (v2) Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 053/138] drm/amd/powerplay: add function to set tool table location " Huang Rui
` (86 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_set_min_dcef_deep_sleep function for smu11.
v2: fix coding error about set_min_dcef_deep_sleep (Kevin)
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 742876c..8553c47 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -613,6 +613,23 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+{
+ int ret = 0;
+ struct smu_table_context *table_context = &smu->smu_table;
+
+ if (!table_context)
+ return -EINVAL;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ PPSMC_MSG_SetMinDeepSleepDcefclk,
+ table_context->boot_values.dcefclk / 100);
+ if (ret)
+ pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -632,6 +649,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.parse_pptable = smu_v11_0_parse_pptable,
.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
.write_pptable = smu_v11_0_write_pptable,
+ .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 053/138] drm/amd/powerplay: add function to set tool table location for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (51 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 052/138] drm/amd/powerplay: add function to set min dcef deep sleep " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 054/138] drm/amd/powerplay: add enum smu_msg_type to header Huang Rui
` (85 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_set_tool_table_location function for smu11.
v2: fix the missed TABLE_PMSTATUSLOG bo creation which caused AGM hung. (Ray)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 8553c47..c0ff55f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -41,6 +41,8 @@
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
+#define SMU11_TOOL_SIZE 0x19000
+
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
{
@@ -288,6 +290,8 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM);
ret = smu_v11_0_init_dpm_context(smu);
if (ret)
@@ -630,6 +634,24 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+{
+ int ret = 0;
+ struct smu_table *tool_table = &smu->smu_table.tables[TABLE_PMSTATUSLOG];
+
+ if (tool_table->mc_address) {
+ ret = smu_send_smc_msg_with_param(smu,
+ PPSMC_MSG_SetToolsDramAddrHigh,
+ upper_32_bits(tool_table->mc_address));
+ if (!ret)
+ ret = smu_send_smc_msg_with_param(smu,
+ PPSMC_MSG_SetToolsDramAddrLow,
+ lower_32_bits(tool_table->mc_address));
+ }
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -650,6 +672,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
.write_pptable = smu_v11_0_write_pptable,
.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ .set_tool_table_location = smu_v11_0_set_tool_table_location,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 054/138] drm/amd/powerplay: add enum smu_msg_type to header
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (52 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 053/138] drm/amd/powerplay: add function to set tool table location " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 055/138] drm/amd/powerplay: implement smu vega20_message_map for vega20 Huang Rui
` (84 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
each asic with different message index,
add this header to help top level smu code to send message.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 89 ++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a034a15..b363741 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -24,6 +24,95 @@
#include "amdgpu.h"
+enum smu_message_type
+{
+ SMU_MSG_TestMessage = 0,
+ SMU_MSG_GetSmuVersion,
+ SMU_MSG_GetDriverIfVersion,
+ SMU_MSG_SetAllowedFeaturesMaskLow,
+ SMU_MSG_SetAllowedFeaturesMaskHigh,
+ SMU_MSG_EnableAllSmuFeatures,
+ SMU_MSG_DisableAllSmuFeatures,
+ SMU_MSG_EnableSmuFeaturesLow,
+ SMU_MSG_EnableSmuFeaturesHigh,
+ SMU_MSG_DisableSmuFeaturesLow,
+ SMU_MSG_DisableSmuFeaturesHigh,
+ SMU_MSG_GetEnabledSmuFeaturesLow,
+ SMU_MSG_GetEnabledSmuFeaturesHigh,
+ SMU_MSG_SetWorkloadMask,
+ SMU_MSG_SetPptLimit,
+ SMU_MSG_SetDriverDramAddrHigh,
+ SMU_MSG_SetDriverDramAddrLow,
+ SMU_MSG_SetToolsDramAddrHigh,
+ SMU_MSG_SetToolsDramAddrLow,
+ SMU_MSG_TransferTableSmu2Dram,
+ SMU_MSG_TransferTableDram2Smu,
+ SMU_MSG_UseDefaultPPTable,
+ SMU_MSG_UseBackupPPTable,
+ SMU_MSG_RunBtc,
+ SMU_MSG_RequestI2CBus,
+ SMU_MSG_ReleaseI2CBus,
+ SMU_MSG_SetFloorSocVoltage,
+ SMU_MSG_SoftReset,
+ SMU_MSG_StartBacoMonitor,
+ SMU_MSG_CancelBacoMonitor,
+ SMU_MSG_EnterBaco,
+ SMU_MSG_SetSoftMinByFreq,
+ SMU_MSG_SetSoftMaxByFreq,
+ SMU_MSG_SetHardMinByFreq,
+ SMU_MSG_SetHardMaxByFreq,
+ SMU_MSG_GetMinDpmFreq,
+ SMU_MSG_GetMaxDpmFreq,
+ SMU_MSG_GetDpmFreqByIndex,
+ SMU_MSG_GetDpmClockFreq,
+ SMU_MSG_GetSsVoltageByDpm,
+ SMU_MSG_SetMemoryChannelConfig,
+ SMU_MSG_SetGeminiMode,
+ SMU_MSG_SetGeminiApertureHigh,
+ SMU_MSG_SetGeminiApertureLow,
+ SMU_MSG_SetMinLinkDpmByIndex,
+ SMU_MSG_OverridePcieParameters,
+ SMU_MSG_OverDriveSetPercentage,
+ SMU_MSG_SetMinDeepSleepDcefclk,
+ SMU_MSG_ReenableAcDcInterrupt,
+ SMU_MSG_NotifyPowerSource,
+ SMU_MSG_SetUclkFastSwitch,
+ SMU_MSG_SetUclkDownHyst,
+ SMU_MSG_GfxDeviceDriverReset,
+ SMU_MSG_GetCurrentRpm,
+ SMU_MSG_SetVideoFps,
+ SMU_MSG_SetTjMax,
+ SMU_MSG_SetFanTemperatureTarget,
+ SMU_MSG_PrepareMp1ForUnload,
+ SMU_MSG_DramLogSetDramAddrHigh,
+ SMU_MSG_DramLogSetDramAddrLow,
+ SMU_MSG_DramLogSetDramSize,
+ SMU_MSG_SetFanMaxRpm,
+ SMU_MSG_SetFanMinPwm,
+ SMU_MSG_ConfigureGfxDidt,
+ SMU_MSG_NumOfDisplays,
+ SMU_MSG_RemoveMargins,
+ SMU_MSG_ReadSerialNumTop32,
+ SMU_MSG_ReadSerialNumBottom32,
+ SMU_MSG_SetSystemVirtualDramAddrHigh,
+ SMU_MSG_SetSystemVirtualDramAddrLow,
+ SMU_MSG_WaflTest,
+ SMU_MSG_SetFclkGfxClkRatio,
+ SMU_MSG_AllowGfxOff,
+ SMU_MSG_DisallowGfxOff,
+ SMU_MSG_GetPptLimit,
+ SMU_MSG_GetDcModeMaxDpmFreq,
+ SMU_MSG_GetDebugData,
+ SMU_MSG_SetXgmiMode,
+ SMU_MSG_RunAfllBtc,
+ SMU_MSG_ExitBaco,
+ SMU_MSG_PrepareMp1ForReset,
+ SMU_MSG_PrepareMp1ForShutdown,
+ SMU_MSG_SetMGpuFanBoostLimitRpm,
+ SMU_MSG_GetAVFSVoltageByDpm,
+ SMU_MSG_MAX_COUNT,
+};
+
enum smu_memory_pool_size
{
SMU_MEMORY_POOL_SIZE_ZERO = 0,
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 055/138] drm/amd/powerplay: implement smu vega20_message_map for vega20
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (53 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 054/138] drm/amd/powerplay: add enum smu_msg_type to header Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 056/138] drm/amd/powerplay: use virtual msg index to replace asic-related msg index Huang Rui
` (83 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements smu vega20_message_map to map the PPSMC messages from
smu11 to specific asic.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 101 ++++++++++++++++++++++++-
2 files changed, 103 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b363741..69832458 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -192,6 +192,7 @@ struct smu_context
struct pptable_funcs {
int (*store_powerplay_table)(struct smu_context *smu);
int (*check_powerplay_table)(struct smu_context *smu);
+ int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
};
struct smu_funcs
@@ -273,6 +274,9 @@ struct smu_funcs
#define smu_check_powerplay_table(smu) \
((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
+#define smu_msg_get_index(smu, msg) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
uint8_t **addr);
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 7bc3e4e..5e561ad 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -28,13 +28,109 @@
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
-#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
#include "soc15_common.h"
#include "atom.h"
#include "vega20_ppt.h"
#include "vega20_pptable.h"
-#include "vega20_ppt.h"
+#include "vega20_ppsmc.h"
+
+#define MSG_MAP(msg, index) \
+ [SMU_MSG_##msg] = index
+
+static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
+ MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
+ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
+ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
+ MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
+ MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
+ MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
+ MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
+ MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
+ MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
+ MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
+ MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
+ MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
+ MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
+ MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
+ MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
+ MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
+ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
+ MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
+ MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
+ MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
+ MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
+ MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
+ MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
+ MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
+ MSG_MAP(RequestI2CBus, PPSMC_MSG_RequestI2CBus),
+ MSG_MAP(ReleaseI2CBus, PPSMC_MSG_ReleaseI2CBus),
+ MSG_MAP(SetFloorSocVoltage, PPSMC_MSG_SetFloorSocVoltage),
+ MSG_MAP(SoftReset, PPSMC_MSG_SoftReset),
+ MSG_MAP(StartBacoMonitor, PPSMC_MSG_StartBacoMonitor),
+ MSG_MAP(CancelBacoMonitor, PPSMC_MSG_CancelBacoMonitor),
+ MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
+ MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
+ MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
+ MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
+ MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
+ MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
+ MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
+ MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
+ MSG_MAP(GetDpmClockFreq, PPSMC_MSG_GetDpmClockFreq),
+ MSG_MAP(GetSsVoltageByDpm, PPSMC_MSG_GetSsVoltageByDpm),
+ MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig),
+ MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
+ MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
+ MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
+ MSG_MAP(SetMinLinkDpmByIndex, PPSMC_MSG_SetMinLinkDpmByIndex),
+ MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
+ MSG_MAP(OverDriveSetPercentage, PPSMC_MSG_OverDriveSetPercentage),
+ MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk),
+ MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
+ MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
+ MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
+ MSG_MAP(SetUclkDownHyst, PPSMC_MSG_SetUclkDownHyst),
+ MSG_MAP(GetCurrentRpm, PPSMC_MSG_GetCurrentRpm),
+ MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
+ MSG_MAP(SetTjMax, PPSMC_MSG_SetTjMax),
+ MSG_MAP(SetFanTemperatureTarget, PPSMC_MSG_SetFanTemperatureTarget),
+ MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
+ MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
+ MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
+ MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
+ MSG_MAP(SetFanMaxRpm, PPSMC_MSG_SetFanMaxRpm),
+ MSG_MAP(SetFanMinPwm, PPSMC_MSG_SetFanMinPwm),
+ MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt),
+ MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays),
+ MSG_MAP(RemoveMargins, PPSMC_MSG_RemoveMargins),
+ MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32),
+ MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32),
+ MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
+ MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
+ MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
+ MSG_MAP(SetFclkGfxClkRatio, PPSMC_MSG_SetFclkGfxClkRatio),
+ MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
+ MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
+ MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
+ MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
+ MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
+ MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc),
+ MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
+ MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
+ MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
+ MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm),
+ MSG_MAP(GetAVFSVoltageByDpm, PPSMC_MSG_GetAVFSVoltageByDpm),
+};
+
+static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+{
+ if (index > SMU_MSG_MAX_COUNT || index > PPSMC_Message_Count)
+ return -EINVAL;
+ return vega20_message_map[index];
+
+}
static int vega20_store_powerplay_table(struct smu_context *smu)
{
@@ -75,6 +171,7 @@ static int vega20_check_powerplay_table(struct smu_context *smu)
static const struct pptable_funcs vega20_ppt_funcs = {
.store_powerplay_table = vega20_store_powerplay_table,
.check_powerplay_table = vega20_check_powerplay_table,
+ .get_smu_msg_index = vega20_get_smu_msg_index,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 056/138] drm/amd/powerplay: use virtual msg index to replace asic-related msg index
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (54 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 055/138] drm/amd/powerplay: implement smu vega20_message_map for vega20 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 057/138] drm/amd/powerplay: replace SMU_MSG_XXX with PPSMC_MSG_XXX message index for smu11 (v2) Huang Rui
` (82 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Using virtual msg index is able to support all ASIC specific message values on
one smu upper layer.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c0ff55f..ff1120a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -81,13 +81,17 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
{
struct amdgpu_device *adev = smu->adev;
- int ret = 0;
+ int ret = 0, index = 0;
+
+ index = smu_msg_get_index(smu, msg);
+ if (index < 0)
+ return index;
smu_v11_0_wait_for_response(smu);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
- smu_v11_0_send_msg_without_waiting(smu, msg);
+ smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
ret = smu_v11_0_wait_for_response(smu);
@@ -105,7 +109,11 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
{
struct amdgpu_device *adev = smu->adev;
- int ret = 0;
+ int ret = 0, index = 0;
+
+ index = smu_msg_get_index(smu, msg);
+ if (index < 0)
+ return index;
ret = smu_v11_0_wait_for_response(smu);
if (ret)
@@ -116,7 +124,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
- smu_v11_0_send_msg_without_waiting(smu, msg);
+ smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
ret = smu_v11_0_wait_for_response(smu);
if (ret)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 057/138] drm/amd/powerplay: replace SMU_MSG_XXX with PPSMC_MSG_XXX message index for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (55 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 056/138] drm/amd/powerplay: use virtual msg index to replace asic-related msg index Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 058/138] drm/amd/powerplay: add append_powerplay_table function Huang Rui
` (81 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch is to setup a common SMU_MSGs for smu11. We can support common MSG
definitions for each asics under smu11.
v2: move smu_v11_0_ppsmc.h to xxx_ppt.c level, because it depends on specific
asic.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ff1120a..fd432fe 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -27,7 +27,6 @@
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
-#include "smu_v11_0_ppsmc.h"
#include "smu11_driver_if.h"
#include "soc15_common.h"
#include "atom.h"
@@ -75,7 +74,7 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
if (i == adev->usec_timeout)
return -ETIME;
- return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == PPSMC_Result_OK ? 0:-EIO;
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
}
static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
@@ -210,7 +209,7 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
uint32_t smu_version = 0xff;
int ret = 0;
- ret = smu_send_smc_msg(smu, PPSMC_MSG_GetDriverIfVersion);
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
if (ret)
goto err;
@@ -468,12 +467,12 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
address_low = (uint32_t)lower_32_bits(address);
ret = smu_send_smc_msg_with_param(smu,
- PPSMC_MSG_SetSystemVirtualDramAddrHigh,
+ SMU_MSG_SetSystemVirtualDramAddrHigh,
address_high);
if (ret)
return ret;
ret = smu_send_smc_msg_with_param(smu,
- PPSMC_MSG_SetSystemVirtualDramAddrLow,
+ SMU_MSG_SetSystemVirtualDramAddrLow,
address_low);
if (ret)
return ret;
@@ -482,15 +481,15 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
address_high = (uint32_t)upper_32_bits(address);
address_low = (uint32_t)lower_32_bits(address);
- ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_DramLogSetDramAddrHigh,
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
address_high);
if (ret)
return ret;
- ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_DramLogSetDramAddrLow,
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
address_low);
if (ret)
return ret;
- ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_DramLogSetDramSize,
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
(uint32_t)memory_pool->size);
if (ret)
return ret;
@@ -594,19 +593,19 @@ static int smu_v11_0_copy_table_to_smc(struct smu_context *smu,
memcpy(driver_pptable->cpu_addr, table_context->driver_pptable,
driver_pptable->size);
- ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_SetDriverDramAddrHigh,
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
upper_32_bits(driver_pptable->mc_address));
if (ret) {
pr_err("[CopyTableToSMC] Attempt to Set Dram Addr High Failed!");
return ret;
}
- ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_SetDriverDramAddrLow,
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
lower_32_bits(driver_pptable->mc_address));
if (ret) {
pr_err("[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!");
return ret;
}
- ret = smu_send_smc_msg_with_param(smu, PPSMC_MSG_TransferTableDram2Smu,
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_TransferTableDram2Smu,
table_id);
if (ret) {
pr_err("[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!");
@@ -634,7 +633,7 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
return -EINVAL;
ret = smu_send_smc_msg_with_param(smu,
- PPSMC_MSG_SetMinDeepSleepDcefclk,
+ SMU_MSG_SetMinDeepSleepDcefclk,
table_context->boot_values.dcefclk / 100);
if (ret)
pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
@@ -649,11 +648,11 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
if (tool_table->mc_address) {
ret = smu_send_smc_msg_with_param(smu,
- PPSMC_MSG_SetToolsDramAddrHigh,
+ SMU_MSG_SetToolsDramAddrHigh,
upper_32_bits(tool_table->mc_address));
if (!ret)
ret = smu_send_smc_msg_with_param(smu,
- PPSMC_MSG_SetToolsDramAddrLow,
+ SMU_MSG_SetToolsDramAddrLow,
lower_32_bits(tool_table->mc_address));
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 058/138] drm/amd/powerplay: add append_powerplay_table function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (56 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 057/138] drm/amd/powerplay: replace SMU_MSG_XXX with PPSMC_MSG_XXX message index for smu11 (v2) Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 059/138] drm/amd/powerplay: expose the function of smu read argument Huang Rui
` (80 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
It needs to add append_powerplay_table function to program the smc_dpm_table for
PPTable_t.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 ++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 92 ++++++++++++++++++++++++++
3 files changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 69832458..fb5ca71 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -192,6 +192,7 @@ struct smu_context
struct pptable_funcs {
int (*store_powerplay_table)(struct smu_context *smu);
int (*check_powerplay_table)(struct smu_context *smu);
+ int (*append_powerplay_table)(struct smu_context *smu);
int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
};
@@ -273,6 +274,8 @@ struct smu_funcs
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
+#define smu_append_powerplay_table(smu) \
+ ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index fd432fe..1b82c25 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -520,6 +520,10 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
return -ENOMEM;
ret = smu_store_powerplay_table(smu);
+ if (ret)
+ return -EINVAL;
+
+ ret = smu_append_powerplay_table(smu);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 5e561ad..6cdbb4f 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -148,6 +148,97 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
return 0;
}
+static int vega20_append_powerplay_table(struct smu_context *smu)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ PPTable_t *smc_pptable = table_context->driver_pptable;
+ struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
+ int index, i, ret;
+
+ index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ smc_dpm_info);
+
+ ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
+ (uint8_t **)&smc_dpm_table);
+ if (ret)
+ return ret;
+
+ smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
+ smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
+
+ smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
+ smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
+ smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
+ smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
+
+ smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
+ smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
+ smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
+
+ smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
+ smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
+ smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
+
+ smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
+ smc_pptable->SocOffset = smc_dpm_table->socoffset;
+ smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
+
+ smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
+ smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
+ smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
+
+ smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
+ smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
+ smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
+
+ smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
+ smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
+ smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
+ smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
+
+ smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
+ smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
+ smc_pptable->Padding1 = smc_dpm_table->padding1;
+ smc_pptable->Padding2 = smc_dpm_table->padding2;
+
+ smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
+ smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
+ smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
+
+ smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
+ smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
+ smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
+
+ smc_pptable->UclkSpreadEnabled = 0;
+ smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
+ smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
+
+ smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
+ smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
+ smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
+
+ smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
+ smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
+ smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
+
+ for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
+ smc_pptable->I2cControllers[i].Enabled =
+ smc_dpm_table->i2ccontrollers[i].enabled;
+ smc_pptable->I2cControllers[i].SlaveAddress =
+ smc_dpm_table->i2ccontrollers[i].slaveaddress;
+ smc_pptable->I2cControllers[i].ControllerPort =
+ smc_dpm_table->i2ccontrollers[i].controllerport;
+ smc_pptable->I2cControllers[i].ThermalThrottler =
+ smc_dpm_table->i2ccontrollers[i].thermalthrottler;
+ smc_pptable->I2cControllers[i].I2cProtocol =
+ smc_dpm_table->i2ccontrollers[i].i2cprotocol;
+ smc_pptable->I2cControllers[i].I2cSpeed =
+ smc_dpm_table->i2ccontrollers[i].i2cspeed;
+ }
+
+ return 0;
+}
+
static int vega20_check_powerplay_table(struct smu_context *smu)
{
ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
@@ -171,6 +262,7 @@ static int vega20_check_powerplay_table(struct smu_context *smu)
static const struct pptable_funcs vega20_ppt_funcs = {
.store_powerplay_table = vega20_store_powerplay_table,
.check_powerplay_table = vega20_check_powerplay_table,
+ .append_powerplay_table = vega20_append_powerplay_table,
.get_smu_msg_index = vega20_get_smu_msg_index,
};
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 059/138] drm/amd/powerplay: expose the function of smu read argument
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (57 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 058/138] drm/amd/powerplay: add append_powerplay_table function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 060/138] drm/amd/powerplay: Change the allocate method of dpm context for smu11 Huang Rui
` (79 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Expose the function of smu_read_smc_arg to get argument value from SMU11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index fb5ca71..8eb2b75 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -221,6 +221,7 @@ struct smu_funcs
int (*system_features_control)(struct smu_context *smu, bool en);
int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
+ int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
};
@@ -270,6 +271,8 @@ struct smu_funcs
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+#define smu_read_smc_arg(smu, arg) \
+ ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 1b82c25..ff3cfdb 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -213,7 +213,7 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
if (ret)
goto err;
- ret = smu_v11_0_read_arg(smu, &smu_version);
+ ret = smu_read_smc_arg(smu, &smu_version);
if (ret)
goto err;
@@ -670,6 +670,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.check_fw_version = smu_v11_0_check_fw_version,
.send_smc_msg = smu_v11_0_send_msg,
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ .read_smc_arg = smu_v11_0_read_arg,
.read_pptable_from_vbios = smu_v11_0_read_pptable_from_vbios,
.init_smc_tables = smu_v11_0_init_smc_tables,
.fini_smc_tables = smu_v11_0_fini_smc_tables,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 060/138] drm/amd/powerplay: Change the allocate method of dpm context for smu11.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (58 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 059/138] drm/amd/powerplay: expose the function of smu read argument Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 061/138] drm/amd/powerplay: implement smu_init_display " Huang Rui
` (78 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Change the allocate method of dpm context as dpm_table is different bewteen
vega20 and smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 15 +++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 44 ++++++++++++++++++++++++++
4 files changed, 63 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8eb2b75..bd8af3d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -190,6 +190,7 @@ struct smu_context
};
struct pptable_funcs {
+ int (*alloc_dpm_context)(struct smu_context *smu);
int (*store_powerplay_table)(struct smu_context *smu);
int (*check_powerplay_table)(struct smu_context *smu);
int (*append_powerplay_table)(struct smu_context *smu);
@@ -273,6 +274,8 @@ struct smu_funcs
((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
#define smu_read_smc_arg(smu, arg) \
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+#define smu_alloc_dpm_context(smu) \
+ ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ff3cfdb..9cb1796 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -251,12 +251,7 @@ static int smu_v11_0_init_dpm_context(struct smu_context *smu)
if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
return -EINVAL;
- smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), GFP_KERNEL);
- if (!smu_dpm->dpm_context)
- return -ENOMEM;
- smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
-
- return 0;
+ return smu_alloc_dpm_context(smu);
}
static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 6cdbb4f..e2cac46 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -132,6 +132,20 @@ static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
}
+static int vega20_allocate_dpm_context(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+ smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
+ GFP_KERNEL);
+ if (!smu_dpm->dpm_context)
+ return -ENOMEM;
+
+ smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
+
+ return 0;
+}
+
static int vega20_store_powerplay_table(struct smu_context *smu)
{
ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
@@ -260,6 +274,7 @@ static int vega20_check_powerplay_table(struct smu_context *smu)
}
static const struct pptable_funcs vega20_ppt_funcs = {
+ .alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
.check_powerplay_table = vega20_check_powerplay_table,
.append_powerplay_table = vega20_append_powerplay_table,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index b597596..27b2f1e 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -23,6 +23,50 @@
#ifndef __VEGA20_PPT_H__
#define __VEGA20_PPT_H__
+#define MAX_REGULAR_DPM_NUMBER 16
+#define MAX_PCIE_CONF 2
+
+struct vega20_dpm_level {
+ bool enabled;
+ uint32_t value;
+ uint32_t param1;
+};
+
+struct vega20_dpm_state {
+ uint32_t soft_min_level;
+ uint32_t soft_max_level;
+ uint32_t hard_min_level;
+ uint32_t hard_max_level;
+};
+
+struct vega20_single_dpm_table {
+ uint32_t count;
+ struct vega20_dpm_state dpm_state;
+ struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct vega20_pcie_table {
+ uint16_t count;
+ uint8_t pcie_gen[MAX_PCIE_CONF];
+ uint8_t pcie_lane[MAX_PCIE_CONF];
+ uint32_t lclk[MAX_PCIE_CONF];
+};
+
+struct vega20_dpm_table {
+ struct vega20_single_dpm_table soc_table;
+ struct vega20_single_dpm_table gfx_table;
+ struct vega20_single_dpm_table mem_table;
+ struct vega20_single_dpm_table eclk_table;
+ struct vega20_single_dpm_table vclk_table;
+ struct vega20_single_dpm_table dclk_table;
+ struct vega20_single_dpm_table dcef_table;
+ struct vega20_single_dpm_table pixel_table;
+ struct vega20_single_dpm_table display_table;
+ struct vega20_single_dpm_table phy_table;
+ struct vega20_single_dpm_table fclk_table;
+ struct vega20_pcie_table pcie_table;
+};
+
extern void vega20_set_ppt_funcs(struct smu_context *smu);
#endif
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 061/138] drm/amd/powerplay: implement smu_init_display for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (59 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 060/138] drm/amd/powerplay: Change the allocate method of dpm context for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 062/138] drm/amd/powerplay: implement smu_run_afll_btc function Huang Rui
` (77 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Add smu_init_display function to send msg to smc to init display.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Ray <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 8 ++++++++
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e4da464..773a388 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -236,6 +236,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
{
int ret;
+ ret = smu_init_display(smu);
+ if (ret)
+ return ret;
+
ret = smu_read_pptable_from_vbios(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index bd8af3d..a618910 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -223,6 +223,7 @@ struct smu_funcs
int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
+ int (*init_display)(struct smu_context *smu);
};
@@ -276,6 +277,9 @@ struct smu_funcs
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
#define smu_alloc_dpm_context(smu) \
((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
+#define smu_init_display(smu) \
+ ((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
+
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9cb1796..d093304 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -658,6 +658,13 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_init_display(struct smu_context *smu)
+{
+ int ret = 0;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -680,6 +687,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.write_pptable = smu_v11_0_write_pptable,
.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
+ .init_display = smu_v11_0_init_display,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 062/138] drm/amd/powerplay: implement smu_run_afll_btc function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (60 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 061/138] drm/amd/powerplay: implement smu_init_display " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 063/138] drm/amd/powerplay: implement smu feature functions Huang Rui
` (76 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
Add smu_run_afll_btc function to send msg to smc to start run afll btc.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 ++++++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 773a388..3ca3d1c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -232,6 +232,7 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
return 0;
}
+
static int smu_smc_table_hw_init(struct smu_context *smu)
{
int ret;
@@ -306,6 +307,11 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ /* issue RunAfllBtc msg */
+ ret = smu_run_afll_btc(smu);
+ if (ret)
+ return ret;
+
/*
* Set min deep sleep dce fclk with bootup value from vbios via
* SetMinDeepSleepDcefclk MSG.
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a618910..984dbb2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -195,6 +195,7 @@ struct pptable_funcs {
int (*check_powerplay_table)(struct smu_context *smu);
int (*append_powerplay_table)(struct smu_context *smu);
int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
+ int (*run_afll_btc)(struct smu_context *smu);
};
struct smu_funcs
@@ -289,6 +290,8 @@ struct smu_funcs
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+#define smu_run_afll_btc(smu) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index e2cac46..57d5f0b 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -273,12 +273,18 @@ static int vega20_check_powerplay_table(struct smu_context *smu)
return 0;
}
+static int vega20_run_btc_afll(struct smu_context *smu)
+{
+ return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
.check_powerplay_table = vega20_check_powerplay_table,
.append_powerplay_table = vega20_append_powerplay_table,
.get_smu_msg_index = vega20_get_smu_msg_index,
+ .run_afll_btc = vega20_run_btc_afll,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 063/138] drm/amd/powerplay: implement smu feature functions
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (61 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 062/138] drm/amd/powerplay: implement smu_run_afll_btc function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 064/138] drm/amd/powerplay: implement feature get&set functions Huang Rui
` (75 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
each ip will support different smu feature,
the driver use bitmap to management this feature.
bitmap:
-allowed: sw driver to enable & disable some feature when driver init.
-suppored: the feature is supproed.
-enabled: the feature is enabled.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <Ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 36 ++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 28 +++++++-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 99 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 14 ++++
4 files changed, 176 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 3ca3d1c..f9b254c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,26 @@
#include "smu_v11_0.h"
#include "atom.h"
+int smu_feature_init_dpm(struct smu_context *smu)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+ uint32_t unallowed_feature_mask[SMU_FEATURE_MAX/32];
+
+ bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
+
+ ret = smu_get_unallowed_feature_mask(smu, unallowed_feature_mask,
+ SMU_FEATURE_MAX/32);
+ if (ret)
+ return ret;
+
+ bitmap_andnot(feature->allowed, feature->allowed,
+ (unsigned long *)unallowed_feature_mask,
+ feature->feature_num);
+
+ return ret;
+}
+
static int smu_set_funcs(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
@@ -133,6 +153,10 @@ static int smu_sw_init(void *handle)
return -EINVAL;
smu->pool_size = adev->pm.smu_prv_buffer_size;
+ smu->smu_feature.feature_num = SMU_FEATURE_MAX;
+ bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
+ bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
+ bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
ret = smu_init_microcode(smu);
if (ret) {
@@ -241,6 +265,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_feature_set_allowed_mask(smu);
+ if (ret)
+ return ret;
+
ret = smu_read_pptable_from_vbios(smu);
if (ret)
return ret;
@@ -312,6 +340,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_feature_enable_all(smu);
+ if (ret)
+ return ret;
+
/*
* Set min deep sleep dce fclk with bootup value from vbios via
* SetMinDeepSleepDcefclk MSG.
@@ -413,6 +445,10 @@ static int smu_hw_init(void *handle)
mutex_lock(&smu->mutex);
+ ret = smu_feature_init_dpm(smu);
+ if (ret)
+ goto failed;
+
ret = smu_smc_table_hw_init(smu);
if (ret)
goto failed;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 984dbb2..740dae2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -175,6 +175,16 @@ struct smu_power_context {
uint32_t power_context_size;
};
+
+#define SMU_FEATURE_MAX (64)
+struct smu_feature
+{
+ uint32_t feature_num;
+ DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
+ DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
+ DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
+};
+
struct smu_context
{
struct amdgpu_device *adev;
@@ -187,6 +197,7 @@ struct smu_context
struct smu_table_context smu_table;
struct smu_dpm_context smu_dpm;
struct smu_power_context smu_power;
+ struct smu_feature smu_feature;
};
struct pptable_funcs {
@@ -196,6 +207,7 @@ struct pptable_funcs {
int (*append_powerplay_table)(struct smu_context *smu);
int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
int (*run_afll_btc)(struct smu_context *smu);
+ int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
};
struct smu_funcs
@@ -225,6 +237,10 @@ struct smu_funcs
int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
int (*init_display)(struct smu_context *smu);
+ int (*set_allowed_mask)(struct smu_context *smu);
+ int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+ int (*enable_all_mask)(struct smu_context *smu);
+ int (*disable_all_mask)(struct smu_context *smu);
};
@@ -280,7 +296,14 @@ struct smu_funcs
((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
#define smu_init_display(smu) \
((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
-
+#define smu_feature_set_allowed_mask(smu) \
+ ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
+#define smu_feature_get_enabled_mask(smu, mask, num) \
+ ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+#define smu_feature_enable_all(smu) \
+ ((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
+#define smu_feature_disable_all(smu) \
+ ((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
@@ -292,6 +315,8 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
#define smu_run_afll_btc(smu) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
+#define smu_get_unallowed_feature_mask(smu, feature_mask, num) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
@@ -300,5 +325,6 @@ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
extern const struct amd_ip_funcs smu_ip_funcs;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
+extern int smu_feature_init_dpm(struct smu_context *smu);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index d093304..f76b5af 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -665,6 +665,101 @@ static int smu_v11_0_init_display(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+ uint32_t feature_mask[2];
+
+ if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
+ return -EINVAL;
+
+ bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
+ feature_mask[1]);
+ if (ret)
+ return ret;
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
+ feature_mask[0]);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
+static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num)
+{
+ uint32_t feature_mask_high = 0, feature_mask_low = 0;
+ int ret = 0;
+
+ if (!feature_mask || num < 2)
+ return -EINVAL;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
+ if (ret)
+ return ret;
+ ret = smu_read_smc_arg(smu, &feature_mask_high);
+ if (ret)
+ return ret;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
+ if (ret)
+ return ret;
+ ret = smu_read_smc_arg(smu, &feature_mask_low);
+ if (ret)
+ return ret;
+
+ feature_mask[0] = feature_mask_low;
+ feature_mask[1] = feature_mask_high;
+
+ return ret;
+}
+
+static int smu_v11_0_enable_all_mask(struct smu_context *smu)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ uint32_t feature_mask[2];
+ int ret = 0;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_EnableAllSmuFeatures);
+ if (ret)
+ return ret;
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+ return ret;
+
+ bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
+ feature->feature_num);
+ bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
+ feature->feature_num);
+
+ return ret;
+}
+
+static int smu_v11_0_disable_all_mask(struct smu_context *smu)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ uint32_t feature_mask[2];
+ int ret = 0;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
+ if (ret)
+ return ret;
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+ return ret;
+
+ bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
+ feature->feature_num);
+ bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
+ feature->feature_num);
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -688,6 +783,10 @@ static const struct smu_funcs smu_v11_0_funcs = {
.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
.init_display = smu_v11_0_init_display,
+ .set_allowed_mask = smu_v11_0_set_allowed_mask,
+ .get_enabled_mask = smu_v11_0_get_enabled_mask,
+ .enable_all_mask = smu_v11_0_enable_all_mask,
+ .disable_all_mask = smu_v11_0_disable_all_mask,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 57d5f0b..4b756e8 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -278,6 +278,19 @@ static int vega20_run_btc_afll(struct smu_context *smu)
return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
}
+static int
+vega20_get_unallowed_feature_mask(struct smu_context *smu,
+ uint32_t *feature_mask, uint32_t num)
+{
+ if (num > 2)
+ return -EINVAL;
+
+ feature_mask[0] = 0xE0041C00;
+ feature_mask[1] = 0xFFFFFFFE; /* bit32~bit63 is Unsupported */
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -285,6 +298,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.append_powerplay_table = vega20_append_powerplay_table,
.get_smu_msg_index = vega20_get_smu_msg_index,
.run_afll_btc = vega20_run_btc_afll,
+ .get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 064/138] drm/amd/powerplay: implement feature get&set functions
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (62 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 063/138] drm/amd/powerplay: implement smu feature functions Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 065/138] drm/amd/powerplay: implement smu_notify_display_change function for smu11 Huang Rui
` (74 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add smu feature operation function helper to deal with smu feature
bitmap.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 37 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 ++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f9b254c..aba3fb1 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -49,6 +49,43 @@ int smu_feature_init_dpm(struct smu_context *smu)
return ret;
}
+int smu_feature_is_enabled(struct smu_context *smu, int feature_id)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ WARN_ON(feature_id > feature->feature_num);
+ return test_bit(feature_id, feature->enabled);
+}
+
+int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ WARN_ON(feature_id > feature->feature_num);
+ if (enable)
+ test_and_set_bit(feature_id, feature->enabled);
+ else
+ test_and_clear_bit(feature_id, feature->enabled);
+ return 0;
+}
+
+int smu_feature_is_supported(struct smu_context *smu, int feature_id)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ WARN_ON(feature_id > feature->feature_num);
+ return test_bit(feature_id, feature->supported);
+}
+
+int smu_feature_set_supported(struct smu_context *smu, int feature_id,
+ bool enable)
+{
+ struct smu_feature *feature = &smu->smu_feature;
+ WARN_ON(feature_id > feature->feature_num);
+ if (enable)
+ test_and_set_bit(feature_id, feature->supported);
+ else
+ test_and_clear_bit(feature_id, feature->supported);
+ return 0;
+}
+
static int smu_set_funcs(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 740dae2..dfabd73 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -327,4 +327,9 @@ extern const struct amd_ip_funcs smu_ip_funcs;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
extern int smu_feature_init_dpm(struct smu_context *smu);
+extern int smu_feature_is_enabled(struct smu_context *smu, int feature_id);
+extern int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable);
+extern int smu_feature_is_supported(struct smu_context *smu, int feature_id);
+extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bool enable);
+
#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 065/138] drm/amd/powerplay: implement smu_notify_display_change function for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (63 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 064/138] drm/amd/powerplay: implement feature get&set functions Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 066/138] drm/amd/powerplay: set defalut dpm table for smu Huang Rui
` (73 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add smu_notify_display_change function to send msg to smc to notify
display is changed.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 11 +++++++++++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index aba3fb1..47b4611 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -381,6 +381,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_notify_display_change(smu);
+ if (ret)
+ return ret;
+
/*
* Set min deep sleep dce fclk with bootup value from vbios via
* SetMinDeepSleepDcefclk MSG.
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index dfabd73..154f74e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -241,6 +241,7 @@ struct smu_funcs
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
int (*enable_all_mask)(struct smu_context *smu);
int (*disable_all_mask)(struct smu_context *smu);
+ int (*notify_display_change)(struct smu_context *smu);
};
@@ -304,6 +305,8 @@ struct smu_funcs
((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
#define smu_feature_disable_all(smu) \
((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
+#define smu_notify_display_change(smu) \
+ ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
#define smu_store_powerplay_table(smu) \
((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
#define smu_check_powerplay_table(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f76b5af..bfda4a3 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -760,6 +760,16 @@ static int smu_v11_0_disable_all_mask(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_notify_display_change(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT))
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -787,6 +797,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_enabled_mask = smu_v11_0_get_enabled_mask,
.enable_all_mask = smu_v11_0_enable_all_mask,
.disable_all_mask = smu_v11_0_disable_all_mask,
+ .notify_display_change = smu_v11_0_notify_display_change,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 066/138] drm/amd/powerplay: set defalut dpm table for smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (64 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 065/138] drm/amd/powerplay: implement smu_notify_display_change function for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 067/138] drm/amd/powerplay: add function to populate umd state clk Huang Rui
` (72 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_set_default_dpm_table function to set dpm table for smu11.
Modified the sequence to populate smc pptable, as it should be done after
related dpm feature is enabled.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 +-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 236 +++++++++++++++++++++++++
4 files changed, 251 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 47b4611..e03132c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -348,15 +348,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
return ret;
/*
- * Set initialized values (get from vbios) to dpm tables context such as
- * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
- * type of clks.
- */
- ret = smu_populate_smc_pptable(smu);
- if (ret)
- return ret;
-
- /*
* Send msg GetDriverIfVersion to check if the return value is equal
* with DRIVER_IF_VERSION of smc header.
*/
@@ -394,6 +385,15 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
return ret;
/*
+ * Set initialized values (get from vbios) to dpm tables context such as
+ * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
+ * type of clks.
+ */
+ ret = smu_populate_smc_pptable(smu);
+ if (ret)
+ return ret;
+
+ /*
* Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
*/
ret = smu_set_tool_table_location(smu);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 154f74e..24babb8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -208,6 +208,7 @@ struct pptable_funcs {
int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
int (*run_afll_btc)(struct smu_context *smu);
int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+ int (*set_default_dpm_table)(struct smu_context *smu);
};
struct smu_funcs
@@ -313,6 +314,8 @@ struct smu_funcs
((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
#define smu_append_powerplay_table(smu) \
((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
+#define smu_set_default_dpm_table(smu) \
+ ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index bfda4a3..66af3e6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -525,43 +525,11 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
-
- PPTable_t *driver_ppt = (PPTable_t *)&(smu->smu_table.tables[TABLE_PPTABLE]);
- struct smu_11_0_dpm_context *dpm_context = (struct smu_11_0_dpm_context *)smu_dpm->dpm_context;
-
- if (dpm_context && driver_ppt) {
- dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
- dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
- dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
- dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
- dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
- dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
- dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
- dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
-
- dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
- dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
+ int ret;
- dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
- dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ ret = smu_set_default_dpm_table(smu);
- return 0;
- }
-
- return -EINVAL;
+ return ret;
}
static int smu_v11_0_copy_table_to_smc(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 4b756e8..bca4085 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -291,6 +291,241 @@ vega20_get_unallowed_feature_mask(struct smu_context *smu,
return 0;
}
+static int
+vega20_set_single_dpm_table(struct smu_context *smu,
+ struct vega20_single_dpm_table *single_dpm_table,
+ PPCLK_e clk_id)
+{
+ int ret = 0;
+ uint32_t i, num_of_levels, clk;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_GetDpmFreqByIndex,
+ (clk_id << 16 | 0xFF));
+ if (ret) {
+ pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
+ return ret;
+ }
+
+ smu_read_smc_arg(smu, &num_of_levels);
+ if (!num_of_levels) {
+ pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
+ return -EINVAL;
+ }
+
+ single_dpm_table->count = num_of_levels;
+
+ for (i = 0; i < num_of_levels; i++) {
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_GetDpmFreqByIndex,
+ (clk_id << 16 | i));
+ if (ret) {
+ pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
+ return ret;
+ }
+ smu_read_smc_arg(smu, &clk);
+ if (!clk) {
+ pr_err("[GetDpmFreqByIndex] clk value is invalid!");
+ return -EINVAL;
+ }
+ single_dpm_table->dpm_levels[i].value = clk;
+ single_dpm_table->dpm_levels[i].enabled = true;
+ }
+ return 0;
+}
+
+static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
+{
+ dpm_state->soft_min_level = 0x0;
+ dpm_state->soft_max_level = 0xffff;
+ dpm_state->hard_min_level = 0x0;
+ dpm_state->hard_max_level = 0xffff;
+}
+
+static int vega20_set_default_dpm_table(struct smu_context *smu)
+{
+ int ret;
+
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_single_dpm_table *single_dpm_table;
+
+ dpm_table = smu_dpm->dpm_context;
+
+ /* socclk */
+ single_dpm_table = &(dpm_table->soc_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_SOCCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* gfxclk */
+ single_dpm_table = &(dpm_table->gfx_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_GFXCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* memclk */
+ single_dpm_table = &(dpm_table->mem_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_UCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+#if 0
+ /* eclk */
+ single_dpm_table = &(dpm_table->eclk_table);
+
+ if (feature->fea_enabled[FEATURE_DPM_VCE_BIT]) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclock / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* vclk */
+ single_dpm_table = &(dpm_table->vclk_table);
+
+ if (feature->fea_enabled[FEATURE_DPM_UVD_BIT]) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclock / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* dclk */
+ single_dpm_table = &(dpm_table->dclk_table);
+
+ if (feature->fea_enabled[FEATURE_DPM_UVD_BIT]) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclock / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+#endif
+
+ /* dcefclk */
+ single_dpm_table = &(dpm_table->dcef_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_DCEFCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* pixclk */
+ single_dpm_table = &(dpm_table->pixel_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_PIXCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 0;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* dispclk */
+ single_dpm_table = &(dpm_table->display_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_DISPCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 0;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* phyclk */
+ single_dpm_table = &(dpm_table->phy_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_PHYCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 0;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ /* fclk */
+ single_dpm_table = &(dpm_table->fclk_table);
+
+ if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_FCLK);
+ if (ret) {
+ pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 0;
+ }
+ vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -299,6 +534,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_smu_msg_index = vega20_get_smu_msg_index,
.run_afll_btc = vega20_run_btc_afll,
.get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
+ .set_default_dpm_table = vega20_set_default_dpm_table,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 067/138] drm/amd/powerplay: add function to populate umd state clk.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (65 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 066/138] drm/amd/powerplay: set defalut dpm table for smu Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 068/138] drm/amd/powerplay: add function to get power limit for smu11 (v2) Huang Rui
` (71 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add vega20_populate_umd_state_clk function to set pstate_sclk and pstate_mclk.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 27 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 3 +++
4 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e03132c..f5ffc9b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -393,6 +393,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_populate_umd_state_clk(smu);
+ if (ret)
+ return ret;
+
/*
* Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
*/
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 24babb8..94013c5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -198,6 +198,9 @@ struct smu_context
struct smu_dpm_context smu_dpm;
struct smu_power_context smu_power;
struct smu_feature smu_feature;
+
+ uint32_t pstate_sclk;
+ uint32_t pstate_mclk;
};
struct pptable_funcs {
@@ -209,6 +212,7 @@ struct pptable_funcs {
int (*run_afll_btc)(struct smu_context *smu);
int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
int (*set_default_dpm_table)(struct smu_context *smu);
+ int (*populate_umd_state_clk)(struct smu_context *smu);
};
struct smu_funcs
@@ -316,6 +320,8 @@ struct smu_funcs
((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
#define smu_set_default_dpm_table(smu) \
((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
+#define smu_populate_umd_state_clk(smu) \
+ ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index bca4085..d794290 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -526,6 +526,32 @@ static int vega20_set_default_dpm_table(struct smu_context *smu)
return 0;
}
+static int vega20_populate_umd_state_clk(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_single_dpm_table *gfx_table = NULL;
+ struct vega20_single_dpm_table *mem_table = NULL;
+
+ dpm_table = smu_dpm->dpm_context;
+ gfx_table = &(dpm_table->gfx_table);
+ mem_table = &(dpm_table->mem_table);
+
+ smu->pstate_sclk = gfx_table->dpm_levels[0].value;
+ smu->pstate_mclk = mem_table->dpm_levels[0].value;
+
+ if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
+ mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
+ smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
+ smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
+ }
+
+ smu->pstate_sclk = smu->pstate_sclk * 100;
+ smu->pstate_mclk = smu->pstate_mclk * 100;
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -535,6 +561,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.run_afll_btc = vega20_run_btc_afll,
.get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
.set_default_dpm_table = vega20_set_default_dpm_table,
+ .populate_umd_state_clk = vega20_populate_umd_state_clk,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index 27b2f1e..ceba4f7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -23,6 +23,9 @@
#ifndef __VEGA20_PPT_H__
#define __VEGA20_PPT_H__
+#define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3
+#define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2
+
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 068/138] drm/amd/powerplay: add function to get power limit for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (66 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 067/138] drm/amd/powerplay: add function to populate umd state clk Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 069/138] drm/amd/powerplay: implement get_current_clk_freq for smu11 Huang Rui
` (70 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add smu_v11_0_get_power_limit function to get power limit vaule.
v2: update "set" to "get", it only implements "get" behavior. (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 ++++++-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 ++++++++++++++++++++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f5ffc9b..b225cf8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -397,6 +397,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_get_power_limit(smu);
+ if (ret)
+ return ret;
+
/*
* Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
*/
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 94013c5..db3d0f57 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -201,6 +201,9 @@ struct smu_context
uint32_t pstate_sclk;
uint32_t pstate_mclk;
+
+ uint32_t power_limit;
+ uint32_t default_power_limit;
};
struct pptable_funcs {
@@ -247,7 +250,7 @@ struct smu_funcs
int (*enable_all_mask)(struct smu_context *smu);
int (*disable_all_mask)(struct smu_context *smu);
int (*notify_display_change)(struct smu_context *smu);
-
+ int (*get_power_limit)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -322,6 +325,8 @@ struct smu_funcs
((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
#define smu_populate_umd_state_clk(smu) \
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+#define smu_get_power_limit(smu) \
+ ((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 66af3e6..4919867 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -738,6 +738,25 @@ static int smu_v11_0_notify_display_change(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_get_power_limit(struct smu_context *smu)
+{
+ int ret;
+ uint32_t power_limit_value;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_GetPptLimit,
+ POWER_SOURCE_AC << 16);
+ if (ret) {
+ pr_err("[GetPptLimit] get default PPT limit failed!");
+ return ret;
+ }
+
+ smu_read_smc_arg(smu, &power_limit_value);
+ smu->power_limit = smu->default_power_limit = power_limit_value;
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -766,6 +785,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.enable_all_mask = smu_v11_0_enable_all_mask,
.disable_all_mask = smu_v11_0_disable_all_mask,
.notify_display_change = smu_v11_0_notify_display_change,
+ .get_power_limit = smu_v11_0_get_power_limit,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 069/138] drm/amd/powerplay: implement get_current_clk_freq for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (67 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 068/138] drm/amd/powerplay: add function to get power limit for smu11 (v2) Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 070/138] drm/amd/powerplay: print clock levels for smu11 (v2) Huang Rui
` (69 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
This patch implements get_current_clk_freq for smu11 future use.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 24 ++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index db3d0f57..bdd930d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -251,6 +251,7 @@ struct smu_funcs
int (*disable_all_mask)(struct smu_context *smu);
int (*notify_display_change)(struct smu_context *smu);
int (*get_power_limit)(struct smu_context *smu);
+ int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
};
#define smu_init_microcode(smu) \
@@ -327,6 +328,8 @@ struct smu_funcs
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_get_power_limit(smu) \
((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
+#define smu_get_current_clk_freq(smu, clk_id, value) \
+ ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4919867..def64f5 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -757,6 +757,29 @@ static int smu_v11_0_get_power_limit(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_get_current_clk_freq(struct smu_context *smu, uint32_t clk_id, uint32_t *value)
+{
+ int ret = 0;
+ uint32_t freq;
+
+ if (clk_id >= PPCLK_COUNT || !value)
+ return -EINVAL;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_GetDpmClockFreq, (clk_id << 16));
+ if (ret)
+ return ret;
+
+ ret = smu_read_smc_arg(smu, &freq);
+ if (ret)
+ return ret;
+
+ freq *= 100;
+ *value = freq;
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -786,6 +809,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.disable_all_mask = smu_v11_0_disable_all_mask,
.notify_display_change = smu_v11_0_notify_display_change,
.get_power_limit = smu_v11_0_get_power_limit,
+ .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 070/138] drm/amd/powerplay: print clock levels for smu11 (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (68 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 069/138] drm/amd/powerplay: implement get_current_clk_freq for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 071/138] drm/amd/powerplay: add get_max_sustainable_clock function Huang Rui
` (68 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function to print current levels for smu11.
v2: expose get_current_clk_freq for smu v11. (Kevin)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 ++-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 79 ++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 250be1e..f1519da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -28,6 +28,7 @@
#include "amdgpu_pm.h"
#include "amdgpu_dpm.h"
#include "amdgpu_display.h"
+#include "amdgpu_smu.h"
#include "atom.h"
#include <linux/power_supply.h>
#include <linux/hwmon.h>
@@ -711,7 +712,9 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->powerplay.pp_funcs->print_clock_levels)
+ if (adev->smu.ppt_funcs)
+ return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
+ else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
else
return snprintf(buf, PAGE_SIZE, "\n");
@@ -783,7 +786,9 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->powerplay.pp_funcs->print_clock_levels)
+ if (adev->smu.ppt_funcs)
+ return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
+ else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
else
return snprintf(buf, PAGE_SIZE, "\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index bdd930d..a3c8b73 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -216,6 +216,7 @@ struct pptable_funcs {
int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
int (*set_default_dpm_table)(struct smu_context *smu);
int (*populate_umd_state_clk)(struct smu_context *smu);
+ int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
};
struct smu_funcs
@@ -330,6 +331,8 @@ struct smu_funcs
((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
#define smu_get_current_clk_freq(smu, clk_id, value) \
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+#define smu_print_clk_levels(smu, type, buf) \
+ ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index d794290..d34e1fa 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -552,6 +552,84 @@ static int vega20_populate_umd_state_clk(struct smu_context *smu)
return 0;
}
+static int vega20_get_clk_table(struct smu_context *smu,
+ struct pp_clock_levels_with_latency *clocks,
+ struct vega20_single_dpm_table *dpm_table)
+{
+ int i, count;
+
+ count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
+ clocks->num_levels = count;
+
+ for (i = 0; i < count; i++) {
+ clocks->data[i].clocks_in_khz =
+ dpm_table->dpm_levels[i].value * 1000;
+ clocks->data[i].latency_in_us = 0;
+ }
+
+ return 0;
+}
+
+static int vega20_print_clk_levels(struct smu_context *smu,
+ enum pp_clock_type type, char *buf)
+{
+ int i, now, size = 0;
+ int ret = 0;
+ struct pp_clock_levels_with_latency clocks;
+ struct vega20_single_dpm_table *single_dpm_table;
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+
+ dpm_table = smu_dpm->dpm_context;
+
+ switch (type) {
+ case PP_SCLK:
+ ret = smu_get_current_clk_freq(smu, PPCLK_GFXCLK, &now);
+ if (ret) {
+ pr_err("Attempt to get current gfx clk Failed!");
+ return ret;
+ }
+
+ single_dpm_table = &(dpm_table->gfx_table);
+ ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
+ if (ret) {
+ pr_err("Attempt to get gfx clk levels Failed!");
+ return ret;
+ }
+
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n", i,
+ clocks.data[i].clocks_in_khz / 1000,
+ (clocks.data[i].clocks_in_khz == now * 10)
+ ? "*" : "");
+ break;
+
+ case PP_MCLK:
+ ret = smu_get_current_clk_freq(smu, PPCLK_UCLK, &now);
+ if (ret) {
+ pr_err("Attempt to get current mclk Failed!");
+ return ret;
+ }
+
+ single_dpm_table = &(dpm_table->mem_table);
+ ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
+ if (ret) {
+ pr_err("Attempt to get memory clk levels Failed!");
+ return ret;
+ }
+
+ for (i = 0; i < clocks.num_levels; i++)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ i, clocks.data[i].clocks_in_khz / 1000,
+ (clocks.data[i].clocks_in_khz == now * 10)
+ ? "*" : "");
+ break;
+ default:
+ break;
+ }
+ return size;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -562,6 +640,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
.set_default_dpm_table = vega20_set_default_dpm_table,
.populate_umd_state_clk = vega20_populate_umd_state_clk,
+ .print_clk_levels = vega20_print_clk_levels,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 071/138] drm/amd/powerplay: add get_max_sustainable_clock function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (69 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 070/138] drm/amd/powerplay: print clock levels for smu11 (v2) Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 072/138] drm/amd/powerplay: add function to get thermal range Huang Rui
` (67 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds get_max_sustainable_clock function for smu11.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 ++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 114 +++++++++++++++++++++++++
4 files changed, 135 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b225cf8..cd04369 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -393,6 +393,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_init_max_sustainable_clocks(smu);
+ if (ret)
+ return ret;
+
ret = smu_populate_umd_state_clk(smu);
if (ret)
return ret;
@@ -539,6 +543,11 @@ static int smu_hw_fini(void *handle)
return -EINVAL;
kfree(table_context->driver_pptable);
+ if (table_context->max_sustainable_clocks) {
+ kfree(table_context->max_sustainable_clocks);
+ table_context->max_sustainable_clocks = NULL;
+ }
+
ret = smu_fini_fb_allocations(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a3c8b73..a68519e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -158,6 +158,7 @@ struct smu_table_context
void *power_play_table;
uint32_t power_play_table_size;
+ void *max_sustainable_clocks;
struct smu_bios_boot_up_values boot_values;
void *driver_pptable;
struct smu_table *tables;
@@ -253,6 +254,7 @@ struct smu_funcs
int (*notify_display_change)(struct smu_context *smu);
int (*get_power_limit)(struct smu_context *smu);
int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
+ int (*init_max_sustainable_clocks)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -297,6 +299,8 @@ struct smu_funcs
((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
#define smu_system_features_control(smu, en) \
((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
+#define smu_init_max_sustainable_clocks(smu) \
+ ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_send_smc_msg(smu, msg) \
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 2853ab7..aa8d81f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -36,6 +36,14 @@
#define smnMP0_FW_INTF 0x30101c0
#define smnMP1_PUB_CTRL 0x3010b14
+struct smu_11_0_max_sustainable_clocks {
+ uint32_t display_clock;
+ uint32_t phy_clock;
+ uint32_t pixel_clock;
+ uint32_t uclock;
+ uint32_t dcef_clock;
+ uint32_t soc_clock;
+};
struct smu_11_0_dpm_table {
uint32_t min; /* MHz */
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index def64f5..129d2b1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -738,6 +738,119 @@ static int smu_v11_0_notify_display_change(struct smu_context *smu)
return ret;
}
+static int
+smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ PPCLK_e clock_select)
+{
+ int ret = 0;
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
+ clock_select << 16);
+ if (ret) {
+ pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
+ return ret;
+ }
+
+ ret = smu_read_smc_arg(smu, clock);
+ if (ret)
+ return ret;
+
+ if (*clock != 0)
+ return 0;
+
+ /* if DC limit is zero, return AC limit */
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
+ clock_select << 16);
+ if (ret) {
+ pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
+ return ret;
+ }
+
+ ret = smu_read_smc_arg(smu, clock);
+
+ return ret;
+}
+
+static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+{
+ struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
+ int ret = 0;
+
+ max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
+ GFP_KERNEL);
+ smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
+
+ max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
+ max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
+ max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
+ max_sustainable_clocks->display_clock = 0xFFFFFFFF;
+ max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
+ max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_v11_0_get_max_sustainable_clock(smu,
+ &(max_sustainable_clocks->uclock),
+ PPCLK_UCLK);
+ if (ret) {
+ pr_err("[%s] failed to get max UCLK from SMC!",
+ __func__);
+ return ret;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
+ ret = smu_v11_0_get_max_sustainable_clock(smu,
+ &(max_sustainable_clocks->soc_clock),
+ PPCLK_SOCCLK);
+ if (ret) {
+ pr_err("[%s] failed to get max SOCCLK from SMC!",
+ __func__);
+ return ret;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_get_max_sustainable_clock(smu,
+ &(max_sustainable_clocks->dcef_clock),
+ PPCLK_DCEFCLK);
+ if (ret) {
+ pr_err("[%s] failed to get max DCEFCLK from SMC!",
+ __func__);
+ return ret;
+ }
+
+ ret = smu_v11_0_get_max_sustainable_clock(smu,
+ &(max_sustainable_clocks->display_clock),
+ PPCLK_DISPCLK);
+ if (ret) {
+ pr_err("[%s] failed to get max DISPCLK from SMC!",
+ __func__);
+ return ret;
+ }
+ ret = smu_v11_0_get_max_sustainable_clock(smu,
+ &(max_sustainable_clocks->phy_clock),
+ PPCLK_PHYCLK);
+ if (ret) {
+ pr_err("[%s] failed to get max PHYCLK from SMC!",
+ __func__);
+ return ret;
+ }
+ ret = smu_v11_0_get_max_sustainable_clock(smu,
+ &(max_sustainable_clocks->pixel_clock),
+ PPCLK_PIXCLK);
+ if (ret) {
+ pr_err("[%s] failed to get max PIXCLK from SMC!",
+ __func__);
+ return ret;
+ }
+ }
+
+ if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
+ max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
+
+ return 0;
+}
+
static int smu_v11_0_get_power_limit(struct smu_context *smu)
{
int ret;
@@ -810,6 +923,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.notify_display_change = smu_v11_0_notify_display_change,
.get_power_limit = smu_v11_0_get_power_limit,
.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 072/138] drm/amd/powerplay: add function to get thermal range
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (70 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 071/138] drm/amd/powerplay: add get_max_sustainable_clock function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 073/138] drm/amd/powerplay: add function to set " Huang Rui
` (66 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add the function to get the min and max thermal value for vega20 with
smu11 architecture.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12 ++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 ++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a68519e..4d12cd6 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -164,6 +164,7 @@ struct smu_table_context
struct smu_table *tables;
uint32_t table_count;
struct smu_table memory_pool;
+ uint16_t software_shutdown_temp;
};
struct smu_dpm_context {
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 129d2b1..630ba224 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -31,6 +31,7 @@
#include "soc15_common.h"
#include "atom.h"
#include "vega20_ppt.h"
+#include "pp_thermal.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
@@ -893,6 +894,17 @@ static int smu_v11_0_get_current_clk_freq(struct smu_context *smu, uint32_t clk_
return ret;
}
+static int smu_v11_0_get_thermal_range(struct smu_context *smu,
+ struct PP_TemperatureRange *range)
+{
+ memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
+
+ range->max = smu->smu_table.software_shutdown_temp *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index d34e1fa..45f3276 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -159,6 +159,8 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
sizeof(PPTable_t));
+ table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 073/138] drm/amd/powerplay: add function to set thermal range
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (71 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 072/138] drm/amd/powerplay: add function to get thermal range Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 074/138] drm/amd/powerplay: add function to enable thermal alert Huang Rui
` (65 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add the function to set the correct min and max thermal value for smu11
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 32 +++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 630ba224..cf6b203 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -42,6 +42,8 @@
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
#define SMU11_TOOL_SIZE 0x19000
+#define SMU11_THERMAL_MINIMUM_ALERT_TEMP 0
+#define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
@@ -905,6 +907,36 @@ static int smu_v11_0_get_thermal_range(struct smu_context *smu,
return 0;
}
+static int smu_v11_0_set_thermal_range(struct smu_context *smu,
+ struct PP_TemperatureRange *range)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ uint32_t val;
+
+ if (low < range->min)
+ low = range->min;
+ if (high > range->max)
+ high = range->max;
+
+ if (low > high)
+ return -EINVAL;
+
+ val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+ val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+
+ WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 074/138] drm/amd/powerplay: add function to enable thermal alert
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (72 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 073/138] drm/amd/powerplay: add function to set " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 075/138] drm/amd/powerplay: add function to set fan table to control thermal Huang Rui
` (64 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function to enable thermal alerts on thermal control for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index cf6b203..59e8458 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -937,6 +937,20 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu,
return 0;
}
+static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t val = 0;
+
+ val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
+ val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
+ val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
+
+ WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 075/138] drm/amd/powerplay: add function to set fan table to control thermal
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (73 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 074/138] drm/amd/powerplay: add function to enable thermal alert Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 076/138] drm/amd/powerplay: add function to start thermal control Huang Rui
` (63 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function of smu_v11_0_set_thermal_fan_table to set fan table for
smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 59e8458..55e9ed6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -951,6 +951,18 @@ static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_set_thermal_fan_table(struct smu_context *smu)
+{
+ int ret;
+ struct smu_table_context *table_context = &smu->smu_table;
+ PPTable_t *pptable = table_context->driver_pptable;
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
+ (uint32_t)pptable->FanTargetTemperature);
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 076/138] drm/amd/powerplay: add function to start thermal control
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (74 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 075/138] drm/amd/powerplay: add function to set fan table to control thermal Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 077/138] drm/amd/powerplay: implement smu update table function Huang Rui
` (62 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function to start thermal control for smu11 when smu hw_init.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 28 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 +
4 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index cd04369..172b844 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -518,6 +518,10 @@ static int smu_hw_init(void *handle)
if (ret)
goto failed;
+ ret = smu_start_thermal_control(smu);
+ if (ret)
+ goto failed;
+
mutex_unlock(&smu->mutex);
pr_info("SMU is initialized successfully!\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 4d12cd6..fe86a7f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -165,6 +165,7 @@ struct smu_table_context
uint32_t table_count;
struct smu_table memory_pool;
uint16_t software_shutdown_temp;
+ uint8_t thermal_controller_type;
};
struct smu_dpm_context {
@@ -256,6 +257,7 @@ struct smu_funcs
int (*get_power_limit)(struct smu_context *smu);
int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
int (*init_max_sustainable_clocks)(struct smu_context *smu);
+ int (*start_thermal_control)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -338,6 +340,8 @@ struct smu_funcs
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
#define smu_print_clk_levels(smu, type, buf) \
((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
+#define smu_start_thermal_control(smu) \
+ ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 55e9ed6..8ba6b9f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -963,6 +963,33 @@ static int smu_v11_0_set_thermal_fan_table(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+{
+ int ret = 0;
+ struct PP_TemperatureRange range;
+ struct amdgpu_device *adev = smu->adev;
+
+ smu_v11_0_get_thermal_range(smu, &range);
+
+ if (smu->smu_table.thermal_controller_type) {
+ ret = smu_v11_0_set_thermal_range(smu, &range);
+ if (ret)
+ return ret;
+
+ ret = smu_v11_0_enable_thermal_alert(smu);
+ if (ret)
+ return ret;
+ ret = smu_v11_0_set_thermal_fan_table(smu);
+ if (ret)
+ return ret;
+ }
+
+ adev->pm.dpm.thermal.min_temp = range.min;
+ adev->pm.dpm.thermal.max_temp = range.max;
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -994,6 +1021,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_power_limit = smu_v11_0_get_power_limit,
.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+ .start_thermal_control = smu_v11_0_start_thermal_control,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 45f3276..171cfc8 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -160,6 +160,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
sizeof(PPTable_t));
table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
+ table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 077/138] drm/amd/powerplay: implement smu update table function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (75 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 076/138] drm/amd/powerplay: add function to start thermal control Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 078/138] drm/amd/powerplay: implement is_support_sw_smu function for new smu Huang Rui
` (61 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
sometime, the driver need changed table data between driver and smu.
this function can help update table data
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 30 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 172b844..a6503b4 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,36 @@
#include "smu_v11_0.h"
#include "atom.h"
+int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_data, bool drv2smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *table = NULL;
+ int ret = 0;
+
+ if (!table_data || table_id >= smu_table->table_count)
+ return -EINVAL;
+
+ table = &smu_table->tables[table_id];
+
+ if (drv2smu)
+ memcpy(table->cpu_addr, table_data, table->size);
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh, upper_32_bits(table->mc_address));
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow, lower_32_bits(table->mc_address));
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, drv2smu ? SMU_MSG_TransferTableDram2Smu : SMU_MSG_TransferTableSmu2Dram, table_id);
+ if (ret)
+ return ret;
+
+ if (!drv2smu)
+ memcpy(table_data, table->cpu_addr, table->size);
+
+ return ret;
+}
+
int smu_feature_init_dpm(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index fe86a7f..2daf318 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -364,4 +364,6 @@ extern int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool
extern int smu_feature_is_supported(struct smu_context *smu, int feature_id);
extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bool enable);
+int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_data, bool drv2smu);
+
#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 078/138] drm/amd/powerplay: implement is_support_sw_smu function for new smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (76 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 077/138] drm/amd/powerplay: implement smu update table function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 079/138] drm/amd/powerplay: implement sysfs of amdgpu_get_busy_percent for smu11 Huang Rui
` (60 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add this helper to check new sw-smu support.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 23 +++++++++++++++++------
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
4 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index f1519da..6260f05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -712,7 +712,7 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->smu.ppt_funcs)
+ if (is_support_sw_smu(adev))
return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
@@ -786,7 +786,7 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->smu.ppt_funcs)
+ if (is_support_sw_smu(adev))
return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0e60496..ed259ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -605,7 +605,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (!amdgpu_sriov_vf(adev)) {
- if (amdgpu_dpm == 1 && adev->asic_type >= CHIP_VEGA20)
+ if (is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
else
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index a6503b4..e30a745 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -59,6 +59,17 @@ int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_dat
return ret;
}
+bool is_support_sw_smu(struct amdgpu_device *adev)
+{
+ if (amdgpu_dpm != 1)
+ return false;
+
+ if (adev->asic_type >= CHIP_VEGA20)
+ return true;
+
+ return false;
+}
+
int smu_feature_init_dpm(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
@@ -216,7 +227,7 @@ static int smu_sw_init(void *handle)
struct smu_context *smu = &adev->smu;
int ret;
- if (adev->asic_type < CHIP_VEGA20)
+ if (!is_support_sw_smu(adev))
return -EINVAL;
smu->pool_size = adev->pm.smu_prv_buffer_size;
@@ -246,7 +257,7 @@ static int smu_sw_fini(void *handle)
struct smu_context *smu = &adev->smu;
int ret;
- if (adev->asic_type < CHIP_VEGA20)
+ if (!is_support_sw_smu(adev))
return -EINVAL;
ret = smu_smc_table_sw_fini(smu);
@@ -511,7 +522,7 @@ static int smu_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
- if (adev->asic_type < CHIP_VEGA20)
+ if (!is_support_sw_smu(adev))
return -EINVAL;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
@@ -570,7 +581,7 @@ static int smu_hw_fini(void *handle)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
- if (adev->asic_type < CHIP_VEGA20)
+ if (!is_support_sw_smu(adev))
return -EINVAL;
if (!table_context->driver_pptable)
@@ -597,7 +608,7 @@ static int smu_suspend(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->asic_type < CHIP_VEGA20)
+ if (!is_support_sw_smu(adev))
return -EINVAL;
return 0;
@@ -609,7 +620,7 @@ static int smu_resume(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
- if (adev->asic_type < CHIP_VEGA20)
+ if (!is_support_sw_smu(adev))
return -EINVAL;
pr_info("SMU is resuming...\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 2daf318..7c79369 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -365,5 +365,6 @@ extern int smu_feature_is_supported(struct smu_context *smu, int feature_id);
extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bool enable);
int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_data, bool drv2smu);
+bool is_support_sw_smu(struct amdgpu_device *adev);
#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 079/138] drm/amd/powerplay: implement sysfs of amdgpu_get_busy_percent for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (77 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 078/138] drm/amd/powerplay: implement is_support_sw_smu function for new smu Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 080/138] drm/amd/powerplay: implement sysfs of pp_table " Huang Rui
` (59 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add interface amdgpu_get_busy_percent for smu11
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 5 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 62 ++++++++++----------------
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 40 +++++++++++++++++
5 files changed, 73 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index dd9a4fb..3643052 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -571,10 +571,9 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
idx = *pos >> 2;
valuesize = sizeof(values);
- if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
- r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
- else
- return -EINVAL;
+ r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
+ if (r)
+ return r;
if (size > valuesize)
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 2f61e9e..c874e30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -260,9 +260,6 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_enable_bapm(adev, e) \
((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
-#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
- ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
-
#define amdgpu_dpm_set_fan_control_mode(adev, m) \
((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
@@ -486,6 +483,8 @@ void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
+int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
bool amdgpu_is_uvd_state(u32 class, u32 class2);
void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
u32 *p, u32 *u);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6260f05..de67dde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -81,6 +81,27 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
}
}
+int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+
+ if (!data || !size)
+ return -EINVAL;
+
+ if (is_support_sw_smu(adev))
+ ret = smu_read_sensor(&adev->smu, sensor, data, size);
+ else {
+ if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
+ ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
+ sensor, data, size);
+ else
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
/**
* DOC: power_dpm_state
*
@@ -1151,14 +1172,10 @@ static ssize_t amdgpu_get_busy_percent(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
int r, value, size = sizeof(value);
- /* sanity check PP is enabled */
- if (!(adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor))
- return -EINVAL;
-
/* read the IP busy sensor */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
(void *)&value, &size);
+
if (r)
return r;
@@ -1252,11 +1269,6 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- /* sanity check PP is enabled */
- if (!(adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor))
- return -EINVAL;
-
/* get the temperature */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
(void *)&temp, &size);
@@ -1427,9 +1439,6 @@ static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
u32 size = sizeof(min_rpm);
int r;
- if (!adev->powerplay.pp_funcs->read_sensor)
- return -EINVAL;
-
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
(void *)&min_rpm, &size);
if (r)
@@ -1447,9 +1456,6 @@ static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
u32 size = sizeof(max_rpm);
int r;
- if (!adev->powerplay.pp_funcs->read_sensor)
- return -EINVAL;
-
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
(void *)&max_rpm, &size);
if (r)
@@ -1574,11 +1580,6 @@ static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- /* sanity check PP is enabled */
- if (!(adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor))
- return -EINVAL;
-
/* get the voltage */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
(void *)&vddgfx, &size);
@@ -1613,11 +1614,6 @@ static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- /* sanity check PP is enabled */
- if (!(adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor))
- return -EINVAL;
-
/* get the voltage */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
(void *)&vddnb, &size);
@@ -1649,11 +1645,6 @@ static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- /* sanity check PP is enabled */
- if (!(adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor))
- return -EINVAL;
-
/* get the voltage */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
(void *)&query, &size);
@@ -2043,9 +2034,7 @@ void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
if (!adev->pm.dpm_enabled)
return;
- if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor &&
- !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
(void *)&temp, &size)) {
if (temp < adev->pm.dpm.thermal.min_temp)
/* switch back the user state */
@@ -2557,11 +2546,6 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
uint32_t query = 0;
int size;
- /* sanity check PP is enabled */
- if (!(adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->read_sensor))
- return -EINVAL;
-
/* GPU Clocks */
size = sizeof(value);
seq_printf(m, "GFX Clocks and Power:\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 7c79369..006a721 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -23,6 +23,7 @@
#define __AMDGPU_SMU_H__
#include "amdgpu.h"
+#include "kgd_pp_interface.h"
enum smu_message_type
{
@@ -258,6 +259,8 @@ struct smu_funcs
int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
int (*init_max_sustainable_clocks)(struct smu_context *smu);
int (*start_thermal_control)(struct smu_context *smu);
+ int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
};
#define smu_init_microcode(smu) \
@@ -342,6 +345,8 @@ struct smu_funcs
((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
#define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+#define smu_read_sensor(smu, sensor, data, size) \
+ ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 8ba6b9f..462133b 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -990,6 +990,45 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_get_current_activity_percent(struct smu_context *smu,
+ uint32_t *value)
+{
+ int ret = 0;
+ SmuMetrics_t metrics;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, TABLE_SMU_METRICS, (void *)&metrics, false);
+ if (ret)
+ return ret;
+
+ *value = metrics.AverageGfxActivity;
+
+ return 0;
+}
+
+static int smu_v11_0_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ ret = smu_v11_0_get_current_activity_percent(smu, data);
+ *size = 4;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ *size = 0;
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1022,6 +1061,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
.start_thermal_control = smu_v11_0_start_thermal_control,
+ .read_sensor = smu_v11_0_read_sensor,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 080/138] drm/amd/powerplay: implement sysfs of pp_table for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (78 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 079/138] drm/amd/powerplay: implement sysfs of amdgpu_get_busy_percent for smu11 Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 081/138] drm/amd/powerplay: upload dpm level " Huang Rui
` (58 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add pp_table sysfs interface for new sw-smu.
get: return pptable raw data
set: write pptable raw data to pptable, then reset smu (hw_fini -> hw_init)
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 14 ++++-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 73 ++++++++++++++++++++++++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++-
4 files changed, 89 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index de67dde..68dfe2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -464,7 +464,12 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
char *table = NULL;
int size;
- if (adev->powerplay.pp_funcs->get_pp_table)
+ if (is_support_sw_smu(adev)) {
+ size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
+ if (size < 0)
+ return size;
+ }
+ else if (adev->powerplay.pp_funcs->get_pp_table)
size = amdgpu_dpm_get_pp_table(adev, &table);
else
return 0;
@@ -484,8 +489,13 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ int ret = 0;
- if (adev->powerplay.pp_funcs->set_pp_table)
+ if (is_support_sw_smu(adev)) {
+ ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
+ if (ret)
+ return ret;
+ } else if (adev->powerplay.pp_funcs->set_pp_table)
amdgpu_dpm_set_pp_table(adev, buf, count);
return count;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e30a745..52babf5 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -70,6 +70,54 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
return false;
}
+int smu_sys_get_pp_table(struct smu_context *smu, void **table)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
+ return -EINVAL;
+
+ if (smu_table->hardcode_pptable)
+ *table = smu_table->hardcode_pptable;
+ else
+ *table = smu_table->power_play_table;
+
+ return smu_table->power_play_table_size;
+}
+
+int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
+ int ret = 0;
+
+ if (header->usStructureSize != size) {
+ pr_err("pp table size not matched !\n");
+ return -EIO;
+ }
+
+ mutex_lock(&smu->mutex);
+
+ if (!smu_table->hardcode_pptable)
+ smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
+ if (!smu_table->hardcode_pptable) {
+ ret = -ENOMEM;
+ goto failed;
+ }
+
+ memcpy(smu_table->hardcode_pptable, buf, size);
+ smu_table->power_play_table = smu_table->hardcode_pptable;
+ smu_table->power_play_table_size = size;
+
+ ret = smu_reset(smu);
+ if (ret)
+ pr_info("smu reset failed, ret = %d\n", ret);
+
+failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
+}
+
int smu_feature_init_dpm(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
@@ -322,7 +370,7 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
uint32_t i = 0;
if (table_count == 0 || tables == NULL)
- return -EINVAL;
+ return 0;
for (i = 0 ; i < table_count; i++) {
if (tables[i].size == 0)
@@ -584,9 +632,10 @@ static int smu_hw_fini(void *handle)
if (!is_support_sw_smu(adev))
return -EINVAL;
- if (!table_context->driver_pptable)
- return -EINVAL;
- kfree(table_context->driver_pptable);
+ if (table_context->driver_pptable) {
+ kfree(table_context->driver_pptable);
+ table_context->driver_pptable = NULL;
+ }
if (table_context->max_sustainable_clocks) {
kfree(table_context->max_sustainable_clocks);
@@ -604,6 +653,22 @@ static int smu_hw_fini(void *handle)
return 0;
}
+int smu_reset(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+
+ ret = smu_hw_fini(adev);
+ if (ret)
+ return ret;
+
+ ret = smu_hw_init(adev);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+
static int smu_suspend(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 006a721..5efa634 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -158,6 +158,7 @@ struct smu_table_context
{
void *power_play_table;
uint32_t power_play_table_size;
+ void *hardcode_pptable;
void *max_sustainable_clocks;
struct smu_bios_boot_up_values boot_values;
@@ -371,5 +372,8 @@ extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bo
int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_data, bool drv2smu);
bool is_support_sw_smu(struct amdgpu_device *adev);
+int smu_reset(struct smu_context *smu);
+int smu_sys_get_pp_table(struct smu_context *smu, void **table);
+int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 462133b..1aef6c6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -241,8 +241,10 @@ static int smu_v11_0_read_pptable_from_vbios(struct smu_context *smu)
if (ret)
return ret;
- smu->smu_table.power_play_table = table;
- smu->smu_table.power_play_table_size = size;
+ if (!smu->smu_table.power_play_table)
+ smu->smu_table.power_play_table = table;
+ if (!smu->smu_table.power_play_table_size)
+ smu->smu_table.power_play_table_size = size;
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 081/138] drm/amd/powerplay: upload dpm level for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (79 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 080/138] drm/amd/powerplay: implement sysfs of pp_table " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 082/138] drm/amd/powerplay: force clock levels " Huang Rui
` (57 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function to support gfx_clk and mem_clk upload min and max dpm level for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 72 ++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 171cfc8..ff000af 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -633,6 +633,78 @@ static int vega20_print_clk_levels(struct smu_context *smu,
return size;
}
+static int vega20_upload_dpm_min_level(struct smu_context *smu)
+{
+ struct vega20_dpm_table *dpm_table;
+ struct vega20_single_dpm_table *single_dpm_table;
+ uint32_t min_freq;
+ int ret = 0;
+
+ dpm_table = smu->smu_dpm.dpm_context;
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
+ single_dpm_table = &(dpm_table->gfx_table);
+ min_freq = single_dpm_table->dpm_state.soft_min_level;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetSoftMinByFreq,
+ (PPCLK_GFXCLK << 16) | (min_freq & 0xffff));
+ if (ret) {
+ pr_err("Failed to set soft min gfxclk !\n");
+ return ret;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ single_dpm_table = &(dpm_table->mem_table);
+ min_freq = single_dpm_table->dpm_state.soft_min_level;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetSoftMinByFreq,
+ (PPCLK_UCLK << 16) | (min_freq & 0xffff));
+ if (ret) {
+ pr_err("Failed to set soft min memclk !\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int vega20_upload_dpm_max_level(struct smu_context *smu)
+{
+ struct vega20_dpm_table *dpm_table;
+ struct vega20_single_dpm_table *single_dpm_table;
+ uint32_t max_freq;
+ int ret = 0;
+
+ dpm_table = smu->smu_dpm.dpm_context;
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
+ single_dpm_table = &(dpm_table->gfx_table);
+ max_freq = single_dpm_table->dpm_state.soft_max_level;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetSoftMaxByFreq,
+ (PPCLK_GFXCLK << 16) | (max_freq & 0xffff));
+ if (ret) {
+ pr_err("Failed to set soft max gfxclk !\n");
+ return ret;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ single_dpm_table = &(dpm_table->mem_table);
+ max_freq = single_dpm_table->dpm_state.soft_max_level;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetSoftMaxByFreq,
+ (PPCLK_UCLK << 16) | (max_freq & 0xffff));
+ if (ret) {
+ pr_err("Failed to set soft max memclk !\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 082/138] drm/amd/powerplay: force clock levels for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (80 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 081/138] drm/amd/powerplay: upload dpm level " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 083/138] drm/amd/powerplay: implement sensor of SCLK and MCLK " Huang Rui
` (56 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function to set sclk or mclk level for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8 ++-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 78 ++++++++++++++++++++++++++
3 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 68dfe2f..5184251 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -801,7 +801,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
if (ret)
return ret;
- if (adev->powerplay.pp_funcs->force_clock_level)
+ if (is_support_sw_smu(adev))
+ ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
if (ret)
@@ -839,7 +841,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
if (ret)
return ret;
- if (adev->powerplay.pp_funcs->force_clock_level)
+ if (is_support_sw_smu(adev))
+ ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 5efa634..5bbf6a2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,7 @@ struct pptable_funcs {
int (*set_default_dpm_table)(struct smu_context *smu);
int (*populate_umd_state_clk)(struct smu_context *smu);
int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
+ int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
};
struct smu_funcs
@@ -344,6 +345,8 @@ struct smu_funcs
((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
#define smu_print_clk_levels(smu, type, buf) \
((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
+#define smu_force_clk_levels(smu, type, level) \
+ ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (type), (level)) : 0)
#define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_read_sensor(smu, sensor, data, size) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index ff000af..16eb5a1 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -705,6 +705,83 @@ static int vega20_upload_dpm_max_level(struct smu_context *smu)
return ret;
}
+static int vega20_force_clk_levels(struct smu_context *smu,
+ enum pp_clock_type type, uint32_t mask)
+{
+ struct vega20_dpm_table *dpm_table;
+ struct vega20_single_dpm_table *single_dpm_table;
+ uint32_t soft_min_level, soft_max_level;
+ int ret;
+
+ soft_min_level = mask ? (ffs(mask) - 1) : 0;
+ soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+ dpm_table = smu->smu_dpm.dpm_context;
+
+ switch (type) {
+ case PP_SCLK:
+ single_dpm_table = &(dpm_table->gfx_table);
+
+ if (soft_max_level >= single_dpm_table->count) {
+ pr_err("Clock level specified %d is over max allowed %d\n",
+ soft_max_level, single_dpm_table->count - 1);
+ return -EINVAL;
+ }
+
+ single_dpm_table->dpm_state.soft_min_level =
+ single_dpm_table->dpm_levels[soft_min_level].value;
+ single_dpm_table->dpm_state.soft_max_level =
+ single_dpm_table->dpm_levels[soft_max_level].value;
+
+ ret = vega20_upload_dpm_min_level(smu);
+ if (ret) {
+ pr_err("Failed to upload boot level to lowest!\n");
+ return ret;
+ }
+
+ ret = vega20_upload_dpm_max_level(smu);
+ if (ret) {
+ pr_err("Failed to upload dpm max level to highest!\n");
+ return ret;
+ }
+
+ break;
+
+ case PP_MCLK:
+ single_dpm_table = &(dpm_table->mem_table);
+
+ if (soft_max_level >= single_dpm_table->count) {
+ pr_err("Clock level specified %d is over max allowed %d\n",
+ soft_max_level, single_dpm_table->count - 1);
+ return -EINVAL;
+ }
+
+ single_dpm_table->dpm_state.soft_min_level =
+ single_dpm_table->dpm_levels[soft_min_level].value;
+ single_dpm_table->dpm_state.soft_max_level =
+ single_dpm_table->dpm_levels[soft_max_level].value;
+
+ ret = vega20_upload_dpm_min_level(smu);
+ if (ret) {
+ pr_err("Failed to upload boot level to lowest!\n");
+ return ret;
+ }
+
+ ret = vega20_upload_dpm_max_level(smu);
+ if (ret) {
+ pr_err("Failed to upload dpm max level to highest!\n");
+ return ret;
+ }
+
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -716,6 +793,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.set_default_dpm_table = vega20_set_default_dpm_table,
.populate_umd_state_clk = vega20_populate_umd_state_clk,
.print_clk_levels = vega20_print_clk_levels,
+ .force_clk_levels = vega20_force_clk_levels,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 083/138] drm/amd/powerplay: implement sensor of SCLK and MCLK for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (81 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 082/138] drm/amd/powerplay: force clock levels " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 084/138] drm/amd/powerplay: implement sensor of thermal_get_temperature " Huang Rui
` (55 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add sensor interface of SCLK and MCKL for sys interface and hwmon.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 1aef6c6..7c16ece 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1020,6 +1020,14 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_v11_0_get_current_activity_percent(smu, data);
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_GFX_MCLK:
+ ret = smu_get_current_clk_freq(smu, PPCLK_UCLK, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GFX_SCLK:
+ ret = smu_get_current_clk_freq(smu, PPCLK_GFXCLK, (uint32_t *)data);
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 084/138] drm/amd/powerplay: implement sensor of thermal_get_temperature for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (82 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 083/138] drm/amd/powerplay: implement sensor of SCLK and MCLK " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 085/138] drm/amd/powerplay: implement sensor of get_gpu_power " Huang Rui
` (54 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add sensor interface of thermal temperature for debugfs and hwmon.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 26 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 1 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 1 -
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7c16ece..25dbeec 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -45,6 +45,8 @@ MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
#define SMU11_THERMAL_MINIMUM_ALERT_TEMP 0
#define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255
+#define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
+
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
{
@@ -1010,6 +1012,26 @@ static int smu_v11_0_get_current_activity_percent(struct smu_context *smu,
return 0;
}
+static int smu_v11_0_thermal_get_temperature(struct smu_context *smu, uint32_t *value)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t temp = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
+ temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
+ CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
+
+ temp = temp & 0x1ff;
+ temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ *value = temp;
+
+ return 0;
+}
+
static int smu_v11_0_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
@@ -1028,6 +1050,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_get_current_clk_freq(smu, PPCLK_GFXCLK, (uint32_t *)data);
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_GPU_TEMP:
+ ret = smu_v11_0_thermal_get_temperature(smu, (uint32_t *)data);
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 16eb5a1..55e1b8d 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -794,6 +794,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.populate_umd_state_clk = vega20_populate_umd_state_clk,
.print_clk_levels = vega20_print_clk_levels,
.force_clk_levels = vega20_force_clk_levels,
+
};
void vega20_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index ceba4f7..419dae3 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -28,7 +28,6 @@
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
-
struct vega20_dpm_level {
bool enabled;
uint32_t value;
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 085/138] drm/amd/powerplay: implement sensor of get_gpu_power for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (83 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 084/138] drm/amd/powerplay: implement sensor of thermal_get_temperature " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 086/138] drm/amd/powerplay: implement sensor of get_gfx_vdd " Huang Rui
` (53 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add sensor interface of get gpu power for debugfs and hwmon.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 25dbeec..031812c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1032,6 +1032,23 @@ static int smu_v11_0_thermal_get_temperature(struct smu_context *smu, uint32_t *
return 0;
}
+static int smu_v11_0_get_gpu_power(struct smu_context *smu, uint32_t *value)
+{
+ int ret = 0;
+ SmuMetrics_t metrics;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, TABLE_SMU_METRICS, (void *)&metrics, false);
+ if (ret)
+ return ret;
+
+ *value = metrics.CurrSocketPower << 8;
+
+ return 0;
+}
+
static int smu_v11_0_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
@@ -1054,6 +1071,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_v11_0_thermal_get_temperature(smu, (uint32_t *)data);
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_GPU_POWER:
+ ret = smu_v11_0_get_gpu_power(smu, (uint32_t *)data);
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 086/138] drm/amd/powerplay: implement sensor of get_gfx_vdd for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (84 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 085/138] drm/amd/powerplay: implement sensor of get_gpu_power " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 087/138] drm/amd/powerplay: implement sensor of get feature mask Huang Rui
` (52 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add sensor interface of gfx vdd for hwmon
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 31 ++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 031812c..63acb2a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -38,6 +38,8 @@
#include "asic_reg/mp/mp_9_0_offset.h"
#include "asic_reg/mp/mp_9_0_sh_mask.h"
#include "asic_reg/nbio/nbio_7_4_offset.h"
+#include "asic_reg/smuio/smuio_9_0_offset.h"
+#include "asic_reg/smuio/smuio_9_0_sh_mask.h"
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
@@ -46,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
#define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255
#define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
+#define SMU11_VOLTAGE_SCALE 4
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
@@ -1049,6 +1052,30 @@ static int smu_v11_0_get_gpu_power(struct smu_context *smu, uint32_t *value)
return 0;
}
+static uint16_t convert_to_vddc(uint8_t vid)
+{
+ return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
+}
+
+static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t vdd = 0, val_vid = 0;
+
+ if (!value)
+ return -EINVAL;
+ val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
+ SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
+ SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
+
+ vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
+
+ *value = vdd;
+
+ return 0;
+
+}
+
static int smu_v11_0_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
@@ -1075,6 +1102,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_v11_0_get_gpu_power(smu, (uint32_t *)data);
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_VDDGFX:
+ ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index 419dae3..ceba4f7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -28,6 +28,7 @@
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
+
struct vega20_dpm_level {
bool enabled;
uint32_t value;
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 087/138] drm/amd/powerplay: implement sensor of get feature mask
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (85 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 086/138] drm/amd/powerplay: implement sensor of get_gfx_vdd " Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 088/138] drm/amd/powerplay: implement sysfs of get num states function Huang Rui
` (51 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add sensor interface of feature mask for debugfs.
this interface is not ip related function, so need move high level
file to implement (amdgpu_smu)
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 21 +++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 52babf5..9ad6e67 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,27 @@
#include "smu_v11_0.h"
#include "atom.h"
+int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+ ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
+ *size = 8;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ *size = 0;
+
+ return ret;
+}
+
int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_data, bool drv2smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 5bbf6a2..c2d28b1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -376,6 +376,8 @@ extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bo
int smu_update_table(struct smu_context *smu, uint32_t table_id, void *table_data, bool drv2smu);
bool is_support_sw_smu(struct amdgpu_device *adev);
int smu_reset(struct smu_context *smu);
+int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ void *data, uint32_t *size);
int smu_sys_get_pp_table(struct smu_context *smu, void **table);
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 63acb2a..610bf0e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1107,7 +1107,7 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
- ret = -EINVAL;
+ ret = smu_common_read_sensor(smu, sensor, data, size);
break;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 088/138] drm/amd/powerplay: implement sysfs of get num states function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (86 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 087/138] drm/amd/powerplay: implement sensor of get feature mask Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 089/138] drm/amd/powerplay: implement sysfs of pp_cur_state function Huang Rui
` (50 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add function smu_get_power_num_state function for sw-smu.
it's only for sysfs interface, the power state feature is not ready for sw-smu.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 7 ++++++-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 12 ++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5184251..15a3020 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -350,10 +350,15 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
struct pp_states_info data;
- int i, buf_len;
+ int i, buf_len, ret;
if (adev->powerplay.pp_funcs->get_pp_num_states)
amdgpu_dpm_get_pp_num_states(adev, &data);
+ else if (is_support_sw_smu(adev)) {
+ ret = smu_get_power_num_states(&adev->smu, &data);
+ if (ret)
+ return ret;
+ }
buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
for (i = 0; i < data.nums; i++)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9ad6e67..d66303c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,18 @@
#include "smu_v11_0.h"
#include "atom.h"
+int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info)
+{
+ if (!state_info)
+ return -EINVAL;
+
+ /* not support power state */
+ memset(state_info, 0, sizeof(struct pp_states_info));
+ state_info->nums = 0;
+
+ return 0;
+}
+
int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c2d28b1..c97760f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -380,5 +380,6 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
int smu_sys_get_pp_table(struct smu_context *smu, void **table);
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
+int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
#endif
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 089/138] drm/amd/powerplay: implement sysfs of pp_cur_state function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (87 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 088/138] drm/amd/powerplay: implement sysfs of get num states function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 090/138] drm/amd/powerplay: implement sysfs of pp_force_state for sw-smu Huang Rui
` (49 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
add function of smu_get_currente_state for sw-smu.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 22 ++++++++++++++--------
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
3 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 15a3020..5468b8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -378,23 +378,29 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
struct pp_states_info data;
+ struct smu_context *smu = &adev->smu;
enum amd_pm_state_type pm = 0;
- int i = 0;
+ int i = 0, ret = 0;
if (adev->powerplay.pp_funcs->get_current_power_state
&& adev->powerplay.pp_funcs->get_pp_num_states) {
pm = amdgpu_dpm_get_current_power_state(adev);
amdgpu_dpm_get_pp_num_states(adev, &data);
+ } else if (is_support_sw_smu(adev)) {
+ pm = smu_get_current_power_state(smu);
+ ret = smu_get_power_num_states(smu, &data);
+ if (ret);
+ return ret;
+ }
- for (i = 0; i < data.nums; i++) {
- if (pm == data.states[i])
- break;
- }
-
- if (i == data.nums)
- i = -EINVAL;
+ for (i = 0; i < data.nums; i++) {
+ if (pm == data.states[i])
+ break;
}
+ if (i == data.nums)
+ i = -EINVAL;
+
return snprintf(buf, PAGE_SIZE, "%d\n", i);
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d66303c..df3df2f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,12 @@
#include "smu_v11_0.h"
#include "atom.h"
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+{
+ /* not support power state */
+ return POWER_STATE_TYPE_DEFAULT;
+}
+
int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info)
{
if (!state_info)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c97760f..6238b60 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -381,5 +381,6 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
int smu_sys_get_pp_table(struct smu_context *smu, void **table);
int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
+enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
#endif
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 090/138] drm/amd/powerplay: implement sysfs of pp_force_state for sw-smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (88 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 089/138] drm/amd/powerplay: implement sysfs of pp_cur_state function Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 091/138] drm/amd/powerplay: add the function to set deep sleep dcefclk Huang Rui
` (48 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <Kevin1.Wang@amd.com>
the SMU v11 doesn’t support pp_force_state so far, so we didn’t implement
it.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5468b8d..2c12a80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -450,6 +450,8 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
AMD_PP_TASK_ENABLE_USER_STATE, &state);
adev->pp_force_state_enabled = true;
}
+ } else if (is_support_sw_smu(adev)) {
+ adev->pp_force_state_enabled = false;
}
fail:
return count;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 091/138] drm/amd/powerplay: add the function to set deep sleep dcefclk
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (89 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 090/138] drm/amd/powerplay: implement sysfs of pp_force_state for sw-smu Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:24 ` [PATCH 092/138] drm/amd/powerplay: add two interfaces to set_active_display_count and store_cc6_data Huang Rui
` (47 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds the function to set deep sleep dcefclk. It will be used on
display part.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 ++++++++++++++-------
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 6238b60..57975e1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -263,6 +263,7 @@ struct smu_funcs
int (*start_thermal_control)(struct smu_context *smu);
int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
+ int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
};
#define smu_init_microcode(smu) \
@@ -358,6 +359,8 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
#define smu_get_unallowed_feature_mask(smu, feature_mask, num) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+#define smu_set_deep_sleep_dcefclk(smu, clk) \
+ ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 610bf0e..17da50f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -601,21 +601,27 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+{
+ int ret;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMinDeepSleepDcefclk, clk);
+ if (ret)
+ pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
+
+ return ret;
+}
+
static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
{
- int ret = 0;
struct smu_table_context *table_context = &smu->smu_table;
if (!table_context)
return -EINVAL;
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_SetMinDeepSleepDcefclk,
+ return smu_set_deep_sleep_dcefclk(smu,
table_context->boot_values.dcefclk / 100);
- if (ret)
- pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
-
- return ret;
}
static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
@@ -1150,6 +1156,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
.start_thermal_control = smu_v11_0_start_thermal_control,
.read_sensor = smu_v11_0_read_sensor,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 092/138] drm/amd/powerplay: add two interfaces to set_active_display_count and store_cc6_data
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (90 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 091/138] drm/amd/powerplay: add the function to set deep sleep dcefclk Huang Rui
@ 2019-01-25 10:24 ` Huang Rui
2019-01-25 10:25 ` [PATCH 093/138] drm/amd/powerplay: add smu display configuration change function Huang Rui
` (46 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds two interfaces to set_active_display_count and store_cc6_data,
they won't be used for smu11, and just be the placeholders for future asic on
display to smu interface.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 57975e1..592ff29 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -264,6 +264,10 @@ struct smu_funcs
int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
+ int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
+ int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
+ bool cc6_disable, bool pstate_disable,
+ bool pstate_switch_disable);
};
#define smu_init_microcode(smu) \
@@ -361,6 +365,10 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
#define smu_set_deep_sleep_dcefclk(smu, clk) \
((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
+#define smu_set_active_display_count(smu, count) \
+ ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
+#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+ ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 093/138] drm/amd/powerplay: add smu display configuration change function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (91 preceding siblings ...)
2019-01-25 10:24 ` [PATCH 092/138] drm/amd/powerplay: add two interfaces to set_active_display_count and store_cc6_data Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 094/138] drm/amd/powerplay: add get_clock_by_type interface for display Huang Rui
` (45 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds display configuration change function that creates the new path
with sw smu driver instead of powerplay.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 5 ++++
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 34 ++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++++
3 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index e8e9eeb..814ee4e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -33,6 +33,7 @@
#include "amdgpu_dm_irq.h"
#include "amdgpu_pm.h"
#include "dm_pp_smu.h"
+#include "amdgpu_smu.h"
bool dm_pp_apply_display_requirements(
@@ -40,6 +41,7 @@ bool dm_pp_apply_display_requirements(
const struct dm_pp_display_configuration *pp_display_cfg)
{
struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = &adev->smu;
int i;
if (adev->pm.dpm_enabled) {
@@ -105,6 +107,9 @@ bool dm_pp_apply_display_requirements(
adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
+ else
+ smu_display_configuration_change(smu,
+ &adev->pm.pm_display_cfg);
amdgpu_pm_compute_clocks(adev);
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index df3df2f..9da4036 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -773,6 +773,40 @@ static int smu_resume(void *handle)
return ret;
}
+int smu_display_configuration_change(struct smu_context *smu,
+ const struct amd_pp_display_configuration *display_config)
+{
+ int index = 0;
+ int num_of_active_display = 0;
+
+ if (!is_support_sw_smu(smu->adev))
+ return -EINVAL;
+
+ if (!display_config)
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ smu_set_deep_sleep_dcefclk(smu,
+ display_config->min_dcef_deep_sleep_set_clk / 100);
+
+ for (index = 0; index < display_config->num_path_including_non_display; index++) {
+ if (display_config->displays[index].controller_id != 0)
+ num_of_active_display++;
+ }
+
+ smu_set_active_display_count(smu, num_of_active_display);
+
+ smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
+ display_config->cpu_cc6_disable,
+ display_config->cpu_pstate_disable,
+ display_config->nb_pstate_switch_disable);
+
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+}
+
static int smu_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 592ff29..d59706b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -24,6 +24,7 @@
#include "amdgpu.h"
#include "kgd_pp_interface.h"
+#include "dm_pp_interface.h"
enum smu_message_type
{
@@ -394,4 +395,9 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
+/* smu to display interface */
+extern int smu_display_configuration_change(struct smu_context *smu, const
+ struct amd_pp_display_configuration
+ *display_config);
+
#endif
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 094/138] drm/amd/powerplay: add get_clock_by_type interface for display
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (92 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 093/138] drm/amd/powerplay: add smu display configuration change function Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 095/138] drm/amd/powerplay: add interface to get max high clocks " Huang Rui
` (44 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds get_clock_by_type interface for display, in smu v11 didn't have
the implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 814ee4e..51c2515 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -313,6 +313,12 @@ bool dm_pp_get_clock_levels_by_type(
if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), &pp_clks)) {
/* Error in pplib. Provide default values. */
+ return true;
+ }
+ } else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
+ if (smu_get_clock_by_type(&adev->smu,
+ dc_to_pp_clock_type(clk_type),
+ &pp_clks)) {
get_default_clock_levels(clk_type, dc_clks);
return true;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index d59706b..a0bc8dd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -269,6 +269,9 @@ struct smu_funcs
int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
bool cc6_disable, bool pstate_disable,
bool pstate_switch_disable);
+ int (*get_clock_by_type)(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct amd_pp_clocks *clocks);
};
#define smu_init_microcode(smu) \
@@ -370,6 +373,8 @@ struct smu_funcs
((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+#define smu_get_clock_by_type(smu, type, clocks) \
+ ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 095/138] drm/amd/powerplay: add interface to get max high clocks for display
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (93 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 094/138] drm/amd/powerplay: add get_clock_by_type interface for display Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 096/138] drm/amd/powerplay: add interface to get clock by type with latency for display (v2) Huang Rui
` (43 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to get max high clocks for display and in smu v11
didn't have this implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 7 +++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 51c2515..f01e440 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -335,6 +335,13 @@ bool dm_pp_get_clock_levels_by_type(
validation_clks.memory_max_clock = 80000;
validation_clks.level = 0;
}
+ } else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {
+ if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
+ DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
+ validation_clks.engine_max_clock = 72000;
+ validation_clks.memory_max_clock = 80000;
+ validation_clks.level = 0;
+ }
}
DRM_INFO("DM_PPLIB: Validation clocks:\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a0bc8dd..256c11d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -272,6 +272,8 @@ struct smu_funcs
int (*get_clock_by_type)(struct smu_context *smu,
enum amd_pp_clock_type type,
struct amd_pp_clocks *clocks);
+ int (*get_max_high_clocks)(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks);
};
#define smu_init_microcode(smu) \
@@ -375,6 +377,8 @@ struct smu_funcs
((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
#define smu_get_clock_by_type(smu, type, clocks) \
((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
+#define smu_get_max_high_clocks(smu, clocks) \
+ ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 096/138] drm/amd/powerplay: add interface to get clock by type with latency for display (v2)
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (94 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 095/138] drm/amd/powerplay: add interface to get max high clocks " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 097/138] drm/amd/powerplay: add interface to get clock by type with voltage for display Huang Rui
` (42 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds get clock by type with latency, display will use it to get
current clocks with latency.
v2: fix the missed mutex lock before return.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 21 ++++++++----
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 +++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 40 +++++++++++++++++++++-
3 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f01e440..7d01f22 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -392,14 +392,21 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
void *pp_handle = adev->powerplay.pp_handle;
struct pp_clock_levels_with_latency pp_clks = { 0 };
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ int ret;
+
+ if (pp_funcs && pp_funcs->get_clock_by_type_with_latency) {
+ ret = pp_funcs->get_clock_by_type_with_latency(pp_handle,
+ dc_to_pp_clock_type(clk_type),
+ &pp_clks);
+ if (ret)
+ return false;
+ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
+ if (smu_get_clock_by_type_with_latency(&adev->smu,
+ dc_to_pp_clock_type(clk_type),
+ &pp_clks))
+ return false;
+ }
- if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
- return false;
-
- if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
- dc_to_pp_clock_type(clk_type),
- &pp_clks))
- return false;
pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 256c11d..8f841e5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -224,6 +224,11 @@ struct pptable_funcs {
int (*populate_umd_state_clk)(struct smu_context *smu);
int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
+ int (*get_clock_by_type_with_latency)(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct
+ pp_clock_levels_with_latency
+ *clocks);
};
struct smu_funcs
@@ -379,6 +384,9 @@ struct smu_funcs
((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
#define smu_get_max_high_clocks(smu, clocks) \
((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
+#define smu_get_clock_by_type_with_latency(smu, type, clocks) \
+ ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (type), (clocks)) : 0)
+
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 55e1b8d..ed0fbe7 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -782,6 +782,44 @@ static int vega20_force_clk_levels(struct smu_context *smu,
return 0;
}
+static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ int ret;
+ struct vega20_single_dpm_table *single_dpm_table;
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+
+ dpm_table = smu_dpm->dpm_context;
+
+ mutex_lock(&smu->mutex);
+
+ switch (type) {
+ case amd_pp_sys_clock:
+ single_dpm_table = &(dpm_table->gfx_table);
+ ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
+ break;
+ case amd_pp_mem_clock:
+ single_dpm_table = &(dpm_table->mem_table);
+ ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
+ break;
+ case amd_pp_dcef_clock:
+ single_dpm_table = &(dpm_table->dcef_table);
+ ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
+ break;
+ case amd_pp_soc_clock:
+ single_dpm_table = &(dpm_table->soc_table);
+ ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ mutex_unlock(&smu->mutex);
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -794,7 +832,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.populate_umd_state_clk = vega20_populate_umd_state_clk,
.print_clk_levels = vega20_print_clk_levels,
.force_clk_levels = vega20_force_clk_levels,
-
+ .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 097/138] drm/amd/powerplay: add interface to get clock by type with voltage for display
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (95 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 096/138] drm/amd/powerplay: add interface to get clock by type with latency for display (v2) Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 098/138] drm/amd/powerplay: add interface to request display clock voltage Huang Rui
` (41 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds inteface to get clock by type with voltage, display will use it
to get current clocks with voltage.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 20 +++++++++++++-------
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 +++++++
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 7d01f22..c60722e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -422,14 +422,20 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
void *pp_handle = adev->powerplay.pp_handle;
struct pp_clock_levels_with_voltage pp_clk_info = {0};
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ int ret;
- if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
- return false;
-
- if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
- dc_to_pp_clock_type(clk_type),
- &pp_clk_info))
- return false;
+ if (pp_funcs && pp_funcs->get_clock_by_type_with_voltage) {
+ ret = pp_funcs->get_clock_by_type_with_voltage(pp_handle,
+ dc_to_pp_clock_type(clk_type),
+ &pp_clk_info);
+ if (ret)
+ return false;
+ } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_voltage) {
+ if (smu_get_clock_by_type_with_voltage(&adev->smu,
+ dc_to_pp_clock_type(clk_type),
+ &pp_clk_info))
+ return false;
+ }
pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8f841e5..80d6615 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -229,6 +229,11 @@ struct pptable_funcs {
struct
pp_clock_levels_with_latency
*clocks);
+ int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
+ enum amd_pp_clock_type type,
+ struct
+ pp_clock_levels_with_voltage
+ *clocks);
};
struct smu_funcs
@@ -386,6 +391,8 @@ struct smu_funcs
((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
#define smu_get_clock_by_type_with_latency(smu, type, clocks) \
((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (type), (clocks)) : 0)
+#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
+ ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 098/138] drm/amd/powerplay: add interface to request display clock voltage
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (96 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 097/138] drm/amd/powerplay: add interface to get clock by type with voltage for display Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 099/138] drm/amd/powerplay: add interface to get dal power level Huang Rui
` (40 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to request display clock voltage, display will use it
to request current display clock voltage.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 17 ++++++---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 44 ++++++++++++++++++++++
3 files changed, 61 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index c60722e..06d2b39 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -476,6 +476,10 @@ bool dm_pp_apply_clock_for_voltage_request(
ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
adev->powerplay.pp_handle,
&pp_clock_request);
+ else if (adev->smu.funcs &&
+ adev->smu.funcs->display_clock_voltage_request)
+ ret = smu_display_clock_voltage_request(&adev->smu,
+ &pp_clock_request);
if (ret)
return false;
return true;
@@ -512,16 +516,19 @@ void pp_rv_set_display_requirement(struct pp_smu *pp,
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct pp_display_clock_request clock = {0};
- if (!pp_funcs || !pp_funcs->display_clock_voltage_request)
- return;
-
clock.clock_type = amd_pp_dcf_clock;
clock.clock_freq_in_khz = req->hard_min_dcefclk_mhz * 1000;
- pp_funcs->display_clock_voltage_request(pp_handle, &clock);
+ if (pp_funcs && pp_funcs->display_clock_voltage_request)
+ pp_funcs->display_clock_voltage_request(pp_handle, &clock);
+ else if (adev->smu.funcs && adev->smu.funcs->display_clock_voltage_request)
+ smu_display_clock_voltage_request(&adev->smu, &clock);
clock.clock_type = amd_pp_f_clock;
clock.clock_freq_in_khz = req->hard_min_fclk_mhz * 1000;
- pp_funcs->display_clock_voltage_request(pp_handle, &clock);
+ if (pp_funcs && pp_funcs->display_clock_voltage_request)
+ pp_funcs->display_clock_voltage_request(pp_handle, &clock);
+ else if (adev->smu.funcs && adev->smu.funcs->display_clock_voltage_request)
+ smu_display_clock_voltage_request(&adev->smu, &clock);
}
void pp_rv_set_wm_ranges(struct pp_smu *pp,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 80d6615..82d5773 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -284,6 +284,9 @@ struct smu_funcs
struct amd_pp_clocks *clocks);
int (*get_max_high_clocks)(struct smu_context *smu,
struct amd_pp_simple_clock_info *clocks);
+ int (*display_clock_voltage_request)(struct smu_context *smu, struct
+ pp_display_clock_request
+ *clock_req);
};
#define smu_init_microcode(smu) \
@@ -393,6 +396,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (type), (clocks)) : 0)
#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
+#define smu_display_clock_voltage_request(smu, clock_req) \
+ ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 17da50f..b5b272f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1123,6 +1123,49 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
return ret;
}
+static int
+smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ struct pp_display_clock_request
+ *clock_req)
+{
+ enum amd_pp_clock_type clk_type = clock_req->clock_type;
+ int ret = 0;
+ PPCLK_e clk_select = 0;
+ uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
+
+ mutex_lock(&smu->mutex);
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ switch (clk_type) {
+ case amd_pp_dcef_clock:
+ clk_select = PPCLK_DCEFCLK;
+ break;
+ case amd_pp_disp_clock:
+ clk_select = PPCLK_DISPCLK;
+ break;
+ case amd_pp_pixel_clock:
+ clk_select = PPCLK_PIXCLK;
+ break;
+ case amd_pp_phy_clock:
+ clk_select = PPCLK_PHYCLK;
+ break;
+ default:
+ pr_info("[%s] Invalid Clock Type!", __func__);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ goto failed;
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
+ (clk_select << 16) | clk_freq);
+ }
+
+failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1157,6 +1200,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.start_thermal_control = smu_v11_0_start_thermal_control,
.read_sensor = smu_v11_0_read_sensor,
.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 099/138] drm/amd/powerplay: add interface to get dal power level
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (97 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 098/138] drm/amd/powerplay: add interface to request display clock voltage Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 100/138] drm/amd/powerplay: add interface to get performance level Huang Rui
` (39 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to get dal power level for display and in smu v11
didn't have this implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 82d5773..708bc66 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -287,6 +287,8 @@ struct smu_funcs
int (*display_clock_voltage_request)(struct smu_context *smu, struct
pp_display_clock_request
*clock_req);
+ int (*get_dal_power_level)(struct smu_context *smu,
+ struct amd_pp_simple_clock_info *clocks);
};
#define smu_init_microcode(smu) \
@@ -398,6 +400,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
#define smu_display_clock_voltage_request(smu, clock_req) \
((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+#define smu_get_dal_power_level(smu, clocks) \
+ ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 100/138] drm/amd/powerplay: add interface to get performance level
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (98 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 099/138] drm/amd/powerplay: add interface to get dal power level Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 101/138] drm/amd/powerplay: add interface to get current shallow sleep clocks Huang Rui
` (38 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to get performance level for display and in smu v11
didn't have this implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 708bc66..03c06aa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -140,6 +140,20 @@ struct smu_table {
struct amdgpu_bo *bo;
};
+enum smu_perf_level_designation {
+ PERF_LEVEL_ACTIVITY,
+ PERF_LEVEL_POWER_CONTAINMENT,
+};
+
+struct smu_performance_level {
+ uint32_t core_clock;
+ uint32_t memory_clock;
+ uint32_t vddc;
+ uint32_t vddci;
+ uint32_t non_local_mem_freq;
+ uint32_t non_local_mem_width;
+};
+
struct smu_bios_boot_up_values
{
uint32_t revision;
@@ -289,6 +303,9 @@ struct smu_funcs
*clock_req);
int (*get_dal_power_level)(struct smu_context *smu,
struct amd_pp_simple_clock_info *clocks);
+ int (*get_perf_level)(struct smu_context *smu,
+ enum smu_perf_level_designation designation,
+ struct smu_performance_level *level);
};
#define smu_init_microcode(smu) \
@@ -402,6 +419,8 @@ struct smu_funcs
((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
#define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+#define smu_get_perf_level(smu, designation, level) \
+ ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 101/138] drm/amd/powerplay: add interface to get current shallow sleep clocks
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (99 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 100/138] drm/amd/powerplay: add interface to get performance level Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 102/138] drm/amd/powerplay: add interface to get current clocks for display Huang Rui
` (37 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to get current shallow sleep clocks for display and in
smu v11 didn't have this implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 03c06aa..a57b245 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -154,6 +154,15 @@ struct smu_performance_level {
uint32_t non_local_mem_width;
};
+struct smu_clock_info {
+ uint32_t min_mem_clk;
+ uint32_t max_mem_clk;
+ uint32_t min_eng_clk;
+ uint32_t max_eng_clk;
+ uint32_t min_bus_bandwidth;
+ uint32_t max_bus_bandwidth;
+};
+
struct smu_bios_boot_up_values
{
uint32_t revision;
@@ -306,6 +315,8 @@ struct smu_funcs
int (*get_perf_level)(struct smu_context *smu,
enum smu_perf_level_designation designation,
struct smu_performance_level *level);
+ int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
+ struct smu_clock_info *clocks);
};
#define smu_init_microcode(smu) \
@@ -421,6 +432,8 @@ struct smu_funcs
((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+ ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 102/138] drm/amd/powerplay: add interface to get current clocks for display
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (100 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 101/138] drm/amd/powerplay: add interface to get current shallow sleep clocks Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 103/138] drm/amd/powerplay: add interface to notify smu enable pme restore register Huang Rui
` (36 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch fills the amd_pp_clock_info data for display, it will get the current
info in that structure.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 2 +
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 78 ++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++
3 files changed, 84 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 06d2b39..9118575 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -497,6 +497,8 @@ bool dm_pp_get_static_clocks(
ret = adev->powerplay.pp_funcs->get_current_clocks(
adev->powerplay.pp_handle,
&pp_clk_info);
+ else if (adev->smu.funcs)
+ ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
if (ret)
return false;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9da4036..26f1833 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -807,6 +807,84 @@ int smu_display_configuration_change(struct smu_context *smu,
return 0;
}
+static int smu_get_clock_info(struct smu_context *smu,
+ struct smu_clock_info *clk_info,
+ enum smu_perf_level_designation designation)
+{
+ int ret;
+ struct smu_performance_level level = {0};
+
+ if (!clk_info)
+ return -EINVAL;
+
+ ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
+ if (ret)
+ return -EINVAL;
+
+ clk_info->min_mem_clk = level.memory_clock;
+ clk_info->min_eng_clk = level.core_clock;
+ clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
+
+ ret = smu_get_perf_level(smu, designation, &level);
+ if (ret)
+ return -EINVAL;
+
+ clk_info->min_mem_clk = level.memory_clock;
+ clk_info->min_eng_clk = level.core_clock;
+ clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
+
+ return 0;
+}
+
+int smu_get_current_clocks(struct smu_context *smu,
+ struct amd_pp_clock_info *clocks)
+{
+ struct amd_pp_simple_clock_info simple_clocks = {0};
+ struct smu_clock_info hw_clocks;
+ int ret = 0;
+
+ if (!is_support_sw_smu(smu->adev))
+ return -EINVAL;
+
+ mutex_lock(&smu->mutex);
+
+ smu_get_dal_power_level(smu, &simple_clocks);
+
+ if (smu->support_power_containment)
+ ret = smu_get_clock_info(smu, &hw_clocks,
+ PERF_LEVEL_POWER_CONTAINMENT);
+ else
+ ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
+
+ if (ret) {
+ pr_err("Error in smu_get_clock_info\n");
+ goto failed;
+ }
+
+ clocks->min_engine_clock = hw_clocks.min_eng_clk;
+ clocks->max_engine_clock = hw_clocks.max_eng_clk;
+ clocks->min_memory_clock = hw_clocks.min_mem_clk;
+ clocks->max_memory_clock = hw_clocks.max_mem_clk;
+ clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
+ clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
+ clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
+ clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
+
+ if (simple_clocks.level == 0)
+ clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
+ else
+ clocks->max_clocks_state = simple_clocks.level;
+
+ if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
+ clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
+ clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
+ }
+
+failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
+}
+
static int smu_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a57b245..08a3f79 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -233,6 +233,8 @@ struct smu_context
uint32_t power_limit;
uint32_t default_power_limit;
+
+ bool support_power_containment;
};
struct pptable_funcs {
@@ -464,5 +466,7 @@ enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
extern int smu_display_configuration_change(struct smu_context *smu, const
struct amd_pp_display_configuration
*display_config);
+extern int smu_get_current_clocks(struct smu_context *smu,
+ struct amd_pp_clock_info *clocks);
#endif
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 103/138] drm/amd/powerplay: add interface to notify smu enable pme restore register
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (101 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 102/138] drm/amd/powerplay: add interface to get current clocks for display Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 104/138] drm/amd/powerplay: implement interface to set watermarks for clock ranges Huang Rui
` (35 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch adds interface to notify smu enable pme restore register for display
and in smu v11 didn't have this implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 8 ++++----
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 9118575..f69299f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -593,10 +593,10 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- if (!pp_funcs || !pp_funcs->notify_smu_enable_pwe)
- return;
-
- pp_funcs->notify_smu_enable_pwe(pp_handle);
+ if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
+ pp_funcs->notify_smu_enable_pwe(pp_handle);
+ else if (adev->smu.funcs)
+ smu_notify_smu_enable_pwe(&adev->smu);
}
void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 08a3f79..ff22446 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -319,6 +319,7 @@ struct smu_funcs
struct smu_performance_level *level);
int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
struct smu_clock_info *clocks);
+ int (*notify_smu_enable_pwe)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -436,6 +437,8 @@ struct smu_funcs
((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+#define smu_notify_smu_enable_pwe(smu) \
+ ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 104/138] drm/amd/powerplay: implement interface to set watermarks for clock ranges
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (102 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 103/138] drm/amd/powerplay: add interface to notify smu enable pme restore register Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 105/138] drm/amd/powerplay: add function to store overdrive information for smu11 Huang Rui
` (34 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch implements inteferface to set watermarks table for clock ranges on
smu 11. It fills watermark table before it is written to SMC.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 11 +--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 80 ++++++++++++++++++++++
4 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f69299f..4e6c449 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -548,9 +548,6 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
- if (!pp_funcs || !pp_funcs->set_watermarks_for_clocks_ranges)
- return;
-
for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
if (ranges->reader_wm_sets[i].wm_inst > 3)
wm_dce_clocks[i].wm_set_id = WM_SET_A;
@@ -583,7 +580,13 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
}
- pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, &wm_with_clock_ranges);
+ if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
+ pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
+ &wm_with_clock_ranges);
+ else if (adev->smu.funcs &&
+ adev->smu.funcs->set_watermarks_for_clock_ranges)
+ smu_set_watermarks_for_clock_ranges(&adev->smu,
+ &wm_with_clock_ranges);
}
void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 26f1833..d1ef248 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -322,6 +322,7 @@ static int smu_sw_init(void *handle)
bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
+ smu->watermarks_bitmap = 0;
ret = smu_init_microcode(smu);
if (ret) {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ff22446..e58b49a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -235,6 +235,11 @@ struct smu_context
uint32_t default_power_limit;
bool support_power_containment;
+ bool disable_watermark;
+
+#define WATERMARKS_EXIST (1 << 0)
+#define WATERMARKS_LOADED (1 << 1)
+ uint32_t watermarks_bitmap;
};
struct pptable_funcs {
@@ -320,6 +325,8 @@ struct smu_funcs
int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
struct smu_clock_info *clocks);
int (*notify_smu_enable_pwe)(struct smu_context *smu);
+ int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
};
#define smu_init_microcode(smu) \
@@ -439,6 +446,8 @@ struct smu_funcs
((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
#define smu_notify_smu_enable_pwe(smu) \
((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
+#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
+ ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index b5b272f..f5e18a2 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1166,6 +1166,85 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
return ret;
}
+static int smu_v11_0_set_watermarks_table(struct smu_context *smu,
+ Watermarks_t *table, struct
+ dm_pp_wm_sets_with_clock_ranges_soc15
+ *clock_ranges)
+{
+ int i;
+
+ if (!table || !clock_ranges)
+ return -EINVAL;
+
+ if (clock_ranges->num_wm_dmif_sets > 4 ||
+ clock_ranges->num_wm_mcif_sets > 4)
+ return -EINVAL;
+
+ for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
+ table->WatermarkRow[1][i].MinClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].MaxClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].MinUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].MaxUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[1][i].WmSetting = (uint8_t)
+ clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
+ }
+
+ for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
+ table->WatermarkRow[0][i].MinClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].MaxClock =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].MinUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].MaxUclk =
+ cpu_to_le16((uint16_t)
+ (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
+ 1000));
+ table->WatermarkRow[0][i].WmSetting = (uint8_t)
+ clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
+ }
+
+ return 0;
+}
+
+static int
+smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
+ dm_pp_wm_sets_with_clock_ranges_soc15
+ *clock_ranges)
+{
+ int ret = 0;
+ struct smu_table *watermarks = &smu->smu_table.tables[TABLE_WATERMARKS];
+ Watermarks_t *table = watermarks->cpu_addr;
+
+ if (!smu->disable_watermark &&
+ smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
+ smu_v11_0_set_watermarks_table(smu, table, clock_ranges);
+ smu->watermarks_bitmap |= WATERMARKS_EXIST;
+ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+ }
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1201,6 +1280,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.read_sensor = smu_v11_0_read_sensor,
.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+ .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 105/138] drm/amd/powerplay: add function to store overdrive information for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (103 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 104/138] drm/amd/powerplay: implement interface to set watermarks for clock ranges Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 106/138] drm/amd/powerplay: add function to set default overdrive settings Huang Rui
` (33 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add vega20_setup_od8_information function to store overdrive information
from powerplay_table to smu_table which will used when setting od8.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 15 +++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 86 +++++++++++++++++++++++++-
3 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d1ef248..3cc26ad 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -682,6 +682,21 @@ static int smu_hw_fini(void *handle)
table_context->max_sustainable_clocks = NULL;
}
+ if (table_context->od_feature_capabilities) {
+ kfree(table_context->od_feature_capabilities);
+ table_context->od_feature_capabilities = NULL;
+ }
+
+ if (table_context->od_settings_max) {
+ kfree(table_context->od_settings_max);
+ table_context->od_settings_max = NULL;
+ }
+
+ if (table_context->od_settings_min) {
+ kfree(table_context->od_settings_min);
+ table_context->od_settings_min = NULL;
+ }
+
ret = smu_fini_fb_allocations(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index e58b49a..2723955 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -192,6 +192,10 @@ struct smu_table_context
struct smu_table memory_pool;
uint16_t software_shutdown_temp;
uint8_t thermal_controller_type;
+
+ uint8_t *od_feature_capabilities;
+ uint32_t *od_settings_max;
+ uint32_t *od_settings_min;
};
struct smu_dpm_context {
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index ed0fbe7..df34953 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -146,10 +146,92 @@ static int vega20_allocate_dpm_context(struct smu_context *smu)
return 0;
}
+static int vega20_setup_od8_information(struct smu_context *smu)
+{
+ ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
+ struct smu_table_context *table_context = &smu->smu_table;
+
+ uint32_t od_feature_count, od_feature_array_size,
+ od_setting_count, od_setting_array_size;
+
+ if (!table_context->power_play_table)
+ return -EINVAL;
+
+ powerplay_table = table_context->power_play_table;
+
+ if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
+ /* Setup correct ODFeatureCount, and store ODFeatureArray from
+ * powerplay table to od_feature_capabilities */
+ od_feature_count =
+ (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
+ ATOM_VEGA20_ODFEATURE_COUNT) ?
+ ATOM_VEGA20_ODFEATURE_COUNT :
+ le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
+
+ od_feature_array_size = sizeof(uint8_t) * od_feature_count;
+
+ if (table_context->od_feature_capabilities)
+ return -EINVAL;
+
+ table_context->od_feature_capabilities = kzalloc(od_feature_array_size, GFP_KERNEL);
+ if (!table_context->od_feature_capabilities)
+ return -ENOMEM;
+
+ memcpy(table_context->od_feature_capabilities,
+ &powerplay_table->OverDrive8Table.ODFeatureCapabilities,
+ od_feature_array_size);
+
+ /* Setup correct ODSettingCount, and store ODSettingArray from
+ * powerplay table to od_settings_max and od_setting_min */
+ od_setting_count =
+ (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
+ ATOM_VEGA20_ODSETTING_COUNT) ?
+ ATOM_VEGA20_ODSETTING_COUNT :
+ le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
+
+ od_setting_array_size = sizeof(uint32_t) * od_setting_count;
+
+ if (table_context->od_settings_max)
+ return -EINVAL;
+
+ table_context->od_settings_max = kzalloc(od_setting_array_size, GFP_KERNEL);
+
+ if (!table_context->od_settings_max) {
+ kfree(table_context->od_feature_capabilities);
+ table_context->od_feature_capabilities = NULL;
+ return -ENOMEM;
+ }
+
+ memcpy(table_context->od_settings_max,
+ &powerplay_table->OverDrive8Table.ODSettingsMax,
+ od_setting_array_size);
+
+ if (table_context->od_settings_min)
+ return -EINVAL;
+
+ table_context->od_settings_min = kzalloc(od_setting_array_size, GFP_KERNEL);
+
+ if (!table_context->od_settings_min) {
+ kfree(table_context->od_feature_capabilities);
+ table_context->od_feature_capabilities = NULL;
+ kfree(table_context->od_settings_max);
+ table_context->od_settings_max = NULL;
+ return -ENOMEM;
+ }
+
+ memcpy(table_context->od_settings_min,
+ &powerplay_table->OverDrive8Table.ODSettingsMin,
+ od_setting_array_size);
+ }
+
+ return 0;
+}
+
static int vega20_store_powerplay_table(struct smu_context *smu)
{
ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
struct smu_table_context *table_context = &smu->smu_table;
+ int ret;
if (!table_context->power_play_table)
return -EINVAL;
@@ -162,7 +244,9 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
- return 0;
+ ret = vega20_setup_od8_information(smu);
+
+ return ret;
}
static int vega20_append_powerplay_table(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 106/138] drm/amd/powerplay: add function to set default overdrive settings
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (104 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 105/138] drm/amd/powerplay: add function to store overdrive information for smu11 Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 107/138] drm/amd/powerplay: add golden dpm table to backup default DPM table Huang Rui
` (32 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function of vega20_set_default_od8_setttings for vega20 with smu11
arch to setup default overdrive value.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 14 ++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 84 ++++------
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 203 +++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 51 +++++++
5 files changed, 309 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 3cc26ad..f4b6ae2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -526,6 +526,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_set_od8_default_settings(smu);
+ if (ret)
+ return ret;
+
ret = smu_populate_umd_state_clk(smu);
if (ret)
return ret;
@@ -697,6 +701,16 @@ static int smu_hw_fini(void *handle)
table_context->od_settings_min = NULL;
}
+ if (table_context->overdrive_table) {
+ kfree(table_context->overdrive_table);
+ table_context->overdrive_table = NULL;
+ }
+
+ if (table_context->od8_settings) {
+ kfree(table_context->od8_settings);
+ table_context->od8_settings = NULL;
+ }
+
ret = smu_fini_fb_allocations(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 2723955..ef8e301 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -196,6 +196,8 @@ struct smu_table_context
uint8_t *od_feature_capabilities;
uint32_t *od_settings_max;
uint32_t *od_settings_min;
+ void *overdrive_table;
+ void *od8_settings;
};
struct smu_dpm_context {
@@ -258,6 +260,7 @@ struct pptable_funcs {
int (*populate_umd_state_clk)(struct smu_context *smu);
int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
+ int (*set_default_od8_settings)(struct smu_context *smu);
int (*get_clock_by_type_with_latency)(struct smu_context *smu,
enum amd_pp_clock_type type,
struct
@@ -331,6 +334,7 @@ struct smu_funcs
int (*notify_smu_enable_pwe)(struct smu_context *smu);
int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+ int (*set_od8_default_settings)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -377,6 +381,8 @@ struct smu_funcs
((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
#define smu_init_max_sustainable_clocks(smu) \
((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+#define smu_set_od8_default_settings(smu) \
+ ((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu)) : 0)
#define smu_send_smc_msg(smu, msg) \
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
@@ -407,6 +413,8 @@ struct smu_funcs
((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
#define smu_populate_umd_state_clk(smu) \
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+#define smu_set_default_od8_settings(smu) \
+ ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
#define smu_get_power_limit(smu) \
((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
#define smu_get_current_clk_freq(smu, clk_id, value) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f5e18a2..3c4c327e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -542,61 +542,12 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
return ret;
}
-static int smu_v11_0_copy_table_to_smc(struct smu_context *smu,
- uint32_t table_id)
-{
- struct smu_table_context *table_context = &smu->smu_table;
- struct smu_table *driver_pptable = &smu->smu_table.tables[table_id];
- int ret = 0;
-
- if (table_id >= TABLE_COUNT) {
- pr_err("Invalid SMU Table ID for smu11!");
- return -EINVAL;
- }
-
- if (!driver_pptable->cpu_addr) {
- pr_err("Invalid virtual address for smu11!");
- return -EINVAL;
- }
- if (!driver_pptable->mc_address) {
- pr_err("Invalid MC address for smu11!");
- return -EINVAL;
- }
- if (!driver_pptable->size) {
- pr_err("Invalid SMU Table size for smu11!");
- return -EINVAL;
- }
-
- memcpy(driver_pptable->cpu_addr, table_context->driver_pptable,
- driver_pptable->size);
-
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
- upper_32_bits(driver_pptable->mc_address));
- if (ret) {
- pr_err("[CopyTableToSMC] Attempt to Set Dram Addr High Failed!");
- return ret;
- }
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
- lower_32_bits(driver_pptable->mc_address));
- if (ret) {
- pr_err("[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!");
- return ret;
- }
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_TransferTableDram2Smu,
- table_id);
- if (ret) {
- pr_err("[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!");
- return ret;
- }
-
- return 0;
-}
-
static int smu_v11_0_write_pptable(struct smu_context *smu)
{
+ struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
- ret = smu_v11_0_copy_table_to_smc(smu, TABLE_PPTABLE);
+ ret = smu_update_table(smu, TABLE_PPTABLE, table_context->driver_pptable, true);
return ret;
}
@@ -1245,6 +1196,36 @@ smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
return ret;
}
+static int smu_v11_0_set_od8_default_settings(struct smu_context *smu)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ int ret;
+
+ if (table_context->overdrive_table)
+ return -EINVAL;
+
+ table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
+
+ if (!table_context->overdrive_table)
+ return -ENOMEM;
+
+ ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
+ if (ret) {
+ pr_err("Failed to export over drive table!\n");
+ return ret;
+ }
+
+ smu_set_default_od8_settings(smu);
+
+ ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
+ if (ret) {
+ pr_err("Failed to import over drive table!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1281,6 +1262,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+ .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index df34953..c398899 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -904,6 +904,208 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
return ret;
}
+static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
+ uint32_t *voltage,
+ uint32_t freq)
+{
+ int ret;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_GetAVFSVoltageByDpm,
+ ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
+ if (ret) {
+ pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
+ return ret;
+ }
+
+ smu_read_smc_arg(smu, voltage);
+ *voltage = *voltage / VOLTAGE_SCALE;
+
+ return 0;
+}
+
+static int vega20_set_default_od8_setttings(struct smu_context *smu)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
+ struct vega20_od8_settings *od8_settings = NULL;
+ PPTable_t *smc_pptable = table_context->driver_pptable;
+ int i, ret;
+
+ if (table_context->od8_settings)
+ return -EINVAL;
+
+ table_context->od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
+
+ if (!table_context->od8_settings)
+ return -ENOMEM;
+
+ memset(table_context->od8_settings, 0, sizeof(struct vega20_od8_settings));
+ od8_settings = (struct vega20_od8_settings *)table_context->od8_settings;
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
+ table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
+ table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
+ (table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
+ table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
+ OD8_GFXCLK_LIMITS;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
+ OD8_GFXCLK_LIMITS;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
+ od_table->GfxclkFmin;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
+ od_table->GfxclkFmax;
+ }
+
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
+ (table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
+ smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
+ (table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
+ smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
+ (table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
+ table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
+ OD8_GFXCLK_CURVE;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
+ OD8_GFXCLK_CURVE;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
+ OD8_GFXCLK_CURVE;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
+ OD8_GFXCLK_CURVE;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
+ OD8_GFXCLK_CURVE;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
+ OD8_GFXCLK_CURVE;
+
+ od_table->GfxclkFreq1 = od_table->GfxclkFmin;
+ od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
+ od_table->GfxclkFreq3 = od_table->GfxclkFmax;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
+ od_table->GfxclkFreq1;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
+ od_table->GfxclkFreq2;
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
+ od_table->GfxclkFreq3;
+
+ ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
+ &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
+ od_table->GfxclkFreq1);
+ if (ret)
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
+ od_table->GfxclkVolt1 =
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
+ * VOLTAGE_SCALE;
+ ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
+ &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
+ od_table->GfxclkFreq2);
+ if (ret)
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
+ od_table->GfxclkVolt2 =
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
+ * VOLTAGE_SCALE;
+ ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
+ &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
+ od_table->GfxclkFreq3);
+ if (ret)
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
+ od_table->GfxclkVolt3 =
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
+ * VOLTAGE_SCALE;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
+ table_context->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
+ table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
+ (table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
+ table_context->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
+ od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
+ OD8_UCLK_MAX;
+ od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
+ od_table->UclkFmax;
+ }
+ }
+
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
+ table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
+ table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
+ table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
+ table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
+ od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
+ OD8_POWER_LIMIT;
+ od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
+ od_table->OverDrivePct;
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_FAN_CONTROL_BIT)) {
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
+ table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
+ table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
+ (table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
+ table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
+ od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
+ OD8_ACOUSTIC_LIMIT_SCLK;
+ od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
+ od_table->FanMaximumRpm;
+ }
+
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
+ table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
+ table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
+ (table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
+ table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
+ od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
+ OD8_FAN_SPEED_MIN;
+ od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
+ od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_THERMAL_BIT)) {
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
+ table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
+ table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
+ (table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
+ table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
+ od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
+ OD8_TEMPERATURE_FAN;
+ od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
+ od_table->FanTargetTemperature;
+ }
+
+ if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
+ table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
+ table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
+ (table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
+ table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
+ od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
+ OD8_TEMPERATURE_SYSTEM;
+ od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
+ od_table->MaxOpTemp;
+ }
+ }
+
+ for (i = 0; i < OD8_SETTING_COUNT; i++) {
+ if (od8_settings->od8_settings_array[i].feature_id) {
+ od8_settings->od8_settings_array[i].min_value =
+ table_context->od_settings_min[i];
+ od8_settings->od8_settings_array[i].max_value =
+ table_context->od_settings_max[i];
+ od8_settings->od8_settings_array[i].current_value =
+ od8_settings->od8_settings_array[i].default_value;
+ } else {
+ od8_settings->od8_settings_array[i].min_value = 0;
+ od8_settings->od8_settings_array[i].max_value = 0;
+ od8_settings->od8_settings_array[i].current_value = 0;
+ }
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -917,6 +1119,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.print_clk_levels = vega20_print_clk_levels,
.force_clk_levels = vega20_force_clk_levels,
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
+ .set_default_od8_settings = vega20_set_default_od8_setttings,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index ceba4f7..9b229b2 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -29,6 +29,10 @@
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
+#define VOLTAGE_SCALE 4
+#define AVFS_CURVE 0
+#define OD8_HOTCURVE_TEMPERATURE 85
+
struct vega20_dpm_level {
bool enabled;
uint32_t value;
@@ -70,6 +74,53 @@ struct vega20_dpm_table {
struct vega20_pcie_table pcie_table;
};
+enum OD8_FEATURE_ID
+{
+ OD8_GFXCLK_LIMITS = 1 << 0,
+ OD8_GFXCLK_CURVE = 1 << 1,
+ OD8_UCLK_MAX = 1 << 2,
+ OD8_POWER_LIMIT = 1 << 3,
+ OD8_ACOUSTIC_LIMIT_SCLK = 1 << 4, //FanMaximumRpm
+ OD8_FAN_SPEED_MIN = 1 << 5, //FanMinimumPwm
+ OD8_TEMPERATURE_FAN = 1 << 6, //FanTargetTemperature
+ OD8_TEMPERATURE_SYSTEM = 1 << 7, //MaxOpTemp
+ OD8_MEMORY_TIMING_TUNE = 1 << 8,
+ OD8_FAN_ZERO_RPM_CONTROL = 1 << 9
+};
+
+enum OD8_SETTING_ID
+{
+ OD8_SETTING_GFXCLK_FMIN = 0,
+ OD8_SETTING_GFXCLK_FMAX,
+ OD8_SETTING_GFXCLK_FREQ1,
+ OD8_SETTING_GFXCLK_VOLTAGE1,
+ OD8_SETTING_GFXCLK_FREQ2,
+ OD8_SETTING_GFXCLK_VOLTAGE2,
+ OD8_SETTING_GFXCLK_FREQ3,
+ OD8_SETTING_GFXCLK_VOLTAGE3,
+ OD8_SETTING_UCLK_FMAX,
+ OD8_SETTING_POWER_PERCENTAGE,
+ OD8_SETTING_FAN_ACOUSTIC_LIMIT,
+ OD8_SETTING_FAN_MIN_SPEED,
+ OD8_SETTING_FAN_TARGET_TEMP,
+ OD8_SETTING_OPERATING_TEMP_MAX,
+ OD8_SETTING_AC_TIMING,
+ OD8_SETTING_FAN_ZERO_RPM_CONTROL,
+ OD8_SETTING_COUNT
+};
+
+struct vega20_od8_single_setting {
+ uint32_t feature_id;
+ int32_t min_value;
+ int32_t max_value;
+ int32_t current_value;
+ int32_t default_value;
+};
+
+struct vega20_od8_settings {
+ struct vega20_od8_single_setting od8_settings_array[OD8_SETTING_COUNT];
+};
+
extern void vega20_set_ppt_funcs(struct smu_context *smu);
#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 107/138] drm/amd/powerplay: add golden dpm table to backup default DPM table
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (105 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 106/138] drm/amd/powerplay: add function to set default overdrive settings Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 108/138] drm/amd/powerplay: print overdrive percentage information for smu11 Huang Rui
` (31 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Backup default DPM table into golden dpm table.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 ++-
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 14 ++++++++++++++
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f4b6ae2..2e3e084 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -671,11 +671,22 @@ static int smu_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
struct smu_table_context *table_context = &smu->smu_table;
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
int ret = 0;
if (!is_support_sw_smu(adev))
return -EINVAL;
+ if (smu_dpm->dpm_context) {
+ kfree(smu_dpm->dpm_context);
+ smu_dpm->dpm_context = NULL;
+ }
+
+ if (smu_dpm->golden_dpm_context) {
+ kfree(smu_dpm->golden_dpm_context);
+ smu_dpm->golden_dpm_context = NULL;
+ }
+
if (table_context->driver_pptable) {
kfree(table_context->driver_pptable);
table_context->driver_pptable = NULL;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ef8e301..3ef752f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -201,8 +201,9 @@ struct smu_table_context
};
struct smu_dpm_context {
- void *dpm_context;
uint32_t dpm_context_size;
+ void *dpm_context;
+ void *golden_dpm_context;
};
struct smu_power_context {
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c398899..aa7f41a 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -136,11 +136,22 @@ static int vega20_allocate_dpm_context(struct smu_context *smu)
{
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ if (smu_dpm->dpm_context)
+ return -EINVAL;
+
smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
GFP_KERNEL);
if (!smu_dpm->dpm_context)
return -ENOMEM;
+ if (smu_dpm->golden_dpm_context)
+ return -EINVAL;
+
+ smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
+ GFP_KERNEL);
+ if (!smu_dpm->golden_dpm_context)
+ return -ENOMEM;
+
smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
return 0;
@@ -610,6 +621,9 @@ static int vega20_set_default_dpm_table(struct smu_context *smu)
}
vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
+ memcpy(smu_dpm->golden_dpm_context, dpm_table,
+ sizeof(struct vega20_dpm_table));
+
return 0;
}
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 108/138] drm/amd/powerplay: print overdrive percentage information for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (106 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 107/138] drm/amd/powerplay: add golden dpm table to backup default DPM table Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 109/138] drm/amd/powerplay: get overdrive clock and voltage information Huang Rui
` (30 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function to get sclk or mclk overdrive percentage information for smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8 ++++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 37 ++++++++++++++++++++++++++
3 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2c12a80..90f06ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1017,7 +1017,9 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
uint32_t value = 0;
- if (adev->powerplay.pp_funcs->get_sclk_od)
+ if (is_support_sw_smu(adev))
+ value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
+ else if (adev->powerplay.pp_funcs->get_sclk_od)
value = amdgpu_dpm_get_sclk_od(adev);
return snprintf(buf, PAGE_SIZE, "%d\n", value);
@@ -1061,7 +1063,9 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
uint32_t value = 0;
- if (adev->powerplay.pp_funcs->get_mclk_od)
+ if (is_support_sw_smu(adev))
+ value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
+ else if (adev->powerplay.pp_funcs->get_mclk_od)
value = amdgpu_dpm_get_mclk_od(adev);
return snprintf(buf, PAGE_SIZE, "%d\n", value);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 3ef752f..71b2703 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -262,6 +262,7 @@ struct pptable_funcs {
int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
int (*set_default_od8_settings)(struct smu_context *smu);
+ int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type type);
int (*get_clock_by_type_with_latency)(struct smu_context *smu,
enum amd_pp_clock_type type,
struct
@@ -424,6 +425,8 @@ struct smu_funcs
((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
#define smu_force_clk_levels(smu, type, level) \
((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (type), (level)) : 0)
+#define smu_get_od_percentage(smu, type) \
+ ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
#define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_read_sensor(smu, sensor, data, size) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index aa7f41a..42eb828 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1120,6 +1120,42 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu)
return 0;
}
+static int vega20_get_od_percentage(struct smu_context *smu,
+ enum pp_clock_type type)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_dpm_table *golden_table = NULL;
+ struct vega20_single_dpm_table *single_dpm_table;
+ struct vega20_single_dpm_table *golden_dpm_table;
+ int value, golden_value;
+
+ dpm_table = smu_dpm->dpm_context;
+ golden_table = smu_dpm->golden_dpm_context;
+
+ switch (type) {
+ case OD_SCLK:
+ single_dpm_table = &(dpm_table->gfx_table);
+ golden_dpm_table = &(golden_table->gfx_table);
+ break;
+ case OD_MCLK:
+ single_dpm_table = &(dpm_table->mem_table);
+ golden_dpm_table = &(golden_table->mem_table);
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+
+ value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
+ golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
+
+ value -= golden_value;
+ value = DIV_ROUND_UP(value * 100, golden_value);
+
+ return value;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -1134,6 +1170,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.force_clk_levels = vega20_force_clk_levels,
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
.set_default_od8_settings = vega20_set_default_od8_setttings,
+ .get_od_percentage = vega20_get_od_percentage,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 109/138] drm/amd/powerplay: get overdrive clock and voltage information
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (107 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 108/138] drm/amd/powerplay: print overdrive percentage information for smu11 Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 110/138] drm/amd/powerplay: remove unnecessary checking in smu_hw_fini Huang Rui
` (29 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add sys interface to get overdrive clock and voltage information for
smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8 ++-
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 99 ++++++++++++++++++++++++++++++
2 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 90f06ab..a78b9e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -658,7 +658,13 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
uint32_t size = 0;
- if (adev->powerplay.pp_funcs->print_clock_levels) {
+ if (is_support_sw_smu(adev)) {
+ size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
+ size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
+ size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
+ size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
+ return size;
+ } else if (adev->powerplay.pp_funcs->print_clock_levels) {
size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 42eb828..b9f4e7b 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -678,8 +678,13 @@ static int vega20_print_clk_levels(struct smu_context *smu,
int ret = 0;
struct pp_clock_levels_with_latency clocks;
struct vega20_single_dpm_table *single_dpm_table;
+ struct smu_table_context *table_context = &smu->smu_table;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_od8_settings *od8_settings =
+ (struct vega20_od8_settings *)table_context->od8_settings;
+ OverDriveTable_t *od_table =
+ (OverDriveTable_t *)(table_context->overdrive_table);
dpm_table = smu_dpm->dpm_context;
@@ -725,6 +730,100 @@ static int vega20_print_clk_levels(struct smu_context *smu,
(clocks.data[i].clocks_in_khz == now * 10)
? "*" : "");
break;
+
+ case OD_SCLK:
+ if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
+ size = sprintf(buf, "%s:\n", "OD_SCLK");
+ size += sprintf(buf + size, "0: %10uMhz\n",
+ od_table->GfxclkFmin);
+ size += sprintf(buf + size, "1: %10uMhz\n",
+ od_table->GfxclkFmax);
+ }
+
+ break;
+
+ case OD_MCLK:
+ if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
+ size = sprintf(buf, "%s:\n", "OD_MCLK");
+ size += sprintf(buf + size, "1: %10uMhz\n",
+ od_table->UclkFmax);
+ }
+
+ break;
+
+ case OD_VDDC_CURVE:
+ if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
+ size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
+ size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
+ od_table->GfxclkFreq1,
+ od_table->GfxclkVolt1 / VOLTAGE_SCALE);
+ size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
+ od_table->GfxclkFreq2,
+ od_table->GfxclkVolt2 / VOLTAGE_SCALE);
+ size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
+ od_table->GfxclkFreq3,
+ od_table->GfxclkVolt3 / VOLTAGE_SCALE);
+ }
+
+ break;
+
+ case OD_RANGE:
+ size = sprintf(buf, "%s:\n", "OD_RANGE");
+
+ if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
+ size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
+ }
+
+ if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
+ single_dpm_table = &(dpm_table->mem_table);
+ ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
+ if (ret) {
+ pr_err("Attempt to get memory clk levels Failed!");
+ return ret;
+ }
+
+ size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
+ clocks.data[0].clocks_in_khz / 1000,
+ od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
+ }
+
+ if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
+ size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
+ size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
+ size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
+ size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
+ size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
+ size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
+ }
+
+ break;
+
default:
break;
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 110/138] drm/amd/powerplay: remove unnecessary checking in smu_hw_fini
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (108 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 109/138] drm/amd/powerplay: get overdrive clock and voltage information Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 111/138] drm/amd/powerplay: don't check hwmgr while using the sw smu Huang Rui
` (28 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
This patch removes unnecessary NULL pointer checking in smu_hw_fini, because
kfree is able to handle NULL pointer case.
Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 54 ++++++++++--------------------
1 file changed, 18 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 2e3e084..eed6cb9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -677,50 +677,32 @@ static int smu_hw_fini(void *handle)
if (!is_support_sw_smu(adev))
return -EINVAL;
- if (smu_dpm->dpm_context) {
- kfree(smu_dpm->dpm_context);
- smu_dpm->dpm_context = NULL;
- }
+ kfree(smu_dpm->dpm_context);
+ smu_dpm->dpm_context = NULL;
- if (smu_dpm->golden_dpm_context) {
- kfree(smu_dpm->golden_dpm_context);
- smu_dpm->golden_dpm_context = NULL;
- }
+ kfree(smu_dpm->golden_dpm_context);
+ smu_dpm->golden_dpm_context = NULL;
- if (table_context->driver_pptable) {
- kfree(table_context->driver_pptable);
- table_context->driver_pptable = NULL;
- }
+ kfree(table_context->driver_pptable);
+ table_context->driver_pptable = NULL;
- if (table_context->max_sustainable_clocks) {
- kfree(table_context->max_sustainable_clocks);
- table_context->max_sustainable_clocks = NULL;
- }
+ kfree(table_context->max_sustainable_clocks);
+ table_context->max_sustainable_clocks = NULL;
- if (table_context->od_feature_capabilities) {
- kfree(table_context->od_feature_capabilities);
- table_context->od_feature_capabilities = NULL;
- }
+ kfree(table_context->od_feature_capabilities);
+ table_context->od_feature_capabilities = NULL;
- if (table_context->od_settings_max) {
- kfree(table_context->od_settings_max);
- table_context->od_settings_max = NULL;
- }
+ kfree(table_context->od_settings_max);
+ table_context->od_settings_max = NULL;
- if (table_context->od_settings_min) {
- kfree(table_context->od_settings_min);
- table_context->od_settings_min = NULL;
- }
+ kfree(table_context->od_settings_min);
+ table_context->od_settings_min = NULL;
- if (table_context->overdrive_table) {
- kfree(table_context->overdrive_table);
- table_context->overdrive_table = NULL;
- }
+ kfree(table_context->overdrive_table);
+ table_context->overdrive_table = NULL;
- if (table_context->od8_settings) {
- kfree(table_context->od8_settings);
- table_context->od8_settings = NULL;
- }
+ kfree(table_context->od8_settings);
+ table_context->od8_settings = NULL;
ret = smu_fini_fb_allocations(smu);
if (ret)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 111/138] drm/amd/powerplay: don't check hwmgr while using the sw smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (109 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 110/138] drm/amd/powerplay: remove unnecessary checking in smu_hw_fini Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 112/138] drm/amd/powerplay: implement power_dpm_state sys interface for SMU11 Huang Rui
` (27 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Huang Rui, Chengming Gui
While using the sw smu path, driver won't init hwmgr structure.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a78b9e6..c4c2383 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2443,7 +2443,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_power_profile_mode\n");
return ret;
}
- if (hwmgr->od_enabled) {
+ if (is_support_sw_smu(adev) || hwmgr->od_enabled) {
ret = device_create_file(adev->dev,
&dev_attr_pp_od_clk_voltage);
if (ret) {
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 112/138] drm/amd/powerplay: implement power_dpm_state sys interface for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (110 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 111/138] drm/amd/powerplay: don't check hwmgr while using the sw smu Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 113/138] drm/amd/powerplay: add watermarks related data structs and function " Huang Rui
` (26 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
Add functions to get/set dpm state for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Kevin Wang <kevin.wang@amd.com>
Reviewd-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 4 +-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 116 +++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 46 ++++++++++
5 files changed, 175 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index c874e30..2e0dd4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -290,6 +290,12 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_get_current_power_state(adev) \
((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
+#define amdgpu_smu_get_current_power_state(adev) \
+ ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
+
+#define amdgpu_smu_set_power_state(adev) \
+ ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
+
#define amdgpu_dpm_get_pp_num_states(adev, data) \
((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c4c2383..d748256 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -144,7 +144,9 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
enum amd_pm_state_type pm;
- if (adev->powerplay.pp_funcs->get_current_power_state)
+ if (adev->smu.ppt_funcs->get_current_power_state)
+ pm = amdgpu_smu_get_current_power_state(adev);
+ else if (adev->powerplay.pp_funcs->get_current_power_state)
pm = amdgpu_dpm_get_current_power_state(adev);
else
pm = adev->pm.dpm.user_state;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 71b2703..0b04bb2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -26,6 +26,118 @@
#include "kgd_pp_interface.h"
#include "dm_pp_interface.h"
+struct smu_hw_power_state {
+ unsigned int magic;
+};
+
+struct smu_power_state;
+
+enum smu_state_ui_label {
+ SMU_STATE_UI_LABEL_NONE,
+ SMU_STATE_UI_LABEL_BATTERY,
+ SMU_STATE_UI_TABEL_MIDDLE_LOW,
+ SMU_STATE_UI_LABEL_BALLANCED,
+ SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
+ SMU_STATE_UI_LABEL_PERFORMANCE,
+ SMU_STATE_UI_LABEL_BACO,
+};
+
+enum smu_state_classification_flag {
+ SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
+ SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
+ SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
+ SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
+ SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
+ SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
+ SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
+ SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
+ SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
+ SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
+ SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
+ SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
+ SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
+ SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
+ SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
+ SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
+ SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
+ SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
+ SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
+ SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
+ SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
+};
+
+struct smu_state_classification_block {
+ enum smu_state_ui_label ui_label;
+ enum smu_state_classification_flag flags;
+ int bios_index;
+ bool temporary_state;
+ bool to_be_deleted;
+};
+
+struct smu_state_pcie_block {
+ unsigned int lanes;
+};
+
+enum smu_refreshrate_source {
+ SMU_REFRESHRATE_SOURCE_EDID,
+ SMU_REFRESHRATE_SOURCE_EXPLICIT
+};
+
+struct smu_state_display_block {
+ bool disable_frame_modulation;
+ bool limit_refreshrate;
+ enum smu_refreshrate_source refreshrate_source;
+ int explicit_refreshrate;
+ int edid_refreshrate_index;
+ bool enable_vari_bright;
+};
+
+struct smu_state_memroy_block {
+ bool dll_off;
+ uint8_t m3arb;
+ uint8_t unused[3];
+};
+
+struct smu_state_software_algorithm_block {
+ bool disable_load_balancing;
+ bool enable_sleep_for_timestamps;
+};
+
+struct smu_temperature_range {
+ int min;
+ int max;
+};
+
+struct smu_state_validation_block {
+ bool single_display_only;
+ bool disallow_on_dc;
+ uint8_t supported_power_levels;
+};
+
+struct smu_uvd_clocks {
+ uint32_t vclk;
+ uint32_t dclk;
+};
+
+/**
+* Structure to hold a SMU Power State.
+*/
+struct smu_power_state {
+ uint32_t id;
+ struct list_head ordered_list;
+ struct list_head all_states_list;
+
+ struct smu_state_classification_block classification;
+ struct smu_state_validation_block validation;
+ struct smu_state_pcie_block pcie;
+ struct smu_state_display_block display;
+ struct smu_state_memroy_block memory;
+ struct smu_temperature_range temperatures;
+ struct smu_state_software_algorithm_block software;
+ struct smu_uvd_clocks uvd_clocks;
+ struct smu_hw_power_state hardware;
+};
+
enum smu_message_type
{
SMU_MSG_TestMessage = 0,
@@ -204,6 +316,8 @@ struct smu_dpm_context {
uint32_t dpm_context_size;
void *dpm_context;
void *golden_dpm_context;
+ struct smu_power_state *dpm_request_power_state;
+ struct smu_power_state *dpm_current_power_state;
};
struct smu_power_context {
@@ -257,7 +371,9 @@ struct pptable_funcs {
int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
int (*run_afll_btc)(struct smu_context *smu);
int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+ enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
int (*set_default_dpm_table)(struct smu_context *smu);
+ int (*set_power_state)(struct smu_context *smu);
int (*populate_umd_state_clk)(struct smu_context *smu);
int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3c4c327e..542292f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -272,8 +272,12 @@ static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
return -EINVAL;
kfree(smu_dpm->dpm_context);
+ kfree(smu_dpm->dpm_current_power_state);
+ kfree(smu_dpm->dpm_request_power_state);
smu_dpm->dpm_context = NULL;
smu_dpm->dpm_context_size = 0;
+ smu_dpm->dpm_current_power_state = NULL;
+ smu_dpm->dpm_request_power_state = NULL;
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index b9f4e7b..04ff561 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -31,6 +31,7 @@
#include "smu11_driver_if.h"
#include "soc15_common.h"
#include "atom.h"
+#include "power_state.h"
#include "vega20_ppt.h"
#include "vega20_pptable.h"
#include "vega20_ppsmc.h"
@@ -154,6 +155,16 @@ static int vega20_allocate_dpm_context(struct smu_context *smu)
smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
+ smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
+ GFP_KERNEL);
+ if (!smu_dpm->dpm_current_power_state)
+ return -ENOMEM;
+
+ smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
+ GFP_KERNEL);
+ if (!smu_dpm->dpm_request_power_state)
+ return -ENOMEM;
+
return 0;
}
@@ -389,6 +400,39 @@ vega20_get_unallowed_feature_mask(struct smu_context *smu,
return 0;
}
+static enum
+amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
+{
+ enum amd_pm_state_type pm_type;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+
+ if (!smu_dpm_ctx->dpm_context ||
+ !smu_dpm_ctx->dpm_current_power_state)
+ return -EINVAL;
+
+ mutex_lock(&(smu->mutex));
+ switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
+ case SMU_STATE_UI_LABEL_BATTERY:
+ pm_type = POWER_STATE_TYPE_BATTERY;
+ break;
+ case SMU_STATE_UI_LABEL_BALLANCED:
+ pm_type = POWER_STATE_TYPE_BALANCED;
+ break;
+ case SMU_STATE_UI_LABEL_PERFORMANCE:
+ pm_type = POWER_STATE_TYPE_PERFORMANCE;
+ break;
+ default:
+ if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
+ pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
+ else
+ pm_type = POWER_STATE_TYPE_DEFAULT;
+ break;
+ }
+ mutex_unlock(&(smu->mutex));
+
+ return pm_type;
+}
+
static int
vega20_set_single_dpm_table(struct smu_context *smu,
struct vega20_single_dpm_table *single_dpm_table,
@@ -1263,7 +1307,9 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_smu_msg_index = vega20_get_smu_msg_index,
.run_afll_btc = vega20_run_btc_afll,
.get_unallowed_feature_mask = vega20_get_unallowed_feature_mask,
+ .get_current_power_state = vega20_get_current_power_state,
.set_default_dpm_table = vega20_set_default_dpm_table,
+ .set_power_state = NULL,
.populate_umd_state_clk = vega20_populate_umd_state_clk,
.print_clk_levels = vega20_print_clk_levels,
.force_clk_levels = vega20_force_clk_levels,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 113/138] drm/amd/powerplay: add watermarks related data structs and function for SMU11.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (111 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 112/138] drm/amd/powerplay: implement power_dpm_state sys interface for SMU11 Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 114/138] drm/amd/powerplay: implement pp_power_profile_mode sys inerface " Huang Rui
` (25 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add write watermark table function and watermark flags
to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 542292f..403b0f4 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -556,6 +556,12 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
+{
+ return smu_update_table(smu, TABLE_WATERMARKS,
+ smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr, true);
+}
+
static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
{
int ret;
@@ -1250,6 +1256,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.parse_pptable = smu_v11_0_parse_pptable,
.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
.write_pptable = smu_v11_0_write_pptable,
+ .write_watermarks_table = smu_v11_0_write_watermarks_table,
.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
.init_display = smu_v11_0_init_display,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 114/138] drm/amd/powerplay: implement pp_power_profile_mode sys inerface for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (112 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 113/138] drm/amd/powerplay: add watermarks related data structs and function " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 115/138] drm/amd/powerplay: add display_config to handle display config " Huang Rui
` (24 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
Add set/get power profile mode functions.
Added dependency interfaces:
1) vega20_set_activity_monitor_coeff
2) vega20_get_activity_monitor_coeff
3) conv_power_profile_to_pplib_workload
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 ++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 22 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 293 +++++++++++++++++++++++++
4 files changed, 340 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d748256..7015e03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1136,7 +1136,9 @@ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->powerplay.pp_funcs->get_power_profile_mode)
+ if (is_support_sw_smu(adev))
+ return smu_get_power_profile_mode(&adev->smu, buf);
+ else if (adev->powerplay.pp_funcs->get_power_profile_mode)
return amdgpu_dpm_get_power_profile_mode(adev, buf);
return snprintf(buf, PAGE_SIZE, "\n");
@@ -1186,9 +1188,10 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
}
}
parameter[parameter_size] = profile_mode;
- if (adev->powerplay.pp_funcs->set_power_profile_mode)
+ if (is_support_sw_smu(adev))
+ ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
+ else if (adev->powerplay.pp_funcs->set_power_profile_mode)
ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
-
if (!ret)
return count;
fail:
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index eed6cb9..14788d4 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -323,6 +323,25 @@ static int smu_sw_init(void *handle)
bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
smu->watermarks_bitmap = 0;
+ smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+ smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+
+ smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
+ smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
+ smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
+ smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
+ smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
+ smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
+ smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
+ smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
+
+ smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+ smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+ smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
+ smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
+ smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
+ smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
+ smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
ret = smu_init_microcode(smu);
if (ret) {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 0b04bb2..191bfc2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -335,6 +335,7 @@ struct smu_feature
DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
};
+#define WORKLOAD_POLICY_MAX 7
struct smu_context
{
struct amdgpu_device *adev;
@@ -361,6 +362,12 @@ struct smu_context
#define WATERMARKS_EXIST (1 << 0)
#define WATERMARKS_LOADED (1 << 1)
uint32_t watermarks_bitmap;
+
+ uint32_t workload_mask;
+ uint32_t workload_prority[WORKLOAD_POLICY_MAX];
+ uint32_t workload_setting[WORKLOAD_POLICY_MAX];
+ uint32_t power_profile_mode;
+ uint32_t default_power_profile_mode;
};
struct pptable_funcs {
@@ -389,6 +396,8 @@ struct pptable_funcs {
struct
pp_clock_levels_with_voltage
*clocks);
+ int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
+ int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
};
struct smu_funcs
@@ -453,6 +462,15 @@ struct smu_funcs
int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
int (*set_od8_default_settings)(struct smu_context *smu);
+ int (*get_activity_monitor_coeff)(struct smu_context *smu,
+ uint8_t *table,
+ uint16_t workload_type);
+ int (*set_activity_monitor_coeff)(struct smu_context *smu,
+ uint8_t *table,
+ uint16_t workload_type);
+ int (*conv_power_profile_to_pplib_workload)(int power_profile);
+ int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
+ int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
};
#define smu_init_microcode(smu) \
@@ -547,6 +565,10 @@ struct smu_funcs
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_read_sensor(smu, sensor, data, size) \
((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+#define smu_get_power_profile_mode(smu, buf) \
+ ((smu)->funcs->get_power_profile_mode ? (smu)->funcs->get_power_profile_mode((smu), buf) : 0)
+#define smu_set_power_profile_mode(smu, param, param_size) \
+ ((smu)->funcs->set_power_profile_mode ? (smu)->funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 403b0f4..6cabc87 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -308,6 +308,10 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, TABLE_ACTIVITY_MONITOR_COEFF,
+ sizeof(DpmActivityMonitorCoeffInt_t),
+ PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM);
ret = smu_v11_0_init_dpm_context(smu);
if (ret)
@@ -1236,6 +1240,290 @@ static int smu_v11_0_set_od8_default_settings(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_set_activity_monitor_coeff(struct smu_context *smu,
+ uint8_t *table, uint16_t workload_type)
+{
+ int ret = 0;
+ memcpy(smu->smu_table.tables[TABLE_ACTIVITY_MONITOR_COEFF].cpu_addr,
+ table, smu->smu_table.tables[TABLE_ACTIVITY_MONITOR_COEFF].size);
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
+ upper_32_bits(smu->smu_table.tables[TABLE_ACTIVITY_MONITOR_COEFF].mc_address));
+ if (ret) {
+ pr_err("[%s] Attempt to Set Dram Addr High Failed!", __func__);
+ return ret;
+ }
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
+ lower_32_bits(smu->smu_table.tables[TABLE_ACTIVITY_MONITOR_COEFF].mc_address));
+ if (ret) {
+ pr_err("[%s] Attempt to Set Dram Addr Low Failed!", __func__);
+ return ret;
+ }
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_TransferTableSmu2Dram,
+ TABLE_ACTIVITY_MONITOR_COEFF | (workload_type << 16));
+ if (ret) {
+ pr_err("[%s] Attempt to Transfer Table From SMU Failed!", __func__);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int smu_v11_0_get_activity_monitor_coeff(struct smu_context *smu,
+ uint8_t *table, uint16_t workload_type)
+{
+ int ret = 0;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrHigh,
+ upper_32_bits(smu->smu_table.tables[TABLE_ACTIVITY_MONITOR_COEFF].mc_address));
+ if (ret) {
+ pr_err("[%s] Attempt to Set Dram Addr High Failed!", __func__);
+ return ret;
+ }
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetDriverDramAddrLow,
+ lower_32_bits(smu->smu_table.tables[TABLE_ACTIVITY_MONITOR_COEFF].mc_address));
+ if (ret) {
+ pr_err("[%s] Attempt to Set Dram Addr Low Failed!", __func__);
+ return ret;
+ }
+
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_TransferTableSmu2Dram,
+ TABLE_ACTIVITY_MONITOR_COEFF | (workload_type << 16));
+ if (ret) {
+ pr_err("[%s] Attempt to Transfer Table From SMU Failed!", __func__);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int smu_v11_0_conv_power_profile_to_pplib_workload(int power_profile)
+{
+ int pplib_workload = 0;
+
+ switch (power_profile) {
+ case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
+ pplib_workload = WORKLOAD_DEFAULT_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
+ pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_POWERSAVING:
+ pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_VIDEO:
+ pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_VR:
+ pplib_workload = WORKLOAD_PPLIB_VR_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_COMPUTE:
+ pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
+ break;
+ case PP_SMC_POWER_PROFILE_CUSTOM:
+ pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
+ break;
+ }
+
+ return pplib_workload;
+}
+
+static int smu_v11_0_get_power_profile_mode(struct smu_context *smu, char *buf)
+{
+ DpmActivityMonitorCoeffInt_t activity_monitor;
+ uint32_t i, size = 0;
+ uint16_t workload_type = 0;
+ static const char *profile_name[] = {
+ "BOOTUP_DEFAULT",
+ "3D_FULL_SCREEN",
+ "POWER_SAVING",
+ "VIDEO",
+ "VR",
+ "COMPUTE",
+ "CUSTOM"};
+ static const char *title[] = {
+ "PROFILE_INDEX(NAME)",
+ "CLOCK_TYPE(NAME)",
+ "FPS",
+ "UseRlcBusy",
+ "MinActiveFreqType",
+ "MinActiveFreq",
+ "BoosterFreqType",
+ "BoosterFreq",
+ "PD_Data_limit_c",
+ "PD_Data_error_coeff",
+ "PD_Data_error_rate_coeff"};
+ int result = 0;
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
+ title[0], title[1], title[2], title[3], title[4], title[5],
+ title[6], title[7], title[8], title[9], title[10]);
+
+ for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type = smu_v11_0_conv_power_profile_to_pplib_workload(i);
+ result = smu_v11_0_get_activity_monitor_coeff(smu,
+ (uint8_t *)(&activity_monitor),
+ workload_type);
+ if (result) {
+ pr_err("[%s] Failed to get activity monitor!", __func__);
+ return result;
+ }
+
+ size += sprintf(buf + size, "%2d %14s%s:\n",
+ i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 0,
+ "GFXCLK",
+ activity_monitor.Gfx_FPS,
+ activity_monitor.Gfx_UseRlcBusy,
+ activity_monitor.Gfx_MinActiveFreqType,
+ activity_monitor.Gfx_MinActiveFreq,
+ activity_monitor.Gfx_BoosterFreqType,
+ activity_monitor.Gfx_BoosterFreq,
+ activity_monitor.Gfx_PD_Data_limit_c,
+ activity_monitor.Gfx_PD_Data_error_coeff,
+ activity_monitor.Gfx_PD_Data_error_rate_coeff);
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 1,
+ "SOCCLK",
+ activity_monitor.Soc_FPS,
+ activity_monitor.Soc_UseRlcBusy,
+ activity_monitor.Soc_MinActiveFreqType,
+ activity_monitor.Soc_MinActiveFreq,
+ activity_monitor.Soc_BoosterFreqType,
+ activity_monitor.Soc_BoosterFreq,
+ activity_monitor.Soc_PD_Data_limit_c,
+ activity_monitor.Soc_PD_Data_error_coeff,
+ activity_monitor.Soc_PD_Data_error_rate_coeff);
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 2,
+ "UCLK",
+ activity_monitor.Mem_FPS,
+ activity_monitor.Mem_UseRlcBusy,
+ activity_monitor.Mem_MinActiveFreqType,
+ activity_monitor.Mem_MinActiveFreq,
+ activity_monitor.Mem_BoosterFreqType,
+ activity_monitor.Mem_BoosterFreq,
+ activity_monitor.Mem_PD_Data_limit_c,
+ activity_monitor.Mem_PD_Data_error_coeff,
+ activity_monitor.Mem_PD_Data_error_rate_coeff);
+
+ size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 3,
+ "FCLK",
+ activity_monitor.Fclk_FPS,
+ activity_monitor.Fclk_UseRlcBusy,
+ activity_monitor.Fclk_MinActiveFreqType,
+ activity_monitor.Fclk_MinActiveFreq,
+ activity_monitor.Fclk_BoosterFreqType,
+ activity_monitor.Fclk_BoosterFreq,
+ activity_monitor.Fclk_PD_Data_limit_c,
+ activity_monitor.Fclk_PD_Data_error_coeff,
+ activity_monitor.Fclk_PD_Data_error_rate_coeff);
+ }
+
+ return size;
+}
+
+static int smu_v11_0_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
+{
+ DpmActivityMonitorCoeffInt_t activity_monitor;
+ int workload_type, ret = 0;
+
+ smu->power_profile_mode = input[size];
+
+ if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+ pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
+ return -EINVAL;
+ }
+
+ if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+ if (size < 0)
+ return -EINVAL;
+
+ ret = smu_v11_0_get_activity_monitor_coeff(smu,
+ (uint8_t *)(&activity_monitor),
+ WORKLOAD_PPLIB_CUSTOM_BIT);
+ if (ret) {
+ pr_err("[%s] Failed to get activity monitor!", __func__);
+ return ret;
+ }
+
+ switch (input[0]) {
+ case 0: /* Gfxclk */
+ activity_monitor.Gfx_FPS = input[1];
+ activity_monitor.Gfx_UseRlcBusy = input[2];
+ activity_monitor.Gfx_MinActiveFreqType = input[3];
+ activity_monitor.Gfx_MinActiveFreq = input[4];
+ activity_monitor.Gfx_BoosterFreqType = input[5];
+ activity_monitor.Gfx_BoosterFreq = input[6];
+ activity_monitor.Gfx_PD_Data_limit_c = input[7];
+ activity_monitor.Gfx_PD_Data_error_coeff = input[8];
+ activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
+ break;
+ case 1: /* Socclk */
+ activity_monitor.Soc_FPS = input[1];
+ activity_monitor.Soc_UseRlcBusy = input[2];
+ activity_monitor.Soc_MinActiveFreqType = input[3];
+ activity_monitor.Soc_MinActiveFreq = input[4];
+ activity_monitor.Soc_BoosterFreqType = input[5];
+ activity_monitor.Soc_BoosterFreq = input[6];
+ activity_monitor.Soc_PD_Data_limit_c = input[7];
+ activity_monitor.Soc_PD_Data_error_coeff = input[8];
+ activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
+ break;
+ case 2: /* Uclk */
+ activity_monitor.Mem_FPS = input[1];
+ activity_monitor.Mem_UseRlcBusy = input[2];
+ activity_monitor.Mem_MinActiveFreqType = input[3];
+ activity_monitor.Mem_MinActiveFreq = input[4];
+ activity_monitor.Mem_BoosterFreqType = input[5];
+ activity_monitor.Mem_BoosterFreq = input[6];
+ activity_monitor.Mem_PD_Data_limit_c = input[7];
+ activity_monitor.Mem_PD_Data_error_coeff = input[8];
+ activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
+ break;
+ case 3: /* Fclk */
+ activity_monitor.Fclk_FPS = input[1];
+ activity_monitor.Fclk_UseRlcBusy = input[2];
+ activity_monitor.Fclk_MinActiveFreqType = input[3];
+ activity_monitor.Fclk_MinActiveFreq = input[4];
+ activity_monitor.Fclk_BoosterFreqType = input[5];
+ activity_monitor.Fclk_BoosterFreq = input[6];
+ activity_monitor.Fclk_PD_Data_limit_c = input[7];
+ activity_monitor.Fclk_PD_Data_error_coeff = input[8];
+ activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
+ break;
+ }
+
+ ret = smu_v11_0_set_activity_monitor_coeff(smu,
+ (uint8_t *)(&activity_monitor),
+ WORKLOAD_PPLIB_CUSTOM_BIT);
+ if (ret) {
+ pr_err("[%s] Failed to set activity monitor!", __func__);
+ return ret;
+ }
+ }
+
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type =
+ smu_v11_0_conv_power_profile_to_pplib_workload(smu->power_profile_mode);
+ smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
+ 1 << workload_type);
+
+ return ret;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1274,6 +1562,11 @@ static const struct smu_funcs smu_v11_0_funcs = {
.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
.set_od8_default_settings = smu_v11_0_set_od8_default_settings,
+ .get_activity_monitor_coeff = smu_v11_0_get_activity_monitor_coeff,
+ .set_activity_monitor_coeff = smu_v11_0_set_activity_monitor_coeff,
+ .conv_power_profile_to_pplib_workload = smu_v11_0_conv_power_profile_to_pplib_workload,
+ .get_power_profile_mode = smu_v11_0_get_power_profile_mode,
+ .set_power_profile_mode = smu_v11_0_set_power_profile_mode,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 115/138] drm/amd/powerplay: add display_config to handle display config for SMU11.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (113 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 114/138] drm/amd/powerplay: implement pp_power_profile_mode sys inerface " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 116/138] drm/amd/powerplay: add mclk_latency_table struct and smu_clocks struct " Huang Rui
` (23 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add display_config to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 -
3 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 14788d4..04be1e0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -342,6 +342,7 @@ static int smu_sw_init(void *handle)
smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
+ smu->display_config = &adev->pm.pm_display_cfg;
ret = smu_init_microcode(smu);
if (ret) {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 191bfc2..116c365 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -349,6 +349,7 @@ struct smu_context
struct smu_dpm_context smu_dpm;
struct smu_power_context smu_power;
struct smu_feature smu_feature;
+ struct amd_pp_display_configuration *display_config;
uint32_t pstate_sclk;
uint32_t pstate_mclk;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 6cabc87..f11df04 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -336,7 +336,6 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
if (ret)
return ret;
return 0;
-
}
static int smu_v11_0_init_power(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 116/138] drm/amd/powerplay: add mclk_latency_table struct and smu_clocks struct for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (114 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 115/138] drm/amd/powerplay: add display_config to handle display config " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 117/138] drm/amd/powerplay: add enable_umd_pstate functions " Huang Rui
` (22 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add mclk_latency_table struct and smu_clocks structi
to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 116c365..c022cdf 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -318,6 +318,7 @@ struct smu_dpm_context {
void *golden_dpm_context;
struct smu_power_state *dpm_request_power_state;
struct smu_power_state *dpm_current_power_state;
+ struct mclock_latency_table *mclk_latency_table;
};
struct smu_power_context {
@@ -335,6 +336,25 @@ struct smu_feature
DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
};
+struct smu_clocks {
+ uint32_t engine_clock;
+ uint32_t memory_clock;
+ uint32_t bus_bandwidth;
+ uint32_t engine_clock_in_sr;
+ uint32_t dcef_clock;
+ uint32_t dcef_clock_in_sr;
+};
+
+#define MAX_REGULAR_DPM_NUM 16
+struct mclk_latency_entries {
+ uint32_t frequency;
+ uint32_t latency;
+};
+struct mclock_latency_table {
+ uint32_t count;
+ struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
+};
+
#define WORKLOAD_POLICY_MAX 7
struct smu_context
{
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 117/138] drm/amd/powerplay: add enable_umd_pstate functions for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (115 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 116/138] drm/amd/powerplay: add mclk_latency_table struct and smu_clocks struct " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 118/138] drm/amd/powerplay: add get_profiling_clk_mask " Huang Rui
` (21 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add enable_umd_pstate to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/include/amd_shared.h | 3 ++
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 44 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +++
3 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 470d7b8..574bf6e 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -137,6 +137,7 @@ enum DC_FEATURE_MASK {
DC_FBC_MASK = 0x1,
};
+enum amd_dpm_forced_level;
/**
* struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
*/
@@ -186,6 +187,8 @@ struct amd_ip_funcs {
enum amd_powergating_state state);
/** @get_clockgating_state: get current clockgating status */
void (*get_clockgating_state)(void *handle, u32 *flags);
+ /** @enable_umd_pstate: enable UMD powerstate */
+ int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
};
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 04be1e0..2fe3b57 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -940,6 +940,49 @@ static int smu_set_powergating_state(void *handle,
return 0;
}
+static int smu_enable_umd_pstate(void *handle,
+ enum amd_dpm_forced_level *level)
+{
+ uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
+ AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
+ AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
+
+ struct smu_context *smu = (struct smu_context*)(handle);
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ if (!smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
+ if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
+ /* enter umd pstate, save current level, disable gfx cg*/
+ if (*level & profile_mode_mask) {
+ smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
+ smu_dpm_ctx->enable_umd_pstate = true;
+ amdgpu_device_ip_set_clockgating_state(smu->adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(smu->adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_PG_STATE_UNGATE);
+ }
+ } else {
+ /* exit umd pstate, restore level, enable gfx cg*/
+ if (!(*level & profile_mode_mask)) {
+ if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
+ *level = smu_dpm_ctx->saved_dpm_level;
+ smu_dpm_ctx->enable_umd_pstate = false;
+ amdgpu_device_ip_set_clockgating_state(smu->adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(smu->adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_PG_STATE_GATE);
+ }
+ }
+
+ return 0;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
@@ -956,6 +999,7 @@ const struct amd_ip_funcs smu_ip_funcs = {
.soft_reset = NULL,
.set_clockgating_state = smu_set_clockgating_state,
.set_powergating_state = smu_set_powergating_state,
+ .enable_umd_pstate = smu_enable_umd_pstate,
};
const struct amdgpu_ip_block_version smu_v11_0_ip_block =
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c022cdf..bcd7479 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -316,6 +316,10 @@ struct smu_dpm_context {
uint32_t dpm_context_size;
void *dpm_context;
void *golden_dpm_context;
+ bool enable_umd_pstate;
+ enum amd_dpm_forced_level dpm_level;
+ enum amd_dpm_forced_level saved_dpm_level;
+ enum amd_dpm_forced_level requested_dpm_level;
struct smu_power_state *dpm_request_power_state;
struct smu_power_state *dpm_current_power_state;
struct mclock_latency_table *mclk_latency_table;
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 118/138] drm/amd/powerplay: add get_profiling_clk_mask functions for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (116 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 117/138] drm/amd/powerplay: add enable_umd_pstate functions " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 119/138] drm/amd/powerplay: add set_uclk_to_highest_level " Huang Rui
` (20 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add get_profiling_clk_masking_clk_mask
to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 40 ++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 3 +++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 04ff561..62ca0ef 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1299,6 +1299,46 @@ static int vega20_get_od_percentage(struct smu_context *smu,
return value;
}
+static int
+vega20_get_profiling_clk_mask(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ uint32_t *sclk_mask,
+ uint32_t *mclk_mask,
+ uint32_t *soc_mask)
+{
+ struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
+ if (!smu->smu_dpm.dpm_context)
+ return -EINVAL;
+
+ struct vega20_single_dpm_table *gfx_dpm_table = &(dpm_table->gfx_table);
+ struct vega20_single_dpm_table *mem_dpm_table = &(dpm_table->mem_table);
+ struct vega20_single_dpm_table *soc_dpm_table = &(dpm_table->soc_table);
+
+ *sclk_mask = 0;
+ *mclk_mask = 0;
+ *soc_mask = 0;
+
+ if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
+ mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
+ soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
+ *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
+ *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
+ *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
+ }
+
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+ *sclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+ *mclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ *sclk_mask = gfx_dpm_table->count - 1;
+ *mclk_mask = mem_dpm_table->count - 1;
+ *soc_mask = soc_dpm_table->count - 1;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
index 9b229b2..5a0d2af 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.h
@@ -24,7 +24,10 @@
#define __VEGA20_PPT_H__
#define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3
+#define VEGA20_UMD_PSTATE_SOCCLK_LEVEL 0x3
#define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2
+#define VEGA20_UMD_PSTATE_UVDCLK_LEVEL 0x3
+#define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL 0x3
#define MAX_REGULAR_DPM_NUMBER 16
#define MAX_PCIE_CONF 2
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 119/138] drm/amd/powerplay: add set_uclk_to_highest_level for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (117 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 118/138] drm/amd/powerplay: add get_profiling_clk_mask " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 120/138] drm/amd/powerplay: add display_config_changed " Huang Rui
` (19 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add set_uclk_to_highest_level to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 43 +++++++++++++++++++++++++++---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 62ca0ef..1908b91 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1307,12 +1307,16 @@ vega20_get_profiling_clk_mask(struct smu_context *smu,
uint32_t *soc_mask)
{
struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
+ struct vega20_single_dpm_table *gfx_dpm_table;
+ struct vega20_single_dpm_table *mem_dpm_table;
+ struct vega20_single_dpm_table *soc_dpm_table;
+
if (!smu->smu_dpm.dpm_context)
return -EINVAL;
- struct vega20_single_dpm_table *gfx_dpm_table = &(dpm_table->gfx_table);
- struct vega20_single_dpm_table *mem_dpm_table = &(dpm_table->mem_table);
- struct vega20_single_dpm_table *soc_dpm_table = &(dpm_table->soc_table);
+ gfx_dpm_table = &dpm_table->gfx_table;
+ mem_dpm_table = &dpm_table->mem_table;
+ soc_dpm_table = &dpm_table->soc_table;
*sclk_mask = 0;
*mclk_mask = 0;
@@ -1339,6 +1343,39 @@ vega20_get_profiling_clk_mask(struct smu_context *smu,
return 0;
}
+static int
+vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
+ struct vega20_single_dpm_table *dpm_table)
+{
+ int ret = 0;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ if (!smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ if (dpm_table->count <= 0) {
+ pr_err("[%s] Dpm table has no entry!", __func__);
+ return -EINVAL;
+ }
+
+ if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
+ pr_err("[%s] Dpm table has too many entries!", __func__);
+ return -EINVAL;
+ }
+
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetHardMinByFreq,
+ (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
+ if (ret) {
+ pr_err("[%s] Set hard min uclk failed!", __func__);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 120/138] drm/amd/powerplay: add display_config_changed for SMU11.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (118 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 119/138] drm/amd/powerplay: add set_uclk_to_highest_level " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 121/138] drm/amd/powerplay: add apply_clock_adjust_rules " Huang Rui
` (18 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add display_config_changed to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 42 ++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 1908b91..0b13c93 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1376,6 +1376,48 @@ vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
return ret;
}
+static int vega20_display_config_changed(struct smu_context *smu)
+{
+ int ret = 0;
+ struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
+
+ if (!smu->funcs)
+ return -EINVAL;
+
+ if (!smu->smu_dpm.dpm_context ||
+ !smu->smu_table.tables ||
+ !smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr)
+ return -EINVAL;
+
+ smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
+ ret = vega20_set_uclk_to_highest_dpm_level(smu,
+ &dpm_table->mem_table);
+ if (ret) {
+ pr_err("Failed to set uclk to highest dpm level");
+ return ret;
+ }
+
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu->funcs->write_watermarks_table(smu);
+ if (ret) {
+ pr_err("Failed to update WMTABLE!");
+ return ret;
+ }
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
+
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ smu_feature_is_supported(smu, FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_supported(smu, FEATURE_DPM_SOCCLK_BIT)) {
+ smu_send_smc_msg_with_param(smu,
+ SMU_MSG_NumOfDisplays,
+ smu->display_config->num_display);
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 121/138] drm/amd/powerplay: add apply_clock_adjust_rules for SMU11.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (119 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 120/138] drm/amd/powerplay: add display_config_changed " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 122/138] drm/amd/powerplay: add vega20_notify_smc_display_config functions " Huang Rui
` (17 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add apply_clock_adjust_rules to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 151 +++++++++++++++++++++++++++++
1 file changed, 151 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 0b13c93..7f351c8 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1418,6 +1418,157 @@ static int vega20_display_config_changed(struct smu_context *smu)
return ret;
}
+static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
+ struct vega20_single_dpm_table *dpm_table;
+ bool vblank_too_short = false;
+ bool disable_mclk_switching;
+ uint32_t i, latency;
+
+ disable_mclk_switching = ((1 < smu->display_config->num_display) &&
+ !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
+ latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
+
+ /* gfxclk */
+ dpm_table = &(dpm_ctx->gfx_table);
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+ if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ }
+
+ /* memclk */
+ dpm_table = &(dpm_ctx->mem_table);
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+ if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ }
+
+ /* honour DAL's UCLK Hardmin */
+ if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
+ dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
+
+ /* Hardmin is dependent on displayconfig */
+ if (disable_mclk_switching) {
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
+ if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
+ if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
+ break;
+ }
+ }
+ }
+ }
+
+ if (smu->display_config->nb_pstate_switch_disable)
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+#if 0
+ /* vclk */
+ dpm_table = &(dpm_ctx->vclk_table);
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+ if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ }
+
+ /* dclk */
+ dpm_table = &(dpm_ctx->dclk_table);
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+ if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ }
+#endif
+
+ /* socclk */
+ dpm_table = &(dpm_ctx->soc_table);
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+ if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ }
+
+#if 0
+ /* eclk */
+ dpm_table = &(dpm_ctx->eclk_table);
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
+ dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+
+ if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
+ }
+
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
+ }
+#endif
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 122/138] drm/amd/powerplay: add vega20_notify_smc_display_config functions for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (120 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 121/138] drm/amd/powerplay: add apply_clock_adjust_rules " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 123/138] drm/amd/powerplay: add vega20_find/force_higest/lowest_dpm " Huang Rui
` (16 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add vega20_notify_smc_display_config functions to
support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 45 ++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 7f351c8..0440e5c 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1569,6 +1569,51 @@ static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
return 0;
}
+static int
+vega20_notify_smc_dispaly_config(struct smu_context *smu)
+{
+ struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
+ struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
+ struct smu_clocks min_clocks = {0};
+ struct pp_display_clock_request clock_req;
+ int ret = 0;
+
+ min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
+ min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
+ min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
+
+ if (smu_feature_is_supported(smu, FEATURE_DPM_DCEFCLK_BIT)) {
+ clock_req.clock_type = amd_pp_dcef_clock;
+ clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+ if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
+ if (smu_feature_is_supported(smu, FEATURE_DS_DCEFCLK_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMinDeepSleepDcefclk,
+ min_clocks.dcef_clock_in_sr/100);
+ if (ret) {
+ pr_err("Attempt to set divider for DCEFCLK Failed!");
+ return ret;
+ }
+ }
+ } else {
+ pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetHardMinByFreq,
+ (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
+ if (ret) {
+ pr_err("[%s] Set hard min uclk failed!", __func__);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 123/138] drm/amd/powerplay: add vega20_find/force_higest/lowest_dpm for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (121 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 122/138] drm/amd/powerplay: add vega20_notify_smc_display_config functions " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 124/138] drm/amd/powerplay: add vega20_unforce_dpm_levels " Huang Rui
` (15 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add vega20_find_highest_dpm_level, vega20_find_lowest_dpm_level,
vega20_force_highest_dpm and vega20_force_lowest_dpm functions
to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 111 +++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 0440e5c..ec14c91 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1614,6 +1614,117 @@ vega20_notify_smc_dispaly_config(struct smu_context *smu)
return 0;
}
+static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
+{
+ uint32_t i;
+
+ for (i = 0; i < table->count; i++) {
+ if (table->dpm_levels[i].enabled)
+ break;
+ }
+ if (i >= table->count) {
+ i = 0;
+ table->dpm_levels[i].enabled = true;
+ }
+
+ return i;
+}
+
+static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
+{
+ int i = 0;
+
+ if (!table) {
+ pr_err("[%s] DPM Table does not exist!", __func__);
+ return 0;
+ }
+ if (table->count <= 0) {
+ pr_err("[%s] DPM Table has no entry!", __func__);
+ return 0;
+ }
+ if (table->count > MAX_REGULAR_DPM_NUMBER) {
+ pr_err("[%s] DPM Table has too many entries!", __func__);
+ return MAX_REGULAR_DPM_NUMBER - 1;
+ }
+
+ for (i = table->count - 1; i >= 0; i--) {
+ if (table->dpm_levels[i].enabled)
+ break;
+ }
+ if (i < 0) {
+ i = 0;
+ table->dpm_levels[i].enabled = true;
+ }
+
+ return i;
+}
+
+static int vega20_force_dpm_highest(struct smu_context *smu)
+{
+ uint32_t soft_level;
+ int ret = 0;
+ struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
+
+ soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
+
+ dpm_table->gfx_table.dpm_state.soft_min_level =
+ dpm_table->gfx_table.dpm_state.soft_max_level =
+ dpm_table->gfx_table.dpm_levels[soft_level].value;
+
+ soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
+
+ dpm_table->mem_table.dpm_state.soft_min_level =
+ dpm_table->mem_table.dpm_state.soft_max_level =
+ dpm_table->mem_table.dpm_levels[soft_level].value;
+
+ ret = vega20_upload_dpm_min_level(smu);
+ if (ret) {
+ pr_err("Failed to upload boot level to highest!");
+ return ret;
+ }
+
+ ret = vega20_upload_dpm_max_level(smu);
+ if (ret) {
+ pr_err("Failed to upload dpm max level to highest!");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int vega20_force_dpm_lowest(struct smu_context *smu)
+{
+ uint32_t soft_level;
+ int ret = 0;
+ struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
+
+ soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
+
+ dpm_table->gfx_table.dpm_state.soft_min_level =
+ dpm_table->gfx_table.dpm_state.soft_max_level =
+ dpm_table->gfx_table.dpm_levels[soft_level].value;
+
+ soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
+
+ dpm_table->mem_table.dpm_state.soft_min_level =
+ dpm_table->mem_table.dpm_state.soft_max_level =
+ dpm_table->mem_table.dpm_levels[soft_level].value;
+
+ ret = vega20_upload_dpm_min_level(smu);
+ if (ret) {
+ pr_err("Failed to upload boot level to lowest!");
+ return ret;
+ }
+
+ ret = vega20_upload_dpm_max_level(smu);
+ if (ret) {
+ pr_err("Failed to upload dpm max level to lowest!");
+ return ret;
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 124/138] drm/amd/powerplay: add vega20_unforce_dpm_levels for SMU11.
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (122 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 123/138] drm/amd/powerplay: add vega20_find/force_higest/lowest_dpm " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 125/138] drm/amd/powerplay: implement power_dpm_force_performance_level " Huang Rui
` (14 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add vega20_unforce_dpm_levels to support sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index ec14c91..12f6c38 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1725,6 +1725,25 @@ static int vega20_force_dpm_lowest(struct smu_context *smu)
return ret;
}
+static int vega20_unforce_dpm_levels(struct smu_context *smu)
+{
+ int ret = 0;
+
+ ret = vega20_upload_dpm_min_level(smu);
+ if (ret) {
+ pr_err("Failed to upload DPM Bootup Levels!");
+ return ret;
+ }
+
+ ret = vega20_upload_dpm_max_level(smu);
+ if (ret) {
+ pr_err("Failed to upload DPM Max Levels!");
+ return ret;
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 125/138] drm/amd/powerplay: implement power_dpm_force_performance_level for SMU11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (123 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 124/138] drm/amd/powerplay: add vega20_unforce_dpm_levels " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 126/138] drm/amd/powerplay: add sys interface for pcie for smu Huang Rui
` (13 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Chengming Gui <Jack.Gui@amd.com>
add get_performance_level and force_performance_level
to implement the sys interface for SMU11.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 23 +++++-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 -
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 99 ++++++++++++++++++++++++++
5 files changed, 127 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7015e03..a9e1410 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -264,7 +264,9 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return snprintf(buf, PAGE_SIZE, "off\n");
- if (adev->powerplay.pp_funcs->get_performance_level)
+ if (is_support_sw_smu(adev))
+ level = smu_get_performance_level(&adev->smu);
+ else if (adev->powerplay.pp_funcs->get_performance_level)
level = amdgpu_dpm_get_performance_level(adev);
else
level = adev->pm.dpm.forced_level;
@@ -297,7 +299,9 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- if (adev->powerplay.pp_funcs->get_performance_level)
+ if (is_support_sw_smu(adev))
+ current_level = smu_get_performance_level(&adev->smu);
+ else if (adev->powerplay.pp_funcs->get_performance_level)
current_level = amdgpu_dpm_get_performance_level(adev);
if (strncmp("low", buf, strlen("low")) == 0) {
@@ -326,7 +330,20 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
if (current_level == level)
return count;
- if (adev->powerplay.pp_funcs->force_performance_level) {
+ if (is_support_sw_smu(adev)) {
+ mutex_lock(&adev->pm.mutex);
+ if (adev->pm.dpm.thermal_active) {
+ count = -EINVAL;
+ mutex_unlock(&adev->pm.mutex);
+ goto fail;
+ }
+ ret = smu_force_performance_level(&adev->smu, level);
+ if (ret)
+ count = -EINVAL;
+ else
+ adev->pm.dpm.forced_level = level;
+ mutex_unlock(&adev->pm.mutex);
+ } else if (adev->powerplay.pp_funcs->force_performance_level) {
mutex_lock(&adev->pm.mutex);
if (adev->pm.dpm.thermal_active) {
count = -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 2fe3b57..912f44e 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -344,6 +344,8 @@ static int smu_sw_init(void *handle)
smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
smu->display_config = &adev->pm.pm_display_cfg;
+ smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
+ smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
ret = smu_init_microcode(smu);
if (ret) {
pr_err("Failed to load smu firmware!\n");
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index bcd7479..ae9aca4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -423,6 +423,8 @@ struct pptable_funcs {
*clocks);
int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
+ enum amd_dpm_forced_level (*get_performance_level)(struct smu_context *smu);
+ int (*force_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
};
struct smu_funcs
@@ -594,6 +596,10 @@ struct smu_funcs
((smu)->funcs->get_power_profile_mode ? (smu)->funcs->get_power_profile_mode((smu), buf) : 0)
#define smu_set_power_profile_mode(smu, param, param_size) \
((smu)->funcs->set_power_profile_mode ? (smu)->funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
+#define smu_get_performance_level(smu) \
+ ((smu)->ppt_funcs->get_performance_level ? (smu)->ppt_funcs->get_performance_level((smu)) : 0)
+#define smu_force_performance_level(smu, level) \
+ ((smu)->ppt_funcs->force_performance_level ? (smu)->ppt_funcs->force_performance_level((smu), (level)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f11df04..3b2464f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1097,7 +1097,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
PPCLK_e clk_select = 0;
uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
- mutex_lock(&smu->mutex);
if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
switch (clk_type) {
case amd_pp_dcef_clock:
@@ -1126,7 +1125,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
}
failed:
- mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 12f6c38..14185bc 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1744,6 +1744,103 @@ static int vega20_unforce_dpm_levels(struct smu_context *smu)
return ret;
}
+static enum amd_dpm_forced_level vega20_get_performance_level(struct smu_context *smu)
+{
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ if (!smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
+ if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
+ mutex_lock(&(smu->mutex));
+ smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
+ mutex_unlock(&(smu->mutex));
+ }
+ return smu_dpm_ctx->dpm_level;
+}
+
+static int
+vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+{
+ int ret = 0;
+ int index = 0;
+ int i = 0;
+ uint32_t sclk_mask, mclk_mask, soc_mask;
+ long workload;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ if (!smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
+ for (i = 0; i < smu->adev->num_ip_blocks; i++) {
+ if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
+ break;
+ }
+ mutex_lock(&smu->mutex);
+ smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
+ ret = vega20_display_config_changed(smu);
+ if (ret) {
+ pr_err("Failed to change display config!");
+ goto failed;
+ }
+ ret = vega20_apply_clocks_adjust_rules(smu);
+ if (ret) {
+ pr_err("Failed to apply clocks adjust rules!");
+ goto failed;
+ }
+ ret = vega20_notify_smc_dispaly_config(smu);
+ if (ret) {
+ pr_err("Failed to notify smc display config!");
+ goto failed;
+ }
+ switch (level) {
+ case AMD_DPM_FORCED_LEVEL_HIGH:
+ ret = vega20_force_dpm_highest(smu);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_LOW:
+ ret = vega20_force_dpm_lowest(smu);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_AUTO:
+ ret = vega20_unforce_dpm_levels(smu);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ ret = vega20_get_profiling_clk_mask(smu, level,
+ &sclk_mask,
+ &mclk_mask,
+ &soc_mask);
+ if (ret)
+ goto failed;
+ vega20_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
+ vega20_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_MANUAL:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ default:
+ break;
+ }
+
+ if (!ret)
+ smu_dpm_ctx->dpm_level = level;
+
+ if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ index = fls(smu->workload_mask);
+ index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
+ workload = smu->workload_setting[index];
+
+ if (smu->power_profile_mode != workload)
+ smu->funcs->set_power_profile_mode(smu, &workload, 0);
+ }
+
+failed:
+ mutex_unlock(&smu->mutex);
+ return ret;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -1761,6 +1858,8 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
.set_default_od8_settings = vega20_set_default_od8_setttings,
.get_od_percentage = vega20_get_od_percentage,
+ .get_performance_level = vega20_get_performance_level,
+ .force_performance_level = vega20_force_performance_level,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 126/138] drm/amd/powerplay: add sys interface for pcie for smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (124 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 125/138] drm/amd/powerplay: implement power_dpm_force_performance_level " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 127/138] drm/amd/powerplay: add function to update overdrive settings Huang Rui
` (12 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add sys interface for set/get PCIE info for SMU.
The related operate will do nothing as vega20 do not support it now.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8 ++++++--
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 ++++++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a9e1410..baff3b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1005,7 +1005,9 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
- if (adev->powerplay.pp_funcs->print_clock_levels)
+ if (is_support_sw_smu(adev))
+ return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
+ else if (adev->powerplay.pp_funcs->print_clock_levels)
return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
else
return snprintf(buf, PAGE_SIZE, "\n");
@@ -1025,7 +1027,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
if (ret)
return ret;
- if (adev->powerplay.pp_funcs->force_clock_level)
+ if (is_support_sw_smu(adev))
+ ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
+ else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 14185bc..dff5d83 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -775,6 +775,9 @@ static int vega20_print_clk_levels(struct smu_context *smu,
? "*" : "");
break;
+ case PP_PCIE:
+ break;
+
case OD_SCLK:
if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
@@ -1016,6 +1019,9 @@ static int vega20_force_clk_levels(struct smu_context *smu,
break;
+ case PP_PCIE:
+ break;
+
default:
break;
}
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 127/138] drm/amd/powerplay: add function to update overdrive settings
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (125 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 126/138] drm/amd/powerplay: add sys interface for pcie for smu Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 128/138] drm/amd/powerplay: add sys interface for set sclk_od/mclk_od for smu Huang Rui
` (11 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add function of smu_update_specified_od8_value to modify specified
overdrive value.
Add fucntion of smu_update_od8_settings to update overdrive table.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 10 ++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 27 +++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 78 ++++++++++++++++++++++++++
3 files changed, 115 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ae9aca4..19bf9e5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -410,6 +410,9 @@ struct pptable_funcs {
int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
int (*set_default_od8_settings)(struct smu_context *smu);
+ int (*update_specified_od8_value)(struct smu_context *smu,
+ uint32_t index,
+ uint32_t value);
int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type type);
int (*get_clock_by_type_with_latency)(struct smu_context *smu,
enum amd_pp_clock_type type,
@@ -498,6 +501,9 @@ struct smu_funcs
int (*conv_power_profile_to_pplib_workload)(int power_profile);
int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
+ int (*update_od8_settings)(struct smu_context *smu,
+ uint32_t index,
+ uint32_t value);
};
#define smu_init_microcode(smu) \
@@ -546,6 +552,8 @@ struct smu_funcs
((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
#define smu_set_od8_default_settings(smu) \
((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu)) : 0)
+#define smu_update_od8_settings(smu, index, value) \
+ ((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
#define smu_send_smc_msg(smu, msg) \
((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
#define smu_send_smc_msg_with_param(smu, msg, param) \
@@ -578,6 +586,8 @@ struct smu_funcs
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
#define smu_set_default_od8_settings(smu) \
((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+#define smu_update_specified_od8_value(smu, index, value) \
+ ((smu)->ppt_funcs->update_specified_od8_value ? (smu)->ppt_funcs->update_specified_od8_value((smu), (index), (value)) : 0)
#define smu_get_power_limit(smu) \
((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
#define smu_get_current_clk_freq(smu, clk_id, value) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3b2464f..1304ba1 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1521,6 +1521,32 @@ static int smu_v11_0_set_power_profile_mode(struct smu_context *smu, long *input
return ret;
}
+static int smu_v11_0_update_od8_settings(struct smu_context *smu,
+ uint32_t index,
+ uint32_t value)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ int ret;
+
+ ret = smu_update_table(smu, TABLE_OVERDRIVE,
+ table_context->overdrive_table, false);
+ if (ret) {
+ pr_err("Failed to export over drive table!\n");
+ return ret;
+ }
+
+ smu_update_specified_od8_value(smu, index, value);
+
+ ret = smu_update_table(smu, TABLE_OVERDRIVE,
+ table_context->overdrive_table, true);
+ if (ret) {
+ pr_err("Failed to import over drive table!\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1564,6 +1590,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.conv_power_profile_to_pplib_workload = smu_v11_0_conv_power_profile_to_pplib_workload,
.get_power_profile_mode = smu_v11_0_get_power_profile_mode,
.set_power_profile_mode = smu_v11_0_set_power_profile_mode,
+ .update_od8_settings = smu_v11_0_update_od8_settings,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index dff5d83..da224d8 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1847,6 +1847,83 @@ vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_leve
return ret;
}
+static int vega20_update_specified_od8_value(struct smu_context *smu,
+ uint32_t index,
+ uint32_t value)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ OverDriveTable_t *od_table =
+ (OverDriveTable_t *)(table_context->overdrive_table);
+ struct vega20_od8_settings *od8_settings =
+ (struct vega20_od8_settings *)table_context->od8_settings;
+
+ switch (index) {
+ case OD8_SETTING_GFXCLK_FMIN:
+ od_table->GfxclkFmin = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_FMAX:
+ if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
+ value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
+ return -EINVAL;
+ od_table->GfxclkFmax = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_FREQ1:
+ od_table->GfxclkFreq1 = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_VOLTAGE1:
+ od_table->GfxclkVolt1 = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_FREQ2:
+ od_table->GfxclkFreq2 = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_VOLTAGE2:
+ od_table->GfxclkVolt2 = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_FREQ3:
+ od_table->GfxclkFreq3 = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_GFXCLK_VOLTAGE3:
+ od_table->GfxclkVolt3 = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_UCLK_FMAX:
+ if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
+ value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
+ return -EINVAL;
+ od_table->UclkFmax = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_POWER_PERCENTAGE:
+ od_table->OverDrivePct = (int16_t)value;
+ break;
+
+ case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
+ od_table->FanMaximumRpm = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_FAN_MIN_SPEED:
+ od_table->FanMinimumPwm = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_FAN_TARGET_TEMP:
+ od_table->FanTargetTemperature = (uint16_t)value;
+ break;
+
+ case OD8_SETTING_OPERATING_TEMP_MAX:
+ od_table->MaxOpTemp = (uint16_t)value;
+ break;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -1866,6 +1943,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_od_percentage = vega20_get_od_percentage,
.get_performance_level = vega20_get_performance_level,
.force_performance_level = vega20_force_performance_level,
+ .update_specified_od8_value = vega20_update_specified_od8_value,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 128/138] drm/amd/powerplay: add sys interface for set sclk_od/mclk_od for smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (126 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 127/138] drm/amd/powerplay: add function to update overdrive settings Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 129/138] drm/amd/powerplay: add sys interface to set pp_od_clk_voltage " Huang Rui
` (10 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add sys interface for set pp_sclk_od and pp_mclk_od for smu.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 34 +++++++++-----
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 62 ++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index baff3b9..1a81a1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1070,14 +1070,19 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
count = -EINVAL;
goto fail;
}
- if (adev->powerplay.pp_funcs->set_sclk_od)
- amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ if (is_support_sw_smu(adev)) {
+ value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
} else {
- adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
- amdgpu_pm_compute_clocks(adev);
+ if (adev->powerplay.pp_funcs->set_sclk_od)
+ amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
+
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ } else {
+ adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
+ amdgpu_pm_compute_clocks(adev);
+ }
}
fail:
@@ -1116,14 +1121,19 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
count = -EINVAL;
goto fail;
}
- if (adev->powerplay.pp_funcs->set_mclk_od)
- amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ if (is_support_sw_smu(adev)) {
+ value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
} else {
- adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
- amdgpu_pm_compute_clocks(adev);
+ if (adev->powerplay.pp_funcs->set_mclk_od)
+ amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
+
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ } else {
+ adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
+ amdgpu_pm_compute_clocks(adev);
+ }
}
fail:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 19bf9e5..0d8c601 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -414,6 +414,9 @@ struct pptable_funcs {
uint32_t index,
uint32_t value);
int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type type);
+ int (*set_od_percentage)(struct smu_context *smu,
+ enum pp_clock_type type,
+ uint32_t value);
int (*get_clock_by_type_with_latency)(struct smu_context *smu,
enum amd_pp_clock_type type,
struct
@@ -598,6 +601,8 @@ struct smu_funcs
((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (type), (level)) : 0)
#define smu_get_od_percentage(smu, type) \
((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
+#define smu_set_od_percentage(smu, type, value) \
+ ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
#define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_read_sensor(smu, sensor, data, size) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index da224d8..9e30d92 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1924,6 +1924,67 @@ static int vega20_update_specified_od8_value(struct smu_context *smu,
return 0;
}
+static int vega20_set_od_percentage(struct smu_context *smu,
+ enum pp_clock_type type,
+ uint32_t value)
+{
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_dpm_table *golden_table = NULL;
+ struct vega20_single_dpm_table *single_dpm_table;
+ struct vega20_single_dpm_table *golden_dpm_table;
+ uint32_t od_clk, index;
+ int ret, feature_enabled;
+ PPCLK_e clk_id;
+
+ dpm_table = smu_dpm->dpm_context;
+ golden_table = smu_dpm->golden_dpm_context;
+
+ switch (type) {
+ case OD_SCLK:
+ single_dpm_table = &(dpm_table->gfx_table);
+ golden_dpm_table = &(golden_table->gfx_table);
+ feature_enabled = smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT);
+ clk_id = PPCLK_GFXCLK;
+ index = OD8_SETTING_GFXCLK_FMAX;
+ break;
+ case OD_MCLK:
+ single_dpm_table = &(dpm_table->mem_table);
+ golden_dpm_table = &(golden_table->mem_table);
+ feature_enabled = smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT);
+ clk_id = PPCLK_UCLK;
+ index = OD8_SETTING_UCLK_FMAX;
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+
+ od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
+ od_clk /= 100;
+ od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
+
+ ret = smu_update_od8_settings(smu, index, od_clk);
+ if (ret) {
+ pr_err("[Setoverdrive] failed to set od clk!\n");
+ return ret;
+ }
+
+ if (feature_enabled) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ clk_id);
+ if (ret) {
+ pr_err("[Setoverdrive] failed to refresh dpm table!\n");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -1944,6 +2005,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_performance_level = vega20_get_performance_level,
.force_performance_level = vega20_force_performance_level,
.update_specified_od8_value = vega20_update_specified_od8_value,
+ .set_od_percentage = vega20_set_od_percentage,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 129/138] drm/amd/powerplay: add sys interface to set pp_od_clk_voltage for smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (127 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 128/138] drm/amd/powerplay: add sys interface for set sclk_od/mclk_od for smu Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 130/138] drm/amd/powerplay: adjust power state when set od_clk Huang Rui
` (9 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add sys interface to set pp_od_clk_voltage for smu.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 30 ++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 +
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 223 +++++++++++++++++++++++++
3 files changed, 250 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1a81a1d..03eea8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -650,19 +650,29 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
tmp_str++;
}
- if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
- ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
- parameter, parameter_size);
+ if (is_support_sw_smu(adev)) {
+ ret = smu_od_edit_dpm_table(&adev->smu, type,
+ parameter, parameter_size);
- if (ret)
- return -EINVAL;
+ if (ret)
+ return -EINVAL;
+ } else {
+ if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
+ ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+ parameter, parameter_size);
- if (type == PP_OD_COMMIT_DPM_TABLE) {
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
- return count;
- } else {
+ if (ret)
return -EINVAL;
+
+ if (type == PP_OD_COMMIT_DPM_TABLE) {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev,
+ AMD_PP_TASK_READJUST_POWER_STATE,
+ NULL);
+ return count;
+ } else {
+ return -EINVAL;
+ }
}
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 0d8c601..ddcfbd9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -310,6 +310,8 @@ struct smu_table_context
uint32_t *od_settings_min;
void *overdrive_table;
void *od8_settings;
+ bool od_gfxclk_update;
+ bool od_memclk_update;
};
struct smu_dpm_context {
@@ -417,6 +419,9 @@ struct pptable_funcs {
int (*set_od_percentage)(struct smu_context *smu,
enum pp_clock_type type,
uint32_t value);
+ int (*od_edit_dpm_table)(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size);
int (*get_clock_by_type_with_latency)(struct smu_context *smu,
enum amd_pp_clock_type type,
struct
@@ -603,6 +608,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
#define smu_set_od_percentage(smu, type, value) \
((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
+#define smu_od_edit_dpm_table(smu, type, input, size) \
+ ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
#define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
#define smu_read_sensor(smu, sensor, data, size) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 9e30d92..7745319 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1985,6 +1985,228 @@ static int vega20_set_od_percentage(struct smu_context *smu,
return 0;
}
+static int vega20_odn_edit_dpm_table(struct smu_context *smu,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size)
+{
+ struct smu_table_context *table_context = &smu->smu_table;
+ OverDriveTable_t *od_table =
+ (OverDriveTable_t *)(table_context->overdrive_table);
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ struct vega20_dpm_table *dpm_table = NULL;
+ struct vega20_single_dpm_table *single_dpm_table;
+ struct vega20_od8_settings *od8_settings =
+ (struct vega20_od8_settings *)table_context->od8_settings;
+ struct pp_clock_levels_with_latency clocks;
+ int32_t input_index, input_clk, input_vol, i;
+ int od8_id, ret;
+
+ dpm_table = smu_dpm->dpm_context;
+
+ if (!input) {
+ pr_warn("NULL user input for clock and voltage\n");
+ return -EINVAL;
+ }
+
+ switch (type) {
+ case PP_OD_EDIT_SCLK_VDDC_TABLE:
+ if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
+ pr_info("Sclk min/max frequency overdrive not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ for (i = 0; i < size; i += 2) {
+ if (i + 2 > size) {
+ pr_info("invalid number of input parameters %d\n", size);
+ return -EINVAL;
+ }
+
+ input_index = input[i];
+ input_clk = input[i + 1];
+
+ if (input_index != 0 && input_index != 1) {
+ pr_info("Invalid index %d\n", input_index);
+ pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
+ return -EINVAL;
+ }
+
+ if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
+ input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
+ pr_info("clock freq %d is not within allowed range [%d - %d]\n",
+ input_clk,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
+ return -EINVAL;
+ }
+
+ if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
+ od_table->GfxclkFmin = input_clk;
+ table_context->od_gfxclk_update = true;
+ } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
+ od_table->GfxclkFmax = input_clk;
+ table_context->od_gfxclk_update = true;
+ }
+ }
+
+ break;
+
+ case PP_OD_EDIT_MCLK_VDDC_TABLE:
+ if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
+ pr_info("Mclk max frequency overdrive not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ single_dpm_table = &(dpm_table->mem_table);
+ ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
+ if (ret) {
+ pr_err("Attempt to get memory clk levels Failed!");
+ return ret;
+ }
+
+ for (i = 0; i < size; i += 2) {
+ if (i + 2 > size) {
+ pr_info("invalid number of input parameters %d\n",
+ size);
+ return -EINVAL;
+ }
+
+ input_index = input[i];
+ input_clk = input[i + 1];
+
+ if (input_index != 1) {
+ pr_info("Invalid index %d\n", input_index);
+ pr_info("Support max Mclk frequency setting only which index by 1\n");
+ return -EINVAL;
+ }
+
+ if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
+ input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
+ pr_info("clock freq %d is not within allowed range [%d - %d]\n",
+ input_clk,
+ clocks.data[0].clocks_in_khz / 1000,
+ od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
+ return -EINVAL;
+ }
+
+ if (input_index == 1 && od_table->UclkFmax != input_clk) {
+ table_context->od_gfxclk_update = true;
+ od_table->UclkFmax = input_clk;
+ }
+ }
+
+ break;
+
+ case PP_OD_EDIT_VDDC_CURVE:
+ if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
+ od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
+ pr_info("Voltage curve calibrate not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ for (i = 0; i < size; i += 3) {
+ if (i + 3 > size) {
+ pr_info("invalid number of input parameters %d\n",
+ size);
+ return -EINVAL;
+ }
+
+ input_index = input[i];
+ input_clk = input[i + 1];
+ input_vol = input[i + 2];
+
+ if (input_index > 2) {
+ pr_info("Setting for point %d is not supported\n",
+ input_index + 1);
+ pr_info("Three supported points index by 0, 1, 2\n");
+ return -EINVAL;
+ }
+
+ od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
+ if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
+ input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
+ pr_info("clock freq %d is not within allowed range [%d - %d]\n",
+ input_clk,
+ od8_settings->od8_settings_array[od8_id].min_value,
+ od8_settings->od8_settings_array[od8_id].max_value);
+ return -EINVAL;
+ }
+
+ od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
+ if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
+ input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
+ pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
+ input_vol,
+ od8_settings->od8_settings_array[od8_id].min_value,
+ od8_settings->od8_settings_array[od8_id].max_value);
+ return -EINVAL;
+ }
+
+ switch (input_index) {
+ case 0:
+ od_table->GfxclkFreq1 = input_clk;
+ od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
+ break;
+ case 1:
+ od_table->GfxclkFreq2 = input_clk;
+ od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
+ break;
+ case 2:
+ od_table->GfxclkFreq3 = input_clk;
+ od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
+ break;
+ }
+ }
+
+ break;
+
+ case PP_OD_RESTORE_DEFAULT_TABLE:
+ ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
+ if (ret) {
+ pr_err("Failed to export over drive table!\n");
+ return ret;
+ }
+
+ break;
+
+ case PP_OD_COMMIT_DPM_TABLE:
+ ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
+ if (ret) {
+ pr_err("Failed to import over drive table!\n");
+ return ret;
+ }
+
+ /* retrieve updated gfxclk table */
+ if (table_context->od_gfxclk_update) {
+ table_context->od_gfxclk_update = false;
+ single_dpm_table = &(dpm_table->gfx_table);
+
+ if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
+ ret = vega20_set_single_dpm_table(smu, single_dpm_table,
+ PPCLK_GFXCLK);
+ if (ret) {
+ pr_err("[Setoverdrive] failed to refresh dpm table!\n");
+ return ret;
+ }
+ } else {
+ single_dpm_table->count = 1;
+ single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ }
+ }
+
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs vega20_ppt_funcs = {
.alloc_dpm_context = vega20_allocate_dpm_context,
.store_powerplay_table = vega20_store_powerplay_table,
@@ -2006,6 +2228,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.force_performance_level = vega20_force_performance_level,
.update_specified_od8_value = vega20_update_specified_od8_value,
.set_od_percentage = vega20_set_od_percentage,
+ .od_edit_dpm_table = vega20_odn_edit_dpm_table,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 130/138] drm/amd/powerplay: adjust power state when set od_clk
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (128 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 129/138] drm/amd/powerplay: add sys interface to set pp_od_clk_voltage " Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 131/138] drm/amd/powerplay: dpm clk can be set only when performance level is manual Huang Rui
` (8 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Expose the function of adjust_power_state_dynamic to make it common to
other functions.
Add the operate of adjust powet state when set od percentage or
overdrive commit dpm table.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 80 +++++++++++++++++++++---------
1 file changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 7745319..e117af4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1764,44 +1764,35 @@ static enum amd_dpm_forced_level vega20_get_performance_level(struct smu_context
return smu_dpm_ctx->dpm_level;
}
-static int
-vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+static int vega20_adjust_power_state_dynamic(struct smu_context *smu,
+ enum amd_dpm_forced_level level)
{
int ret = 0;
int index = 0;
- int i = 0;
uint32_t sclk_mask, mclk_mask, soc_mask;
long workload;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- if (!smu_dpm_ctx->dpm_context)
- return -EINVAL;
- for (i = 0; i < smu->adev->num_ip_blocks; i++) {
- if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
- break;
- }
- mutex_lock(&smu->mutex);
- smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
ret = vega20_display_config_changed(smu);
if (ret) {
pr_err("Failed to change display config!");
- goto failed;
+ return ret;
}
ret = vega20_apply_clocks_adjust_rules(smu);
if (ret) {
pr_err("Failed to apply clocks adjust rules!");
- goto failed;
+ return ret;
}
ret = vega20_notify_smc_dispaly_config(smu);
if (ret) {
pr_err("Failed to notify smc display config!");
- goto failed;
+ return ret;
}
+
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
ret = vega20_force_dpm_highest(smu);
break;
-
case AMD_DPM_FORCED_LEVEL_LOW:
ret = vega20_force_dpm_lowest(smu);
break;
@@ -1819,7 +1810,7 @@ vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_leve
&mclk_mask,
&soc_mask);
if (ret)
- goto failed;
+ return ret;
vega20_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
vega20_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
break;
@@ -1842,8 +1833,31 @@ vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_leve
smu->funcs->set_power_profile_mode(smu, &workload, 0);
}
-failed:
+ return ret;
+}
+
+static int
+vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+{
+ int ret = 0;
+ int i;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+
+ if (!smu_dpm_ctx->dpm_context)
+ return -EINVAL;
+
+ for (i = 0; i < smu->adev->num_ip_blocks; i++) {
+ if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
+ break;
+ }
+
+ mutex_lock(&smu->mutex);
+
+ smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
+ ret = vega20_adjust_power_state_dynamic(smu, level);
+
mutex_unlock(&smu->mutex);
+
return ret;
}
@@ -1934,9 +1948,12 @@ static int vega20_set_od_percentage(struct smu_context *smu,
struct vega20_single_dpm_table *single_dpm_table;
struct vega20_single_dpm_table *golden_dpm_table;
uint32_t od_clk, index;
- int ret, feature_enabled;
+ int ret = 0;
+ int feature_enabled;
PPCLK_e clk_id;
+ mutex_lock(&(smu->mutex));
+
dpm_table = smu_dpm->dpm_context;
golden_table = smu_dpm->golden_dpm_context;
@@ -1956,10 +1973,13 @@ static int vega20_set_od_percentage(struct smu_context *smu,
index = OD8_SETTING_UCLK_FMAX;
break;
default:
- return -EINVAL;
+ ret = -EINVAL;
break;
}
+ if (ret)
+ goto set_od_failed;
+
od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
od_clk /= 100;
od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
@@ -1967,7 +1987,7 @@ static int vega20_set_od_percentage(struct smu_context *smu,
ret = smu_update_od8_settings(smu, index, od_clk);
if (ret) {
pr_err("[Setoverdrive] failed to set od clk!\n");
- return ret;
+ goto set_od_failed;
}
if (feature_enabled) {
@@ -1975,14 +1995,19 @@ static int vega20_set_od_percentage(struct smu_context *smu,
clk_id);
if (ret) {
pr_err("[Setoverdrive] failed to refresh dpm table!\n");
- return ret;
+ goto set_od_failed;
}
} else {
single_dpm_table->count = 1;
single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
}
- return 0;
+ ret = vega20_adjust_power_state_dynamic(smu, smu_dpm->dpm_level);
+
+set_od_failed:
+ mutex_unlock(&(smu->mutex));
+
+ return ret;
}
static int vega20_odn_edit_dpm_table(struct smu_context *smu,
@@ -1999,7 +2024,8 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
(struct vega20_od8_settings *)table_context->od8_settings;
struct pp_clock_levels_with_latency clocks;
int32_t input_index, input_clk, input_vol, i;
- int od8_id, ret;
+ int od8_id;
+ int ret = 0;
dpm_table = smu_dpm->dpm_context;
@@ -2204,7 +2230,13 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
return -EINVAL;
}
- return 0;
+ if (type == PP_OD_COMMIT_DPM_TABLE) {
+ mutex_lock(&(smu->mutex));
+ ret = vega20_adjust_power_state_dynamic(smu, smu_dpm->dpm_level);
+ mutex_unlock(&(smu->mutex));
+ }
+
+ return ret;
}
static const struct pptable_funcs vega20_ppt_funcs = {
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 131/138] drm/amd/powerplay: dpm clk can be set only when performance level is manual
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (129 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 130/138] drm/amd/powerplay: adjust power state when set od_clk Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 132/138] drm/amd/powerplay: implement update enabled feature state to smc for smu11 Huang Rui
` (7 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Add condition to make dpm clk can not be set when perfomance level isn't
equal to manual.
Add mutex lock to smu when set dpm clk.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 31 ++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index e117af4..32b1ffc 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -955,7 +955,15 @@ static int vega20_force_clk_levels(struct smu_context *smu,
struct vega20_dpm_table *dpm_table;
struct vega20_single_dpm_table *single_dpm_table;
uint32_t soft_min_level, soft_max_level;
- int ret;
+ struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ int ret = 0;
+
+ if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ pr_info("force clock level is for dpm manual mode only.\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&(smu->mutex));
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -969,7 +977,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
if (soft_max_level >= single_dpm_table->count) {
pr_err("Clock level specified %d is over max allowed %d\n",
soft_max_level, single_dpm_table->count - 1);
- return -EINVAL;
+ ret = -EINVAL;
+ break;
}
single_dpm_table->dpm_state.soft_min_level =
@@ -980,14 +989,12 @@ static int vega20_force_clk_levels(struct smu_context *smu,
ret = vega20_upload_dpm_min_level(smu);
if (ret) {
pr_err("Failed to upload boot level to lowest!\n");
- return ret;
+ break;
}
ret = vega20_upload_dpm_max_level(smu);
- if (ret) {
+ if (ret)
pr_err("Failed to upload dpm max level to highest!\n");
- return ret;
- }
break;
@@ -997,7 +1004,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
if (soft_max_level >= single_dpm_table->count) {
pr_err("Clock level specified %d is over max allowed %d\n",
soft_max_level, single_dpm_table->count - 1);
- return -EINVAL;
+ ret = -EINVAL;
+ break;
}
single_dpm_table->dpm_state.soft_min_level =
@@ -1008,14 +1016,12 @@ static int vega20_force_clk_levels(struct smu_context *smu,
ret = vega20_upload_dpm_min_level(smu);
if (ret) {
pr_err("Failed to upload boot level to lowest!\n");
- return ret;
+ break;
}
ret = vega20_upload_dpm_max_level(smu);
- if (ret) {
+ if (ret)
pr_err("Failed to upload dpm max level to highest!\n");
- return ret;
- }
break;
@@ -1026,7 +1032,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
break;
}
- return 0;
+ mutex_unlock(&(smu->mutex));
+ return ret;
}
static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 132/138] drm/amd/powerplay: implement update enabled feature state to smc for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (130 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 131/138] drm/amd/powerplay: dpm clk can be set only when performance level is manual Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 133/138] drm/amd/powerplay: hwmon don't check powerplay when sw smu is enabled Huang Rui
` (6 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <kevin1.wang@amd.com>
change:
1.when enable smu feature, the feature id will store sw-bitmap and smu
controller.
2.add feature mutex lock to protect feature bitmap changed when update
feature enabled state.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 45 +++++++++++++++++++++---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 47 ++++++++++++++++++++++++--
3 files changed, 89 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 912f44e..9262d98 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -163,16 +163,20 @@ int smu_feature_init_dpm(struct smu_context *smu)
int ret = 0;
uint32_t unallowed_feature_mask[SMU_FEATURE_MAX/32];
+ mutex_lock(&feature->mutex);
bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
+ mutex_unlock(&feature->mutex);
ret = smu_get_unallowed_feature_mask(smu, unallowed_feature_mask,
SMU_FEATURE_MAX/32);
if (ret)
return ret;
+ mutex_lock(&feature->mutex);
bitmap_andnot(feature->allowed, feature->allowed,
(unsigned long *)unallowed_feature_mask,
feature->feature_num);
+ mutex_unlock(&feature->mutex);
return ret;
}
@@ -180,38 +184,70 @@ int smu_feature_init_dpm(struct smu_context *smu)
int smu_feature_is_enabled(struct smu_context *smu, int feature_id)
{
struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+
WARN_ON(feature_id > feature->feature_num);
- return test_bit(feature_id, feature->enabled);
+
+ mutex_lock(&feature->mutex);
+ ret = test_bit(feature_id, feature->enabled);
+ mutex_unlock(&feature->mutex);
+
+ return ret;
}
int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable)
{
struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+
WARN_ON(feature_id > feature->feature_num);
+
+ mutex_lock(&feature->mutex);
+ ret = smu_feature_update_enable_state(smu, feature_id, enable);
+ if (ret)
+ goto failed;
+
if (enable)
test_and_set_bit(feature_id, feature->enabled);
else
test_and_clear_bit(feature_id, feature->enabled);
- return 0;
+
+failed:
+ mutex_unlock(&feature->mutex);
+
+ return ret;
}
int smu_feature_is_supported(struct smu_context *smu, int feature_id)
{
struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+
WARN_ON(feature_id > feature->feature_num);
- return test_bit(feature_id, feature->supported);
+
+ mutex_lock(&feature->mutex);
+ ret = test_bit(feature_id, feature->supported);
+ mutex_unlock(&feature->mutex);
+
+ return ret;
}
int smu_feature_set_supported(struct smu_context *smu, int feature_id,
bool enable)
{
struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+
WARN_ON(feature_id > feature->feature_num);
+
+ mutex_unlock(&feature->mutex);
if (enable)
test_and_set_bit(feature_id, feature->supported);
else
test_and_clear_bit(feature_id, feature->supported);
- return 0;
+ mutex_unlock(&feature->mutex);
+
+ return ret;
}
static int smu_set_funcs(struct amdgpu_device *adev)
@@ -319,6 +355,7 @@ static int smu_sw_init(void *handle)
smu->pool_size = adev->pm.smu_prv_buffer_size;
smu->smu_feature.feature_num = SMU_FEATURE_MAX;
+ mutex_init(&smu->smu_feature.mutex);
bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ddcfbd9..2c6923d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -340,6 +340,7 @@ struct smu_feature
DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
+ struct mutex mutex;
};
struct smu_clocks {
@@ -469,6 +470,7 @@ struct smu_funcs
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
int (*enable_all_mask)(struct smu_context *smu);
int (*disable_all_mask)(struct smu_context *smu);
+ int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
int (*notify_display_change)(struct smu_context *smu);
int (*get_power_limit)(struct smu_context *smu);
int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
@@ -580,6 +582,8 @@ struct smu_funcs
((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
#define smu_feature_disable_all(smu) \
((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
+#define smu_feature_update_enable_state(smu, feature_id, enabled) \
+ ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
#define smu_notify_display_change(smu) \
((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
#define smu_store_powerplay_table(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 1304ba1..0662f40 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -613,27 +613,67 @@ static int smu_v11_0_init_display(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
+{
+ uint32_t feature_low = 0, feature_high = 0;
+ int ret = 0;
+
+ if (feature_id >= 0 && feature_id < 31)
+ feature_low = (1 << feature_id);
+ else if (feature_id > 31 && feature_id < 63)
+ feature_high = (1 << feature_id);
+ else
+ return -EINVAL;
+
+ if (enabled) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+ feature_low);
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+ feature_high);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+ feature_low);
+ if (ret)
+ return ret;
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+ feature_high);
+ if (ret)
+ return ret;
+
+ }
+
+ return ret;
+}
+
static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
int ret = 0;
uint32_t feature_mask[2];
+ mutex_lock(&feature->mutex);
if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
- return -EINVAL;
+ goto failed;
bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
feature_mask[1]);
if (ret)
- return ret;
+ goto failed;
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
feature_mask[0]);
if (ret)
- return ret;
+ goto failed;
+failed:
+ mutex_unlock(&feature->mutex);
return ret;
}
@@ -1575,6 +1615,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_enabled_mask = smu_v11_0_get_enabled_mask,
.enable_all_mask = smu_v11_0_enable_all_mask,
.disable_all_mask = smu_v11_0_disable_all_mask,
+ .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
.notify_display_change = smu_v11_0_notify_display_change,
.get_power_limit = smu_v11_0_get_power_limit,
.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 133/138] drm/amd/powerplay: hwmon don't check powerplay when sw smu is enabled
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (131 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 132/138] drm/amd/powerplay: implement update enabled feature state to smc for smu11 Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 134/138] drm/amd/powerplay: implement uvd & vce dpm enable functions Huang Rui
` (5 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <kevin1.wang@amd.com>
when sw-smu is enabled, the driver won't init powerplay structure.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 ++++++++++++++++++----------------
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 03eea8b..7b6be5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2046,18 +2046,20 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
return 0;
- /* mask fan attributes if we have no bindings for this asic to expose */
- if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
- attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
- (!adev->powerplay.pp_funcs->get_fan_control_mode &&
- attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
- effective_mode &= ~S_IRUGO;
-
- if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
- attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
- (!adev->powerplay.pp_funcs->set_fan_control_mode &&
- attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
- effective_mode &= ~S_IWUSR;
+ if (!is_support_sw_smu(adev)) {
+ /* mask fan attributes if we have no bindings for this asic to expose */
+ if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
+ attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
+ (!adev->powerplay.pp_funcs->get_fan_control_mode &&
+ attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
+ effective_mode &= ~S_IRUGO;
+
+ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
+ attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
+ (!adev->powerplay.pp_funcs->set_fan_control_mode &&
+ attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
+ effective_mode &= ~S_IWUSR;
+ }
if ((adev->flags & AMD_IS_APU) &&
(attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
@@ -2065,20 +2067,22 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
return 0;
- /* hide max/min values if we can't both query and manage the fan */
- if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
- !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
- (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
- !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
- (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
- attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
- return 0;
-
- if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
- !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
- (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
- attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
- return 0;
+ if (!is_support_sw_smu(adev)) {
+ /* hide max/min values if we can't both query and manage the fan */
+ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
+ !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
+ (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
+ !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
+ (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
+ attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
+ return 0;
+
+ if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
+ !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
+ (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
+ attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
+ return 0;
+ }
/* only APUs have vddnb */
if (!(adev->flags & AMD_IS_APU) &&
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 134/138] drm/amd/powerplay: implement uvd & vce dpm enable functions
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (132 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 133/138] drm/amd/powerplay: hwmon don't check powerplay when sw smu is enabled Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 135/138] drm/amd/powerplay: implement sensor of uvd & vce power state for smu11 Huang Rui
` (4 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <kevin1.wang@amd.com>
add dpm enable functions for vce,uvd.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 25 +++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 2c6923d..ebde63d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -514,6 +514,8 @@ struct smu_funcs
int (*update_od8_settings)(struct smu_context *smu,
uint32_t index,
uint32_t value);
+ int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
+ int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
};
#define smu_init_microcode(smu) \
@@ -659,6 +661,10 @@ struct smu_funcs
((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+#define smu_dpm_set_uvd_enable(smu, enable) \
+ ((smu)->funcs->dpm_set_uvd_enable ? (smu)->funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+#define smu_dpm_set_vce_enable(smu, enable) \
+ ((smu)->funcs->dpm_set_vce_enable ? (smu)->funcs->dpm_set_vce_enable((smu), (enable)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 0662f40..39525ad 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1587,6 +1587,28 @@ static int smu_v11_0_update_od8_settings(struct smu_context *smu,
return 0;
}
+static int smu_v11_0_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+{
+ if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))
+ return 0;
+
+ if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))
+ return 0;
+
+ return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);
+}
+
+static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
+{
+ if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))
+ return 0;
+
+ if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT))
+ return 0;
+
+ return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -1632,6 +1654,9 @@ static const struct smu_funcs smu_v11_0_funcs = {
.get_power_profile_mode = smu_v11_0_get_power_profile_mode,
.set_power_profile_mode = smu_v11_0_set_power_profile_mode,
.update_od8_settings = smu_v11_0_update_od8_settings,
+ .dpm_set_uvd_enable = smu_v11_0_dpm_set_uvd_enable,
+ .dpm_set_vce_enable = smu_v11_0_dpm_set_vce_enable,
+
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 135/138] drm/amd/powerplay: implement sensor of uvd & vce power state for smu11
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (133 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 134/138] drm/amd/powerplay: implement uvd & vce dpm enable functions Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 136/138] drm/amd/powerplay: implement dpm enable functions of uvd & vce for smu Huang Rui
` (3 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <kevin1.wang@amd.com>
add functions of uvd & vce for hwmon.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 39525ad..b6ba7f5 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1116,6 +1116,14 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_UVD_POWER:
+ *(uint32_t *)data = smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT) ? 1 : 0;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_VCE_POWER:
+ *(uint32_t *)data = smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT) ? 1 : 0;
+ *size = 4;
+ break;
default:
ret = smu_common_read_sensor(smu, sensor, data, size);
break;
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 136/138] drm/amd/powerplay: implement dpm enable functions of uvd & vce for smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (134 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 135/138] drm/amd/powerplay: implement sensor of uvd & vce power state for smu11 Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 137/138] drm/amd/powerplay: Unify smu handle task function Huang Rui
` (2 subsequent siblings)
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <kevin1.wang@amd.com>
add function of dpm enable uvd & vce for extern module use.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 16 ++++++++++++++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +-
3 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 7b6be5a..97027b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2347,7 +2347,13 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
{
- if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+ int ret = 0;
+ if (is_support_sw_smu(adev)) {
+ ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
+ if (ret)
+ DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
+ enable ? "true" : "false", ret);
+ } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
/* enable/disable UVD */
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
@@ -2368,7 +2374,13 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
{
- if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+ int ret = 0;
+ if (is_support_sw_smu(adev)) {
+ ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
+ if (ret)
+ DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
+ enable ? "true" : "false", ret);
+ } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
/* enable/disable VCE */
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9262d98..b4db490 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,24 @@
#include "smu_v11_0.h"
#include "atom.h"
+int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate)
+{
+ int ret = 0;
+
+ switch (block_type) {
+ case AMD_IP_BLOCK_TYPE_UVD:
+ ret = smu_dpm_set_uvd_enable(smu, gate);
+ break;
+ case AMD_IP_BLOCK_TYPE_VCE:
+ ret = smu_dpm_set_vce_enable(smu, gate);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
{
/* not support power state */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ebde63d..f1b136e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -697,5 +697,5 @@ extern int smu_display_configuration_change(struct smu_context *smu, const
*display_config);
extern int smu_get_current_clocks(struct smu_context *smu,
struct amd_pp_clock_info *clocks);
-
+extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
#endif
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 137/138] drm/amd/powerplay: Unify smu handle task function
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (135 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 136/138] drm/amd/powerplay: implement dpm enable functions of uvd & vce for smu Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-01-25 10:25 ` [PATCH 138/138] drm/amd/powerplay: enable amdgpu dpm for smu Huang Rui
2019-02-20 12:51 ` [PATCH 000/138] The new SW SMU driver of amdgpu Huang, Ray
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Likun Gao <Likun.Gao@amd.com>
Unify power stade adjust function into smu_handle_task by the judgment
of task_id.
Move functions which have no relationship with smu version into the file
of amdgpu_smu.
Modified the function of smu_display_config_changed into two part.
Unify some similiar function.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 46 +++--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 127 ++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 31 +++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 258 ++++++-------------------
4 files changed, 250 insertions(+), 212 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 97027b4..c37264b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2608,28 +2608,38 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
amdgpu_fence_wait_empty(ring);
}
- if (adev->powerplay.pp_funcs->dispatch_tasks) {
- if (!amdgpu_device_has_dc_support(adev)) {
+ if (is_support_sw_smu(adev)) {
+ struct smu_context *smu = &adev->smu;
+ struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
+ mutex_lock(&(smu->mutex));
+ smu_handle_task(&adev->smu,
+ smu_dpm->dpm_level,
+ AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
+ mutex_unlock(&(smu->mutex));
+ } else {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ if (!amdgpu_device_has_dc_support(adev)) {
+ mutex_lock(&adev->pm.mutex);
+ amdgpu_dpm_get_active_displays(adev);
+ adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
+ adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
+ adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
+ /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
+ if (adev->pm.pm_display_cfg.vrefresh > 120)
+ adev->pm.pm_display_cfg.min_vblank_time = 0;
+ if (adev->powerplay.pp_funcs->display_configuration_change)
+ adev->powerplay.pp_funcs->display_configuration_change(
+ adev->powerplay.pp_handle,
+ &adev->pm.pm_display_cfg);
+ mutex_unlock(&adev->pm.mutex);
+ }
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
+ } else {
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_get_active_displays(adev);
- adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
- adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
- adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
- /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
- if (adev->pm.pm_display_cfg.vrefresh > 120)
- adev->pm.pm_display_cfg.min_vblank_time = 0;
- if (adev->powerplay.pp_funcs->display_configuration_change)
- adev->powerplay.pp_funcs->display_configuration_change(
- adev->powerplay.pp_handle,
- &adev->pm.pm_display_cfg);
+ amdgpu_dpm_change_power_state_locked(adev);
mutex_unlock(&adev->pm.mutex);
}
- amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
- } else {
- mutex_lock(&adev->pm.mutex);
- amdgpu_dpm_get_active_displays(adev);
- amdgpu_dpm_change_power_state_locked(adev);
- mutex_unlock(&adev->pm.mutex);
}
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b4db490..5c9c7e1 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1040,6 +1040,133 @@ static int smu_enable_umd_pstate(void *handle,
return 0;
}
+int smu_unforce_dpm_levels(struct smu_context *smu)
+{
+ int ret = 0;
+
+ ret = smu_upload_dpm_level(smu, false);
+ if (ret) {
+ pr_err("Failed to upload DPM Bootup Levels!");
+ return ret;
+ }
+
+ ret = smu_upload_dpm_level(smu, true);
+ if (ret) {
+ pr_err("Failed to upload DPM Max Levels!");
+ return ret;
+ }
+
+ return ret;
+}
+
+int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ bool skip_display_settings)
+{
+ int ret = 0;
+ int index = 0;
+ uint32_t sclk_mask, mclk_mask, soc_mask;
+ long workload;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+
+ if (!skip_display_settings) {
+ ret = smu_display_config_changed(smu);
+ if (ret) {
+ pr_err("Failed to change display config!");
+ return ret;
+ }
+ }
+
+ ret = smu_apply_clocks_adjust_rules(smu);
+ if (ret) {
+ pr_err("Failed to apply clocks adjust rules!");
+ return ret;
+ }
+
+ if (!skip_display_settings) {
+ ret = smu_notify_smc_dispaly_config(smu);
+ if (ret) {
+ pr_err("Failed to notify smc display config!");
+ return ret;
+ }
+ }
+
+ if (smu_dpm_ctx->dpm_level != level) {
+ switch (level) {
+ case AMD_DPM_FORCED_LEVEL_HIGH:
+ ret = smu_force_dpm_limit_value(smu, true);
+ break;
+ case AMD_DPM_FORCED_LEVEL_LOW:
+ ret = smu_force_dpm_limit_value(smu, false);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_AUTO:
+ ret = smu_unforce_dpm_levels(smu);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ ret = smu_get_profiling_clk_mask(smu, level,
+ &sclk_mask,
+ &mclk_mask,
+ &soc_mask);
+ if (ret)
+ return ret;
+ smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
+ smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
+ break;
+
+ case AMD_DPM_FORCED_LEVEL_MANUAL:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ default:
+ break;
+ }
+
+ if (!ret)
+ smu_dpm_ctx->dpm_level = level;
+ }
+
+ if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+ index = fls(smu->workload_mask);
+ index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
+ workload = smu->workload_setting[index];
+
+ if (smu->power_profile_mode != workload)
+ smu_set_power_profile_mode(smu, &workload, 0);
+ }
+
+ return ret;
+}
+
+int smu_handle_task(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum amd_pp_task task_id)
+{
+ int ret = 0;
+
+ switch (task_id) {
+ case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
+ ret = smu_pre_display_config_changed(smu);
+ if (ret)
+ return ret;
+ ret = smu_set_cpu_power_state(smu);
+ if (ret)
+ return ret;
+ ret = smu_adjust_power_state_dynamic(smu, level, false);
+ break;
+ case AMD_PP_TASK_COMPLETE_INIT:
+ case AMD_PP_TASK_READJUST_POWER_STATE:
+ ret = smu_adjust_power_state_dynamic(smu, level, true);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index f1b136e..62e4ed8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -437,6 +437,18 @@ struct pptable_funcs {
int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
enum amd_dpm_forced_level (*get_performance_level)(struct smu_context *smu);
int (*force_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
+ int (*pre_display_config_changed)(struct smu_context *smu);
+ int (*display_config_changed)(struct smu_context *smu);
+ int (*apply_clocks_adjust_rules)(struct smu_context *smu);
+ int (*notify_smc_dispaly_config)(struct smu_context *smu);
+ int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
+ int (*upload_dpm_level)(struct smu_context *smu, bool max);
+ int (*get_profiling_clk_mask)(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ uint32_t *sclk_mask,
+ uint32_t *mclk_mask,
+ uint32_t *soc_mask);
+ int (*set_cpu_power_state)(struct smu_context *smu);
};
struct smu_funcs
@@ -628,6 +640,22 @@ struct smu_funcs
((smu)->ppt_funcs->get_performance_level ? (smu)->ppt_funcs->get_performance_level((smu)) : 0)
#define smu_force_performance_level(smu, level) \
((smu)->ppt_funcs->force_performance_level ? (smu)->ppt_funcs->force_performance_level((smu), (level)) : 0)
+#define smu_pre_display_config_changed(smu) \
+ ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+#define smu_display_config_changed(smu) \
+ ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
+#define smu_apply_clocks_adjust_rules(smu) \
+ ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
+#define smu_notify_smc_dispaly_config(smu) \
+ ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
+#define smu_force_dpm_limit_value(smu, highest) \
+ ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
+#define smu_upload_dpm_level(smu, max) \
+ ((smu)->ppt_funcs->upload_dpm_level ? (smu)->ppt_funcs->upload_dpm_level((smu), (max)) : 0)
+#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
+ ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
+#define smu_set_cpu_power_state(smu) \
+ ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
@@ -698,4 +726,7 @@ extern int smu_display_configuration_change(struct smu_context *smu, const
extern int smu_get_current_clocks(struct smu_context *smu,
struct amd_pp_clock_info *clocks);
extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
+extern int smu_handle_task(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum amd_pp_task task_id);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 32b1ffc..0222e41 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -877,71 +877,39 @@ static int vega20_print_clk_levels(struct smu_context *smu,
return size;
}
-static int vega20_upload_dpm_min_level(struct smu_context *smu)
+static int vega20_upload_dpm_level(struct smu_context *smu, bool max)
{
struct vega20_dpm_table *dpm_table;
struct vega20_single_dpm_table *single_dpm_table;
- uint32_t min_freq;
+ uint32_t freq;
int ret = 0;
dpm_table = smu->smu_dpm.dpm_context;
if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
single_dpm_table = &(dpm_table->gfx_table);
- min_freq = single_dpm_table->dpm_state.soft_min_level;
+ freq = max ? single_dpm_table->dpm_state.soft_max_level :
+ single_dpm_table->dpm_state.soft_min_level;
ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_SetSoftMinByFreq,
- (PPCLK_GFXCLK << 16) | (min_freq & 0xffff));
+ (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
+ (PPCLK_GFXCLK << 16) | (freq & 0xffff));
if (ret) {
- pr_err("Failed to set soft min gfxclk !\n");
+ pr_err("Failed to set soft %s gfxclk !\n",
+ max ? "max" : "min");
return ret;
}
}
if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
single_dpm_table = &(dpm_table->mem_table);
- min_freq = single_dpm_table->dpm_state.soft_min_level;
+ freq = max ? single_dpm_table->dpm_state.soft_max_level :
+ single_dpm_table->dpm_state.soft_min_level;
ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_SetSoftMinByFreq,
- (PPCLK_UCLK << 16) | (min_freq & 0xffff));
+ (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
+ (PPCLK_UCLK << 16) | (freq & 0xffff));
if (ret) {
- pr_err("Failed to set soft min memclk !\n");
- return ret;
- }
- }
-
- return ret;
-}
-
-static int vega20_upload_dpm_max_level(struct smu_context *smu)
-{
- struct vega20_dpm_table *dpm_table;
- struct vega20_single_dpm_table *single_dpm_table;
- uint32_t max_freq;
- int ret = 0;
-
- dpm_table = smu->smu_dpm.dpm_context;
-
- if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
- single_dpm_table = &(dpm_table->gfx_table);
- max_freq = single_dpm_table->dpm_state.soft_max_level;
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_SetSoftMaxByFreq,
- (PPCLK_GFXCLK << 16) | (max_freq & 0xffff));
- if (ret) {
- pr_err("Failed to set soft max gfxclk !\n");
- return ret;
- }
- }
-
- if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
- single_dpm_table = &(dpm_table->mem_table);
- max_freq = single_dpm_table->dpm_state.soft_max_level;
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_SetSoftMaxByFreq,
- (PPCLK_UCLK << 16) | (max_freq & 0xffff));
- if (ret) {
- pr_err("Failed to set soft max memclk !\n");
+ pr_err("Failed to set soft %s memclk !\n",
+ max ? "max" : "min");
return ret;
}
}
@@ -986,13 +954,13 @@ static int vega20_force_clk_levels(struct smu_context *smu,
single_dpm_table->dpm_state.soft_max_level =
single_dpm_table->dpm_levels[soft_max_level].value;
- ret = vega20_upload_dpm_min_level(smu);
+ ret = vega20_upload_dpm_level(smu, false);
if (ret) {
pr_err("Failed to upload boot level to lowest!\n");
break;
}
- ret = vega20_upload_dpm_max_level(smu);
+ ret = vega20_upload_dpm_level(smu, true);
if (ret)
pr_err("Failed to upload dpm max level to highest!\n");
@@ -1013,13 +981,13 @@ static int vega20_force_clk_levels(struct smu_context *smu,
single_dpm_table->dpm_state.soft_max_level =
single_dpm_table->dpm_levels[soft_max_level].value;
- ret = vega20_upload_dpm_min_level(smu);
+ ret = vega20_upload_dpm_level(smu, false);
if (ret) {
pr_err("Failed to upload boot level to lowest!\n");
break;
}
- ret = vega20_upload_dpm_max_level(smu);
+ ret = vega20_upload_dpm_level(smu, true);
if (ret)
pr_err("Failed to upload dpm max level to highest!\n");
@@ -1389,11 +1357,26 @@ vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
return ret;
}
-static int vega20_display_config_changed(struct smu_context *smu)
+static int vega20_pre_display_config_changed(struct smu_context *smu)
{
int ret = 0;
struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
+ if (!smu->smu_dpm.dpm_context)
+ return -EINVAL;
+
+ smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
+ ret = vega20_set_uclk_to_highest_dpm_level(smu,
+ &dpm_table->mem_table);
+ if (ret)
+ pr_err("Failed to set uclk to highest dpm level");
+ return ret;
+}
+
+static int vega20_display_config_changed(struct smu_context *smu)
+{
+ int ret = 0;
+
if (!smu->funcs)
return -EINVAL;
@@ -1402,14 +1385,6 @@ static int vega20_display_config_changed(struct smu_context *smu)
!smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr)
return -EINVAL;
- smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
- ret = vega20_set_uclk_to_highest_dpm_level(smu,
- &dpm_table->mem_table);
- if (ret) {
- pr_err("Failed to set uclk to highest dpm level");
- return ret;
- }
-
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
ret = smu->funcs->write_watermarks_table(smu);
@@ -1672,85 +1647,42 @@ static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *tab
return i;
}
-static int vega20_force_dpm_highest(struct smu_context *smu)
+static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
{
uint32_t soft_level;
int ret = 0;
- struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
+ struct vega20_dpm_table *dpm_table =
+ (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
- soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
+ if (highest)
+ soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
+ else
+ soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
dpm_table->gfx_table.dpm_state.soft_min_level =
dpm_table->gfx_table.dpm_state.soft_max_level =
dpm_table->gfx_table.dpm_levels[soft_level].value;
- soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
+ if (highest)
+ soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
+ else
+ soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
dpm_table->mem_table.dpm_state.soft_min_level =
dpm_table->mem_table.dpm_state.soft_max_level =
dpm_table->mem_table.dpm_levels[soft_level].value;
- ret = vega20_upload_dpm_min_level(smu);
+ ret = vega20_upload_dpm_level(smu, false);
if (ret) {
- pr_err("Failed to upload boot level to highest!");
+ pr_err("Failed to upload boot level to %s!\n",
+ highest ? "highest" : "lowest");
return ret;
}
- ret = vega20_upload_dpm_max_level(smu);
+ ret = vega20_upload_dpm_level(smu, false);
if (ret) {
- pr_err("Failed to upload dpm max level to highest!");
- return ret;
- }
-
- return ret;
-}
-
-static int vega20_force_dpm_lowest(struct smu_context *smu)
-{
- uint32_t soft_level;
- int ret = 0;
- struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
-
- soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
-
- dpm_table->gfx_table.dpm_state.soft_min_level =
- dpm_table->gfx_table.dpm_state.soft_max_level =
- dpm_table->gfx_table.dpm_levels[soft_level].value;
-
- soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
-
- dpm_table->mem_table.dpm_state.soft_min_level =
- dpm_table->mem_table.dpm_state.soft_max_level =
- dpm_table->mem_table.dpm_levels[soft_level].value;
-
- ret = vega20_upload_dpm_min_level(smu);
- if (ret) {
- pr_err("Failed to upload boot level to lowest!");
- return ret;
- }
-
- ret = vega20_upload_dpm_max_level(smu);
- if (ret) {
- pr_err("Failed to upload dpm max level to lowest!");
- return ret;
- }
-
- return ret;
-}
-
-static int vega20_unforce_dpm_levels(struct smu_context *smu)
-{
- int ret = 0;
-
- ret = vega20_upload_dpm_min_level(smu);
- if (ret) {
- pr_err("Failed to upload DPM Bootup Levels!");
- return ret;
- }
-
- ret = vega20_upload_dpm_max_level(smu);
- if (ret) {
- pr_err("Failed to upload DPM Max Levels!");
+ pr_err("Failed to upload dpm max level to %s!\n!",
+ highest ? "highest" : "lowest");
return ret;
}
@@ -1771,78 +1703,6 @@ static enum amd_dpm_forced_level vega20_get_performance_level(struct smu_context
return smu_dpm_ctx->dpm_level;
}
-static int vega20_adjust_power_state_dynamic(struct smu_context *smu,
- enum amd_dpm_forced_level level)
-{
- int ret = 0;
- int index = 0;
- uint32_t sclk_mask, mclk_mask, soc_mask;
- long workload;
- struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
-
- ret = vega20_display_config_changed(smu);
- if (ret) {
- pr_err("Failed to change display config!");
- return ret;
- }
- ret = vega20_apply_clocks_adjust_rules(smu);
- if (ret) {
- pr_err("Failed to apply clocks adjust rules!");
- return ret;
- }
- ret = vega20_notify_smc_dispaly_config(smu);
- if (ret) {
- pr_err("Failed to notify smc display config!");
- return ret;
- }
-
- switch (level) {
- case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = vega20_force_dpm_highest(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_LOW:
- ret = vega20_force_dpm_lowest(smu);
- break;
-
- case AMD_DPM_FORCED_LEVEL_AUTO:
- ret = vega20_unforce_dpm_levels(smu);
- break;
-
- case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
- case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- ret = vega20_get_profiling_clk_mask(smu, level,
- &sclk_mask,
- &mclk_mask,
- &soc_mask);
- if (ret)
- return ret;
- vega20_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
- vega20_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
- break;
-
- case AMD_DPM_FORCED_LEVEL_MANUAL:
- case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
- default:
- break;
- }
-
- if (!ret)
- smu_dpm_ctx->dpm_level = level;
-
- if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
- index = fls(smu->workload_mask);
- index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
- workload = smu->workload_setting[index];
-
- if (smu->power_profile_mode != workload)
- smu->funcs->set_power_profile_mode(smu, &workload, 0);
- }
-
- return ret;
-}
-
static int
vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
{
@@ -1861,7 +1721,8 @@ vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_leve
mutex_lock(&smu->mutex);
smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
- ret = vega20_adjust_power_state_dynamic(smu, level);
+ ret = smu_handle_task(smu, level,
+ AMD_PP_TASK_READJUST_POWER_STATE);
mutex_unlock(&smu->mutex);
@@ -2009,7 +1870,8 @@ static int vega20_set_od_percentage(struct smu_context *smu,
single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
}
- ret = vega20_adjust_power_state_dynamic(smu, smu_dpm->dpm_level);
+ ret = smu_handle_task(smu, smu_dpm->dpm_level,
+ AMD_PP_TASK_READJUST_POWER_STATE);
set_od_failed:
mutex_unlock(&(smu->mutex));
@@ -2239,7 +2101,8 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
if (type == PP_OD_COMMIT_DPM_TABLE) {
mutex_lock(&(smu->mutex));
- ret = vega20_adjust_power_state_dynamic(smu, smu_dpm->dpm_level);
+ ret = smu_handle_task(smu, smu_dpm->dpm_level,
+ AMD_PP_TASK_READJUST_POWER_STATE);
mutex_unlock(&(smu->mutex));
}
@@ -2268,6 +2131,13 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.update_specified_od8_value = vega20_update_specified_od8_value,
.set_od_percentage = vega20_set_od_percentage,
.od_edit_dpm_table = vega20_odn_edit_dpm_table,
+ .pre_display_config_changed = vega20_pre_display_config_changed,
+ .display_config_changed = vega20_display_config_changed,
+ .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
+ .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
+ .force_dpm_limit_value = vega20_force_dpm_limit_value,
+ .upload_dpm_level = vega20_upload_dpm_level,
+ .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
};
void vega20_set_ppt_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 141+ messages in thread* [PATCH 138/138] drm/amd/powerplay: enable amdgpu dpm for smu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (136 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 137/138] drm/amd/powerplay: Unify smu handle task function Huang Rui
@ 2019-01-25 10:25 ` Huang Rui
2019-02-20 12:51 ` [PATCH 000/138] The new SW SMU driver of amdgpu Huang, Ray
138 siblings, 0 replies; 141+ messages in thread
From: Huang Rui @ 2019-01-25 10:25 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Likun Gao, Kevin Wang, Chengming Gui
From: Kevin Wang <kevin1.wang@amd.com>
enable amdgpu dpm global flag
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5c9c7e1..c3176e4 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -734,6 +734,8 @@ static int smu_hw_init(void *handle)
mutex_unlock(&smu->mutex);
+ adev->pm.dpm_enabled = true;
+
pr_info("SMU is initialized successfully!\n");
return 0;
--
2.7.4
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^ permalink raw reply related [flat|nested] 141+ messages in thread* RE: [PATCH 000/138] The new SW SMU driver of amdgpu
[not found] ` <1548411945-12396-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (137 preceding siblings ...)
2019-01-25 10:25 ` [PATCH 138/138] drm/amd/powerplay: enable amdgpu dpm for smu Huang Rui
@ 2019-02-20 12:51 ` Huang, Ray
[not found] ` <MN2PR12MB330957C48B4613D0D35B1AE4EC7D0-rweVpJHSKTpWdvXm18W95QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
138 siblings, 1 reply; 141+ messages in thread
From: Huang, Ray @ 2019-02-20 12:51 UTC (permalink / raw)
To: Huang, Ray,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Deucher, Alexander
Cc: Gao, Likun, Wang, Kevin(Yang), Gui, Jack
Ping.
May I have your comments?
Thanks,
Ray
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Friday, January 25, 2019 6:23 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gao, Likun <Likun.Gao@amd.com>; Wang, Kevin(Yang)
> <Kevin1.Wang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Gui, Jack
> <Jack.Gui@amd.com>
> Subject: [PATCH 000/138] The new SW SMU driver of amdgpu
>
> Hi all,
>
> The series of patches are to implement a new SW SMU driver for future asics.
>
> Background:
> The powerplay driver will be retired. The final version is for vega20 with
> SMU11. However, the future asic will use the new swSMU framework to
> implement as
> well. Here is the first version of new sw smu driver that is basing on vega20.
>
> Purpose:
> We would like to do re-arch for linux power codes to use a new sw SMU ip
> block
> for future asics. We hope to write a simple and readable framework for Linux.
>
> Currently, the default path is still with powerplay on vega20. So far we don’t
> plan to switch default path to new swSMU design for vega20. And we can
> use the
> module parameter amdgpu_dpm to switch it to new SW SMU design
> (modprobe amdgpu
> dpm=1).
>
> Development Items:
> - Setup new SMU IP block skeleton.
> - Implement SMC firmware loading function.
> - Implement SMC table data structure.
> - Implement SMU v11 indirect register (MP1) read/write and SMC message
> sending
> helpers.
> - Implement SMU v11 SMC table initialization (read from vbios, parse,
> populate,
> and write back to smc).
> - Implement SMU v11 memory pool location function.
> - Enable DPM feature for SMU v11 and implement DPM control callback
> function.
> - Enable interfaces for starting tools.
> - Implement SMU v11 power control and power containment functions.
> - Implement and enable SMU v11 thermal/fan control function.
> - Implement SMU interfaces placeholder for DC, VCN, and KFD driver.
> - Enable and align sys interface in the amdgpu_pm.c.
>
> So far, Kevin, Likun, Jack, and I have enabled features such as dpm, od,
> thermal, and etc. with new sw smu driver. (Thanks to Kevin, Likun and Jack's
> great effort!)
>
> Any comments are warm for us.
>
> Thanks & Best Regards!
> Ray
>
>
> Chengming Gui (14):
> drm/amd/powerplay: implement power_dpm_state sys interface for
> SMU11
> drm/amd/powerplay: add watermarks related data structs and function
> for SMU11.
> drm/amd/powerplay: implement pp_power_profile_mode sys inerface for
> SMU11
> drm/amd/powerplay: add display_config to handle display config for
> SMU11.
> drm/amd/powerplay: add mclk_latency_table struct and smu_clocks struct
> for SMU11
> drm/amd/powerplay: add enable_umd_pstate functions for SMU11
> drm/amd/powerplay: add get_profiling_clk_mask functions for SMU11
> drm/amd/powerplay: add set_uclk_to_highest_level for SMU11
> drm/amd/powerplay: add display_config_changed for SMU11.
> drm/amd/powerplay: add apply_clock_adjust_rules for SMU11.
> drm/amd/powerplay: add vega20_notify_smc_display_config functions for
> SMU11
> drm/amd/powerplay: add vega20_find/force_higest/lowest_dpm for
> SMU11
> drm/amd/powerplay: add vega20_unforce_dpm_levels for SMU11.
> drm/amd/powerplay: implement power_dpm_force_performance_level
> for
> SMU11
>
> Huang Rui (53):
> drm/amd/powerplay: add new smu ip block
> drm/amd/powerplay: add smu11 sub block for SMU IP
> drm/amd/powerplay: add firmware loading interface
> drm/amd/powerplay: add fw load checking interface
> drm/amd/powerplay: add interface to read pptable from vbios
> drm/amd/powerplay: add placeholder of smu_initialize_pptable
> drm/amd/powerplay: add interface to init smc tables (v2)
> drm/amd/powerplay: add interface to init power (v2)
> drm/amd/powerplay: add interface to get vbios bootup values (v2)
> drm/amd/powerplay: add interface to check pptable (v2)
> drm/amd/powerplay: add interface to init fb allocations (v2)
> drm/amd/powerplay: add interface to parse pptable (v2)
> drm/amd/powerplay: add interface to populate smc pptable (v2)
> drm/amd/powerplay: add interface to check fw version (v2)
> drm/amd/powerplay: add interface to write pptable (v2)
> drm/amd/powerplay: add interface to set min dcef deep sleep (v2)
> drm/amd/powerplay: add interface to set tool table location (v2)
> drm/amd/powerplay: add interface to allocate memory pool (v2)
> drm/amd/powerplay: add interface to notify memory pool location (v2)
> drm/amd/powerplay: add interfaces for smu resume
> drm/amd/powerplay: add resume sequence placeholder for smu ip block
> drm/amdgpu: enable new smu ip block for vega20
> drm/amd/powerplay: add new ppsmc header for smu11 (v2)
> drm/amd/powerplay: add pptable header for smu11
> drm/amdgpu: update atomfirmware header for smu11
> drm/amdgpu: update new members in atomfirmware
> drm/amd/powerplay: add smu table context structure
> drm/amd/powerplay: add get atom data table helper
> drm/amdgpu: move get_index_into_master_table macro into
> atomfirmware
> header
> drm/amd/powerplay: implement read_pptable_from_vbios function for
> smu11
> drm/amd/powerplay: update pptable header for smu11
> drm/amd/powerplay: add data structure of bootup values
> drm/amd/powerplay: implement get_vbios_bootup_values function for
> smu11 (v2)
> drm/amd/powerplay: implement get_clk_info_from_vbios function for
> smu11 (v2)
> drm/amd/powerplay: add vega20 pptable function file
> drm/amd/powerplay: add append_powerplay_table function
> drm/amd/powerplay: add get_max_sustainable_clock function
> drm/amd/powerplay: add the function to set deep sleep dcefclk
> drm/amd/powerplay: add two interfaces to set_active_display_count and
> store_cc6_data
> drm/amd/powerplay: add smu display configuration change function
> drm/amd/powerplay: add get_clock_by_type interface for display
> drm/amd/powerplay: add interface to get max high clocks for display
> drm/amd/powerplay: add interface to get clock by type with latency for
> display (v2)
> drm/amd/powerplay: add interface to get clock by type with voltage for
> display
> drm/amd/powerplay: add interface to request display clock voltage
> drm/amd/powerplay: add interface to get dal power level
> drm/amd/powerplay: add interface to get performance level
> drm/amd/powerplay: add interface to get current shallow sleep clocks
> drm/amd/powerplay: add interface to get current clocks for display
> drm/amd/powerplay: add interface to notify smu enable pme restore
> register
> drm/amd/powerplay: implement interface to set watermarks for clock
> ranges
> drm/amd/powerplay: remove unnecessary checking in smu_hw_fini
> drm/amd/powerplay: don't check hwmgr while using the sw smu
>
> Kevin Wang (38):
> drm/amd/powerplay: implement smu send message functions for smu11
> (v3)
> drm/amd/powerplay: implement check_fw_status function for smu11
> drm/amd/powerplay: implement check_fw_version function for smu11
> drm/amd/powerplay: implement smu_init[fini]_smc_tables for smu11
> drm/amd/powerplay: implement smu dpm context functions for smu11
> drm/amd/powerplay: implement smu_init[fini]_power function for smu11
> drm/amd/powerplay: implement smu_init(fini)_fb_allocations function
> drm/amd/powerplay: remove header of smu_v11_0_pptable
> drm/amd/powerplay: implement smu_alloc[free]_memory pool function
> drm/amd/powerplay: implement notify_memory_pool_location function
> for
> smu11
> drm/amd/powerplay: add enum smu_msg_type to header
> drm/amd/powerplay: implement smu vega20_message_map for vega20
> drm/amd/powerplay: use virtual msg index to replace asic-related msg
> index
> drm/amd/powerplay: replace SMU_MSG_XXX with PPSMC_MSG_XXX
> message
> index for smu11 (v2)
> drm/amd/powerplay: implement smu_init_display for smu11
> drm/amd/powerplay: implement smu_run_afll_btc function
> drm/amd/powerplay: implement smu feature functions
> drm/amd/powerplay: implement feature get&set functions
> drm/amd/powerplay: implement smu_notify_display_change function for
> smu11
> drm/amd/powerplay: implement get_current_clk_freq for smu11
> drm/amd/powerplay: implement smu update table function
> drm/amd/powerplay: implement is_support_sw_smu function for new smu
> drm/amd/powerplay: implement sysfs of amdgpu_get_busy_percent for
> smu11
> drm/amd/powerplay: implement sysfs of pp_table for smu11
> drm/amd/powerplay: implement sensor of SCLK and MCLK for smu11
> drm/amd/powerplay: implement sensor of thermal_get_temperature for
> smu11
> drm/amd/powerplay: implement sensor of get_gpu_power for smu11
> drm/amd/powerplay: implement sensor of get_gfx_vdd for smu11
> drm/amd/powerplay: implement sensor of get feature mask
> drm/amd/powerplay: implement sysfs of get num states function
> drm/amd/powerplay: implement sysfs of pp_cur_state function
> drm/amd/powerplay: implement sysfs of pp_force_state for sw-smu
> drm/amd/powerplay: implement update enabled feature state to smc for
> smu11
> drm/amd/powerplay: hwmon don't check powerplay when sw smu is
> enabled
> drm/amd/powerplay: implement uvd & vce dpm enable functions
> drm/amd/powerplay: implement sensor of uvd & vce power state for
> smu11
> drm/amd/powerplay: implement dpm enable functions of uvd & vce for
> smu
> drm/amd/powerplay: enable amdgpu dpm for smu
>
> Likun Gao (33):
> drm/amd/powerplay: init microcode for smu11
> drm/amd/powerplay: add function to parse pptable for smu11
> drm/amd/powerplay: add function to check pptable for smu11
> drm/amd/powerplay: update hw fini function to relase some memory
> drm/amd/powerplay: add function to populate smc pptable for smu11
> drm/amd/powerplay: add function to write pptable for smu11 (v2)
> drm/amd/powerplay: add function to set min dcef deep sleep for smu11
> (v2)
> drm/amd/powerplay: add function to set tool table location for smu11
> (v2)
> drm/amd/powerplay: expose the function of smu read argument
> drm/amd/powerplay: Change the allocate method of dpm context for
> smu11.
> drm/amd/powerplay: set defalut dpm table for smu
> drm/amd/powerplay: add function to populate umd state clk.
> drm/amd/powerplay: add function to get power limit for smu11 (v2)
> drm/amd/powerplay: print clock levels for smu11 (v2)
> drm/amd/powerplay: add function to get thermal range
> drm/amd/powerplay: add function to set thermal range
> drm/amd/powerplay: add function to enable thermal alert
> drm/amd/powerplay: add function to set fan table to control thermal
> drm/amd/powerplay: add function to start thermal control
> drm/amd/powerplay: upload dpm level for smu11
> drm/amd/powerplay: force clock levels for smu11
> drm/amd/powerplay: add function to store overdrive information for
> smu11
> drm/amd/powerplay: add function to set default overdrive settings
> drm/amd/powerplay: add golden dpm table to backup default DPM table
> drm/amd/powerplay: print overdrive percentage information for smu11
> drm/amd/powerplay: get overdrive clock and voltage information
> drm/amd/powerplay: add sys interface for pcie for smu
> drm/amd/powerplay: add function to update overdrive settings
> drm/amd/powerplay: add sys interface for set sclk_od/mclk_od for smu
> drm/amd/powerplay: add sys interface to set pp_od_clk_voltage for smu
> drm/amd/powerplay: adjust power state when set od_clk
> drm/amd/powerplay: dpm clk can be set only when performance level is
> manual
> drm/amd/powerplay: Unify smu handle task function
>
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 7 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 11 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 364 ++--
> drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +-
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 99 +-
> drivers/gpu/drm/amd/include/amd_shared.h | 3 +
> drivers/gpu/drm/amd/include/atomfirmware.h | 44 +-
> drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1198 +++++++++++
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 732 +++++++
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 89 +
> .../gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 128 ++
> .../gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h | 147 ++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1683
> +++++++++++++++
> drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2146
> ++++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/vega20_ppt.h | 129 ++
> 19 files changed, 6624 insertions(+), 185 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> create mode 100644
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> create mode 100644
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/vega20_ppt.h
>
> --
> 2.7.4
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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