From: Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: guchun.chen-5C7GfCeVMHo@public.gmane.org,
tao.zhou1-5C7GfCeVMHo@public.gmane.org,
Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>,
alexander.deucher-5C7GfCeVMHo@public.gmane.org,
dennis.li-5C7GfCeVMHo@public.gmane.org,
hawking.zhang-5C7GfCeVMHo@public.gmane.org
Subject: [PATCH 03/10] drm/amdgpu: clear ras controller status registers when interrupt occurs
Date: Wed, 27 Nov 2019 17:15:23 +0800 [thread overview]
Message-ID: <1574846129-4826-3-git-send-email-le.ma@amd.com> (raw)
In-Reply-To: <1574846129-4826-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
To fix issue that ras controller interrupt cannot be triggered anymore after
one time nbif uncorrectable error. And error count is stored in nbif ras object
for query.
Change-Id: Iba482c169fdff3e9c390072c0289a622a522133c
Signed-off-by: Le Ma <le.ma@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 25231d6..9a3a65a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -52,6 +52,9 @@
#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ void *ras_error_status);
+
static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -314,6 +317,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
{
uint32_t bif_doorbell_intr_cntl;
+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
@@ -324,6 +328,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
RAS_CNTLR_INTERRUPT_CLEAR, 1);
WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
+ /*
+ * clear error status after ras_controller_intr according to
+ * hw team and count ue number for query
+ */
+ nbio_v7_4_query_ras_error_count(adev, &obj->err_data);
+
DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
/* ras_controller_int is dedicated for nbif ras error,
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Le Ma <le.ma@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: guchun.chen@amd.com, tao.zhou1@amd.com, Le Ma <le.ma@amd.com>,
alexander.deucher@amd.com, dennis.li@amd.com,
hawking.zhang@amd.com
Subject: [PATCH 03/10] drm/amdgpu: clear ras controller status registers when interrupt occurs
Date: Wed, 27 Nov 2019 17:15:23 +0800 [thread overview]
Message-ID: <1574846129-4826-3-git-send-email-le.ma@amd.com> (raw)
Message-ID: <20191127091523.NsRXHtshleZvPRYS1jyx2-twqNI_XiVP31tEy6GlzqU@z> (raw)
In-Reply-To: <1574846129-4826-1-git-send-email-le.ma@amd.com>
To fix issue that ras controller interrupt cannot be triggered anymore after
one time nbif uncorrectable error. And error count is stored in nbif ras object
for query.
Change-Id: Iba482c169fdff3e9c390072c0289a622a522133c
Signed-off-by: Le Ma <le.ma@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 25231d6..9a3a65a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -52,6 +52,9 @@
#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ void *ras_error_status);
+
static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -314,6 +317,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
{
uint32_t bif_doorbell_intr_cntl;
+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
@@ -324,6 +328,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
RAS_CNTLR_INTERRUPT_CLEAR, 1);
WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
+ /*
+ * clear error status after ras_controller_intr according to
+ * hw team and count ue number for query
+ */
+ nbio_v7_4_query_ras_error_count(adev, &obj->err_data);
+
DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
/* ras_controller_int is dedicated for nbif ras error,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2019-11-27 9:15 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-27 9:15 [PATCH 01/10] drm/amdgpu: remove ras global recovery handling from ras_controller_int handler Le Ma
2019-11-27 9:15 ` Le Ma
[not found] ` <1574846129-4826-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-11-27 9:15 ` [PATCH 02/10] drm/amdgpu: export amdgpu_ras_find_obj to use externally Le Ma
2019-11-27 9:15 ` Le Ma
2019-11-27 9:15 ` Le Ma [this message]
2019-11-27 9:15 ` [PATCH 03/10] drm/amdgpu: clear ras controller status registers when interrupt occurs Le Ma
2019-11-27 9:15 ` [PATCH 05/10] drm/amdgpu: enable/disable doorbell interrupt in baco entry/exit helper Le Ma
2019-11-27 9:15 ` Le Ma
[not found] ` <1574846129-4826-4-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-11-27 12:04 ` Zhang, Hawking
2019-11-27 12:04 ` Zhang, Hawking
[not found] ` <DM5PR12MB14184CF08E965BAF369F4249FC440-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-27 12:14 ` Ma, Le
2019-11-27 12:14 ` Ma, Le
2019-11-28 6:50 ` Zhou1, Tao
2019-11-28 6:50 ` Zhou1, Tao
2019-11-27 9:15 ` [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgmi/ras case Le Ma
2019-11-27 9:15 ` Le Ma
[not found] ` <1574846129-4826-5-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-11-27 11:28 ` Zhang, Hawking
2019-11-27 11:28 ` Zhang, Hawking
[not found] ` <DM5PR12MB141825CB772FEEF1FD013EDBFC440-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-27 12:35 ` Ma, Le
2019-11-27 12:35 ` Ma, Le
2019-11-27 11:38 ` Zhang, Hawking
2019-11-27 11:38 ` Zhang, Hawking
[not found] ` <DM5PR12MB1418D76FD9E6E7748C2F9997FC440-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-27 14:00 ` Ma, Le
2019-11-27 14:00 ` Ma, Le
2019-11-27 9:15 ` [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI Le Ma
2019-11-27 9:15 ` Le Ma
[not found] ` <1574846129-4826-6-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-11-27 15:46 ` Andrey Grodzovsky
2019-11-27 15:46 ` Andrey Grodzovsky
[not found] ` <c09d7928-f864-3a80-40e2-b6116abe044c-5C7GfCeVMHo@public.gmane.org>
2019-11-28 9:00 ` Ma, Le
2019-11-28 9:00 ` Ma, Le
2019-11-29 16:21 ` Andrey Grodzovsky
2019-12-02 11:42 ` Ma, Le
2019-12-02 22:05 ` Andrey Grodzovsky
[not found] ` <MN2PR12MB42855B198BB4064A0D311845F6420@MN2PR12MB4285.namprd12.prod.outlook.com>
[not found] ` <2c4dd3f3-e2ce-9843-312b-1e5c05a51521@amd.com>
2019-12-04 7:09 ` Ma, Le
2019-12-04 16:05 ` Andrey Grodzovsky
2019-12-05 3:14 ` Ma, Le
2019-12-06 21:50 ` Andrey Grodzovsky
2019-12-09 11:34 ` Ma, Le
2019-12-09 15:52 ` Andrey Grodzovsky
2019-12-10 2:45 ` Ma, Le
2019-12-10 19:55 ` Andrey Grodzovsky
2019-12-11 12:18 ` Ma, Le
2019-12-11 14:04 ` Andrey Grodzovsky
2019-12-09 22:00 ` Andrey Grodzovsky
2019-12-10 3:27 ` Ma, Le
2019-11-27 9:15 ` [PATCH 08/10] drm/amdgpu: support full gpu reset workflow when ras err_event_athub occurs Le Ma
2019-11-27 9:15 ` Le Ma
2019-11-27 9:15 ` [PATCH 09/10] drm/amdgpu: clear err_event_athub flag after reset exit Le Ma
2019-11-27 9:15 ` Le Ma
2019-11-27 9:15 ` [PATCH 10/10] drm/amdgpu: reduce redundant uvd context lost warning message Le Ma
2019-11-27 9:15 ` Le Ma
[not found] ` <1574846129-4826-9-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-11-27 9:49 ` Chen, Guchun
2019-11-27 9:49 ` Chen, Guchun
[not found] ` <BYAPR12MB280648A1C59519AA77B3FCA9F1440-ZGDeBxoHBPk0CuAkIMgl3QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-27 9:54 ` Ma, Le
2019-11-27 9:54 ` Ma, Le
2019-11-28 5:27 ` [PATCH 01/10] drm/amdgpu: remove ras global recovery handling from ras_controller_int handler Zhang, Hawking
2019-11-28 5:27 ` Zhang, Hawking
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