[PATCH v3 0/5] drm/amdgpu/vcn: support dec software ring

[PATCH v3 0/5] drm/amdgpu/vcn: support dec software ring

[James Zhu]

This serials of patches add vcn dec software ring support.

v2: clear compilation warning.
V3: replace module parameter with macro
    refactor dec message functions

James Zhu (5):
  drm/amdgpu/vcn: refactor dec message functions
  drm/amdgpu/vcn: update header to support dec vcn software ring
  drm/amdgpu/vcn: add test for dec vcn software ring
  drm/amdgpu/vcn3.0: add dec software ring vm functions to support
  drm/amdgpu/vcn3.0: add software ring share memory support

 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 151 +++++++++++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  30 +++++++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 136 ++++++++++++++++++++++++++--
 3 files changed, 300 insertions(+), 17 deletions(-)

-- 
2.7.4

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[PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions

[James Zhu]

refactor dec message functions to add dec software ring support.

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7e19a66..32251db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -510,16 +510,16 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 }
 
 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
-			      struct dma_fence **fence)
+					 struct amdgpu_bo **bo)
 {
 	struct amdgpu_device *adev = ring->adev;
-	struct amdgpu_bo *bo = NULL;
 	uint32_t *msg;
 	int r, i;
 
+	*bo = NULL;
 	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 				      AMDGPU_GEM_DOMAIN_VRAM,
-				      &bo, NULL, (void **)&msg);
+				      bo, NULL, (void **)&msg);
 	if (r)
 		return r;
 
@@ -540,20 +540,20 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
 	for (i = 14; i < 1024; ++i)
 		msg[i] = cpu_to_le32(0x0);
 
-	return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+	return 0;
 }
 
 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
-			       struct dma_fence **fence)
+					  struct amdgpu_bo **bo)
 {
 	struct amdgpu_device *adev = ring->adev;
-	struct amdgpu_bo *bo = NULL;
 	uint32_t *msg;
 	int r, i;
 
+	*bo = NULL;
 	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 				      AMDGPU_GEM_DOMAIN_VRAM,
-				      &bo, NULL, (void **)&msg);
+				      bo, NULL, (void **)&msg);
 	if (r)
 		return r;
 
@@ -566,19 +566,27 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
 	for (i = 6; i < 1024; ++i)
 		msg[i] = cpu_to_le32(0x0);
 
-	return amdgpu_vcn_dec_send_msg(ring, bo, fence);
+	return 0;
 }
 
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 {
-	struct dma_fence *fence;
+	struct dma_fence *fence = NULL;
+	struct amdgpu_bo *bo;
 	long r;
 
-	r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
+	r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
+	if (r)
+		goto error;
+
+	r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
+	if (r)
+		goto error;
+	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
 	if (r)
 		goto error;
 
-	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
+	r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
 	if (r)
 		goto error;
 
-- 
2.7.4

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[PATCH v3 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring

[James Zhu]

Add macro, structure and function prototype to
support dec vcn software ring.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 1769115..13aa417 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -44,6 +44,17 @@
 #define VCN_DEC_CMD_PACKET_START	0x0000000a
 #define VCN_DEC_CMD_PACKET_END		0x0000000b
 
+#define VCN_DEC_SW_CMD_NO_OP		0x00000000
+#define VCN_DEC_SW_CMD_END		0x00000001
+#define VCN_DEC_SW_CMD_IB		0x00000002
+#define VCN_DEC_SW_CMD_FENCE		0x00000003
+#define VCN_DEC_SW_CMD_TRAP		0x00000004
+#define VCN_DEC_SW_CMD_IB_AUTO		0x00000005
+#define VCN_DEC_SW_CMD_SEMAPHORE	0x00000006
+#define VCN_DEC_SW_CMD_PREEMPT_FENCE	0x00000009
+#define VCN_DEC_SW_CMD_REG_WRITE	0x0000000b
+#define VCN_DEC_SW_CMD_REG_WAIT		0x0000000c
+
 #define VCN_ENC_CMD_NO_OP		0x00000000
 #define VCN_ENC_CMD_END 		0x00000001
 #define VCN_ENC_CMD_IB			0x00000002
@@ -145,6 +156,10 @@
 	} while (0)
 
 #define AMDGPU_VCN_MULTI_QUEUE_FLAG	(1 << 8)
+#define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)
+
+#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001
+#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
 
 enum fw_queue_mode {
 	FW_QUEUE_RING_RESET = 1,
@@ -236,12 +251,25 @@ struct amdgpu_fw_shared_multi_queue {
 	uint8_t padding[4];
 };
 
+struct amdgpu_fw_shared_sw_ring {
+	uint8_t is_enabled;
+	uint8_t padding[3];
+};
+
 struct amdgpu_fw_shared {
 	uint32_t present_flag_0;
 	uint8_t pad[53];
 	struct amdgpu_fw_shared_multi_queue multi_queue;
+	struct amdgpu_fw_shared_sw_ring sw_ring;
 } __attribute__((__packed__));
 
+struct amdgpu_vcn_decode_buffer {
+	uint32_t valid_buf_flag;
+	uint32_t msg_buffer_address_hi;
+	uint32_t msg_buffer_address_lo;
+	uint32_t pad[30];
+};
+
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
@@ -251,6 +279,8 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
 
 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
+int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
-- 
2.7.4

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[PATCH v3 3/5] drm/amdgpu/vcn: add test for dec vcn software ring

[James Zhu]

Add vcn software ring decode ring test and decode ib test.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 121 ++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 32251db..1c97244 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 	return r;
 }
 
+int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t rptr;
+	unsigned int i;
+	int r;
+
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	r = amdgpu_ring_alloc(ring, 16);
+	if (r)
+		return r;
+
+	rptr = amdgpu_ring_get_rptr(ring);
+
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
+	amdgpu_ring_commit(ring);
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		if (amdgpu_ring_get_rptr(ring) != rptr)
+			break;
+		udelay(1);
+	}
+
+	if (i >= adev->usec_timeout)
+		r = -ETIMEDOUT;
+
+	return r;
+}
+
 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 				   struct amdgpu_bo *bo,
 				   struct dma_fence **fence)
@@ -601,6 +632,96 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 	return r;
 }
 
+static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
+				   struct amdgpu_bo *bo,
+				   struct dma_fence **fence)
+{
+	struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
+	const unsigned int ib_size_dw = 64;
+	struct amdgpu_device *adev = ring->adev;
+	struct dma_fence *f = NULL;
+	struct amdgpu_job *job;
+	struct amdgpu_ib *ib;
+	uint64_t addr;
+	int i, r;
+
+	r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
+				AMDGPU_IB_POOL_DIRECT, &job);
+	if (r)
+		goto err;
+
+	ib = &job->ibs[0];
+	addr = amdgpu_bo_gpu_offset(bo);
+	ib->length_dw = 0;
+
+	ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
+	ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
+	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
+	ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
+	memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
+
+	decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
+	decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
+	decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
+
+	for (i = ib->length_dw; i < ib_size_dw; ++i)
+		ib->ptr[i] = 0x0;
+
+	r = amdgpu_job_submit_direct(job, ring, &f);
+	if (r)
+		goto err_free;
+
+	amdgpu_bo_fence(bo, f, false);
+	amdgpu_bo_unreserve(bo);
+	amdgpu_bo_unref(&bo);
+
+	if (fence)
+		*fence = dma_fence_get(f);
+	dma_fence_put(f);
+
+	return 0;
+
+err_free:
+	amdgpu_job_free(job);
+
+err:
+	amdgpu_bo_unreserve(bo);
+	amdgpu_bo_unref(&bo);
+	return r;
+}
+
+int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+	struct dma_fence *fence = NULL;
+	struct amdgpu_bo *bo;
+	long r;
+
+	r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
+	if (r)
+		goto error;
+
+	r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
+	if (r)
+		goto error;
+	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
+	if (r)
+		goto error;
+
+	r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
+	if (r)
+		goto error;
+
+	r = dma_fence_wait_timeout(fence, false, timeout);
+	if (r == 0)
+		r = -ETIMEDOUT;
+	else if (r > 0)
+		r = 0;
+
+	dma_fence_put(fence);
+error:
+	return r;
+}
+
 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
-- 
2.7.4

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[PATCH v3 4/5] drm/amdgpu/vcn3.0: add dec software ring vm functions to support

[James Zhu]

Add dec software ring vm functions to support.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 101 +++++++++++++++++++++++++++++++++-
 1 file changed, 99 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c5e0a53..a94dce4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -48,6 +48,7 @@
 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x25c
 
 #define VCN_INSTANCES_SIENNA_CICHLID				2
+#define DEC_SW_RING_ENABLED					FALSE
 
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
@@ -1673,6 +1674,98 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 	}
 }
 
+void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+				u64 seq, uint32_t flags)
+{
+	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
+	amdgpu_ring_write(ring, addr);
+	amdgpu_ring_write(ring, upper_32_bits(addr));
+	amdgpu_ring_write(ring, seq);
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
+}
+
+void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
+{
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
+			       struct amdgpu_job *job,
+			       struct amdgpu_ib *ib,
+			       uint32_t flags)
+{
+	uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
+
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
+	amdgpu_ring_write(ring, vmid);
+	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+	amdgpu_ring_write(ring, ib->length_dw);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+				uint32_t val, uint32_t mask)
+{
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
+	amdgpu_ring_write(ring, reg << 2);
+	amdgpu_ring_write(ring, mask);
+	amdgpu_ring_write(ring, val);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
+				uint32_t vmid, uint64_t pd_addr)
+{
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+	uint32_t data0, data1, mask;
+
+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+
+	/* wait for register write */
+	data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
+	data1 = lower_32_bits(pd_addr);
+	mask = 0xffffffff;
+	vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
+}
+
+void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
+{
+	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	reg << 2);
+	amdgpu_ring_write(ring, val);
+}
+
+static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
+	.type = AMDGPU_RING_TYPE_VCN_DEC,
+	.align_mask = 0x3f,
+	.nop = VCN_DEC_SW_CMD_NO_OP,
+	.vmhub = AMDGPU_MMHUB_0,
+	.get_rptr = vcn_v3_0_dec_ring_get_rptr,
+	.get_wptr = vcn_v3_0_dec_ring_get_wptr,
+	.set_wptr = vcn_v3_0_dec_ring_set_wptr,
+	.emit_frame_size =
+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
+		4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
+		5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
+		1, /* vcn_v3_0_dec_sw_ring_insert_end */
+	.emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
+	.emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
+	.emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
+	.emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
+	.test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
+	.test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
+	.insert_nop = amdgpu_ring_insert_nop,
+	.insert_end = vcn_v3_0_dec_sw_ring_insert_end,
+	.pad_ib = amdgpu_ring_generic_pad_ib,
+	.begin_use = amdgpu_vcn_ring_begin_use,
+	.end_use = amdgpu_vcn_ring_end_use,
+	.emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
+	.emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
 	.type = AMDGPU_RING_TYPE_VCN_DEC,
 	.align_mask = 0xf,
@@ -1810,9 +1903,13 @@ static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
 
-		adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
+		if (!DEC_SW_RING_ENABLED)
+			adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
+		else
+			adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
 		adev->vcn.inst[i].ring_dec.me = i;
-		DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
+		DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,
+			  DEC_SW_RING_ENABLED?"(Software Ring)":"");
 	}
 }
 
-- 
2.7.4

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[PATCH v3 5/5] drm/amdgpu/vcn3.0: add software ring share memory support

[James Zhu]

Support software ring share memory with vcn firmware.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 35 +++++++++++++++++++++++++++++++----
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index a94dce4..71e10bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -170,6 +170,7 @@ static int vcn_v3_0_sw_init(void *handle)
 	}
 
 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		volatile struct amdgpu_fw_shared *fw_shared;
 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
 
@@ -234,6 +235,10 @@ static int vcn_v3_0_sw_init(void *handle)
 			if (r)
 				return r;
 		}
+
+		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+		fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG);
+		fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
 	}
 
 	if (amdgpu_sriov_vf(adev)) {
@@ -257,7 +262,17 @@ static int vcn_v3_0_sw_init(void *handle)
 static int vcn_v3_0_sw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	int r;
+	int i, r;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		volatile struct amdgpu_fw_shared *fw_shared;
+
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+		fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+		fw_shared->present_flag_0 = 0;
+		fw_shared->sw_ring.is_enabled = false;
+	}
 
 	if (amdgpu_sriov_vf(adev))
 		amdgpu_virt_free_mm_table(adev);
@@ -467,6 +482,15 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
 		upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
 	WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+
+	/* non-cache window */
+	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
+		lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
+	WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
+		upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
+	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
+	WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
+		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
 }
 
 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
@@ -549,13 +573,16 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
 
 	/* non-cache window */
 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
-			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
-			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+			VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
-			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
+			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
 }
 
 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
-- 
2.7.4

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Re: [PATCH v3 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring

[Luben Tuikov]

On 2020-11-18 11:23, James Zhu wrote:
> Add macro, structure and function prototype to
> support dec vcn software ring.
> 
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 1769115..13aa417 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -44,6 +44,17 @@
>  #define VCN_DEC_CMD_PACKET_START	0x0000000a
>  #define VCN_DEC_CMD_PACKET_END		0x0000000b
>  
> +#define VCN_DEC_SW_CMD_NO_OP		0x00000000
> +#define VCN_DEC_SW_CMD_END		0x00000001
> +#define VCN_DEC_SW_CMD_IB		0x00000002
> +#define VCN_DEC_SW_CMD_FENCE		0x00000003
> +#define VCN_DEC_SW_CMD_TRAP		0x00000004
> +#define VCN_DEC_SW_CMD_IB_AUTO		0x00000005
> +#define VCN_DEC_SW_CMD_SEMAPHORE	0x00000006
> +#define VCN_DEC_SW_CMD_PREEMPT_FENCE	0x00000009
> +#define VCN_DEC_SW_CMD_REG_WRITE	0x0000000b
> +#define VCN_DEC_SW_CMD_REG_WAIT		0x0000000c
> +
>  #define VCN_ENC_CMD_NO_OP		0x00000000
>  #define VCN_ENC_CMD_END 		0x00000001
>  #define VCN_ENC_CMD_IB			0x00000002

Alignment is off for the above macros... perhaps TAB char
was inserted to align the columns instead of just using
a space char?

> @@ -145,6 +156,10 @@
>  	} while (0)
>  
>  #define AMDGPU_VCN_MULTI_QUEUE_FLAG	(1 << 8)
> +#define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)
> +
> +#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001
> +#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001

Here too.

Regards,
Luben

>  
>  enum fw_queue_mode {
>  	FW_QUEUE_RING_RESET = 1,
> @@ -236,12 +251,25 @@ struct amdgpu_fw_shared_multi_queue {
>  	uint8_t padding[4];
>  };
>  
> +struct amdgpu_fw_shared_sw_ring {
> +	uint8_t is_enabled;
> +	uint8_t padding[3];
> +};
> +
>  struct amdgpu_fw_shared {
>  	uint32_t present_flag_0;
>  	uint8_t pad[53];
>  	struct amdgpu_fw_shared_multi_queue multi_queue;
> +	struct amdgpu_fw_shared_sw_ring sw_ring;
>  } __attribute__((__packed__));
>  
> +struct amdgpu_vcn_decode_buffer {
> +	uint32_t valid_buf_flag;
> +	uint32_t msg_buffer_address_hi;
> +	uint32_t msg_buffer_address_lo;
> +	uint32_t pad[30];
> +};
> +
>  int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
>  int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
>  int amdgpu_vcn_suspend(struct amdgpu_device *adev);
> @@ -251,6 +279,8 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
>  
>  int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
>  int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
> +int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
> +int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
>  
>  int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
>  int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
> 

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Re: [PATCH v3 2/5] drm/amdgpu/vcn: update header to support dec vcn software ring

[James Zhu]

On 2020-11-18 11:47 a.m., Luben Tuikov wrote:
> On 2020-11-18 11:23, James Zhu wrote:
>> Add macro, structure and function prototype to
>> support dec vcn software ring.
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> Reviewed-by: Leo Liu <leo.liu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index 1769115..13aa417 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -44,6 +44,17 @@
>>   #define VCN_DEC_CMD_PACKET_START	0x0000000a
>>   #define VCN_DEC_CMD_PACKET_END		0x0000000b
>>   
>> +#define VCN_DEC_SW_CMD_NO_OP		0x00000000
>> +#define VCN_DEC_SW_CMD_END		0x00000001
>> +#define VCN_DEC_SW_CMD_IB		0x00000002
>> +#define VCN_DEC_SW_CMD_FENCE		0x00000003
>> +#define VCN_DEC_SW_CMD_TRAP		0x00000004
>> +#define VCN_DEC_SW_CMD_IB_AUTO		0x00000005
>> +#define VCN_DEC_SW_CMD_SEMAPHORE	0x00000006
>> +#define VCN_DEC_SW_CMD_PREEMPT_FENCE	0x00000009
>> +#define VCN_DEC_SW_CMD_REG_WRITE	0x0000000b
>> +#define VCN_DEC_SW_CMD_REG_WAIT		0x0000000c
>> +
>>   #define VCN_ENC_CMD_NO_OP		0x00000000
>>   #define VCN_ENC_CMD_END 		0x00000001
>>   #define VCN_ENC_CMD_IB			0x00000002
> Alignment is off for the above macros... perhaps TAB char
> was inserted to align the columns instead of just using
> a space char?
> [JZ] all TAB is used here, no space.
>> @@ -145,6 +156,10 @@
>>   	} while (0)
>>   
>>   #define AMDGPU_VCN_MULTI_QUEUE_FLAG	(1 << 8)
>> +#define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)
>> +
>> +#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001
>> +#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
> Here too.
>
> Regards,
> Luben
>
>>   
>>   enum fw_queue_mode {
>>   	FW_QUEUE_RING_RESET = 1,
>> @@ -236,12 +251,25 @@ struct amdgpu_fw_shared_multi_queue {
>>   	uint8_t padding[4];
>>   };
>>   
>> +struct amdgpu_fw_shared_sw_ring {
>> +	uint8_t is_enabled;
>> +	uint8_t padding[3];
>> +};
>> +
>>   struct amdgpu_fw_shared {
>>   	uint32_t present_flag_0;
>>   	uint8_t pad[53];
>>   	struct amdgpu_fw_shared_multi_queue multi_queue;
>> +	struct amdgpu_fw_shared_sw_ring sw_ring;
>>   } __attribute__((__packed__));
>>   
>> +struct amdgpu_vcn_decode_buffer {
>> +	uint32_t valid_buf_flag;
>> +	uint32_t msg_buffer_address_hi;
>> +	uint32_t msg_buffer_address_lo;
>> +	uint32_t pad[30];
>> +};
>> +
>>   int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
>>   int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
>>   int amdgpu_vcn_suspend(struct amdgpu_device *adev);
>> @@ -251,6 +279,8 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
>>   
>>   int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
>>   int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
>> +int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
>> +int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
>>   
>>   int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
>>   int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
>>
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Re: [PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions

[Christian König]

Am 18.11.20 um 17:23 schrieb James Zhu:
> refactor dec message functions to add dec software ring support.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 30 +++++++++++++++++++-----------
>   1 file changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 7e19a66..32251db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -510,16 +510,16 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
>   }
>   
>   static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> -			      struct dma_fence **fence)
> +					 struct amdgpu_bo **bo)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> -	struct amdgpu_bo *bo = NULL;
>   	uint32_t *msg;
>   	int r, i;
>   
> +	*bo = NULL;

This looks unnecessary to me.

>   	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>   				      AMDGPU_GEM_DOMAIN_VRAM,
> -				      &bo, NULL, (void **)&msg);
> +				      bo, NULL, (void **)&msg);
>   	if (r)
>   		return r;
>   
> @@ -540,20 +540,20 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>   	for (i = 14; i < 1024; ++i)
>   		msg[i] = cpu_to_le32(0x0);
>   
> -	return amdgpu_vcn_dec_send_msg(ring, bo, fence);
> +	return 0;
>   }
>   
>   static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> -			       struct dma_fence **fence)
> +					  struct amdgpu_bo **bo)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> -	struct amdgpu_bo *bo = NULL;
>   	uint32_t *msg;
>   	int r, i;
>   
> +	*bo = NULL;

Same here.

Apart from that looks good to me.

With that fixed the patch is Reviewed-by: Christian König 
<christian.koenig@amd.com>

Regards,
Christian.

>   	r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>   				      AMDGPU_GEM_DOMAIN_VRAM,
> -				      &bo, NULL, (void **)&msg);
> +				      bo, NULL, (void **)&msg);
>   	if (r)
>   		return r;
>   
> @@ -566,19 +566,27 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>   	for (i = 6; i < 1024; ++i)
>   		msg[i] = cpu_to_le32(0x0);
>   
> -	return amdgpu_vcn_dec_send_msg(ring, bo, fence);
> +	return 0;
>   }
>   
>   int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>   {
> -	struct dma_fence *fence;
> +	struct dma_fence *fence = NULL;
> +	struct amdgpu_bo *bo;
>   	long r;
>   
> -	r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
> +	r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
> +	if (r)
> +		goto error;
> +
> +	r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
> +	if (r)
> +		goto error;
> +	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
>   	if (r)
>   		goto error;
>   
> -	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
> +	r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
>   	if (r)
>   		goto error;
>   

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Re: [PATCH v3 3/5] drm/amdgpu/vcn: add test for dec vcn software ring

[Christian König]

Am 18.11.20 um 17:23 schrieb James Zhu:
> Add vcn software ring decode ring test and decode ib test.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 121 ++++++++++++++++++++++++++++++++
>   1 file changed, 121 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 32251db..1c97244 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -456,6 +456,37 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
>   	return r;
>   }
>   
> +int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
> +{
> +	struct amdgpu_device *adev = ring->adev;
> +	uint32_t rptr;
> +	unsigned int i;
> +	int r;
> +
> +	if (amdgpu_sriov_vf(adev))
> +		return 0;
> +
> +	r = amdgpu_ring_alloc(ring, 16);
> +	if (r)
> +		return r;
> +
> +	rptr = amdgpu_ring_get_rptr(ring);
> +
> +	amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
> +	amdgpu_ring_commit(ring);
> +
> +	for (i = 0; i < adev->usec_timeout; i++) {
> +		if (amdgpu_ring_get_rptr(ring) != rptr)
> +			break;
> +		udelay(1);
> +	}
> +
> +	if (i >= adev->usec_timeout)
> +		r = -ETIMEDOUT;
> +
> +	return r;
> +}
> +
>   static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
>   				   struct amdgpu_bo *bo,
>   				   struct dma_fence **fence)
> @@ -601,6 +632,96 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>   	return r;
>   }
>   
> +static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
> +				   struct amdgpu_bo *bo,
> +				   struct dma_fence **fence)
> +{
> +	struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
> +	const unsigned int ib_size_dw = 64;
> +	struct amdgpu_device *adev = ring->adev;
> +	struct dma_fence *f = NULL;
> +	struct amdgpu_job *job;
> +	struct amdgpu_ib *ib;
> +	uint64_t addr;
> +	int i, r;
> +
> +	r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
> +				AMDGPU_IB_POOL_DIRECT, &job);
> +	if (r)
> +		goto err;
> +
> +	ib = &job->ibs[0];
> +	addr = amdgpu_bo_gpu_offset(bo);
> +	ib->length_dw = 0;
> +
> +	ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
> +	ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
> +	decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
> +	ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
> +	memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
> +
> +	decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
> +	decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
> +	decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
> +
> +	for (i = ib->length_dw; i < ib_size_dw; ++i)
> +		ib->ptr[i] = 0x0;
> +
> +	r = amdgpu_job_submit_direct(job, ring, &f);
> +	if (r)
> +		goto err_free;
> +
> +	amdgpu_bo_fence(bo, f, false);
> +	amdgpu_bo_unreserve(bo);
> +	amdgpu_bo_unref(&bo);
> +
> +	if (fence)
> +		*fence = dma_fence_get(f);
> +	dma_fence_put(f);
> +
> +	return 0;
> +
> +err_free:
> +	amdgpu_job_free(job);
> +
> +err:
> +	amdgpu_bo_unreserve(bo);
> +	amdgpu_bo_unref(&bo);
> +	return r;
> +}
> +
> +int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> +{
> +	struct dma_fence *fence = NULL;
> +	struct amdgpu_bo *bo;
> +	long r;
> +
> +	r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
> +	if (r)
> +		goto error;
> +
> +	r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
> +	if (r)
> +		goto error;
> +	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
> +	if (r)
> +		goto error;
> +
> +	r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
> +	if (r)
> +		goto error;
> +
> +	r = dma_fence_wait_timeout(fence, false, timeout);
> +	if (r == 0)
> +		r = -ETIMEDOUT;
> +	else if (r > 0)
> +		r = 0;
> +
> +	dma_fence_put(fence);
> +error:
> +	return r;
> +}
> +
>   int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;

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Re: [PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions

[James Zhu]

On 2020-11-19 2:59 a.m., Christian König wrote:
> Am 18.11.20 um 17:23 schrieb James Zhu:
>> refactor dec message functions to add dec software ring support.
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 30 
>> +++++++++++++++++++-----------
>>   1 file changed, 19 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>> index 7e19a66..32251db 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>> @@ -510,16 +510,16 @@ static int amdgpu_vcn_dec_send_msg(struct 
>> amdgpu_ring *ring,
>>   }
>>     static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring 
>> *ring, uint32_t handle,
>> -                  struct dma_fence **fence)
>> +                     struct amdgpu_bo **bo)
>>   {
>>       struct amdgpu_device *adev = ring->adev;
>> -    struct amdgpu_bo *bo = NULL;
>>       uint32_t *msg;
>>       int r, i;
>>   +    *bo = NULL;
>
> This looks unnecessary to me.

Hi Christian,

I saw the code has such initialization before refactor. So  I kept them.

But If I remove this initialization, I will have kernel panic. Did I 
miss any other step.

Thanks!

James

Nov 19 09:39:04 jz-tester kernel: [  123.781336] BUG: kernel NULL 
pointer dereference, address: 000000000000028a
Nov 19 09:39:04 jz-tester kernel: [  123.781412] #PF: supervisor read 
access in kernel mode
Nov 19 09:39:04 jz-tester kernel: [  123.781463] #PF: error_code(0x0000) 
- not-present page
Nov 19 09:39:04 jz-tester kernel: [  123.781514] PGD 0 P4D 0
Nov 19 09:39:04 jz-tester kernel: [  123.781547] Oops: 0000 [#1] SMP PTI
Nov 19 09:39:04 jz-tester kernel: [  123.781586] CPU: 1 PID: 19 Comm: 
kworker/1:0 Tainted: G           OE     5.4.0-39-generic #43-Ubuntu
Nov 19 09:39:04 jz-tester kernel: [  123.781670] Hardware name: MSI 
MS-7971/Z170A PC MATE (MS-7971), BIOS A.D0 12/22/2016
Nov 19 09:39:04 jz-tester kernel: [  123.781922] Workqueue: events 
amdgpu_device_delayed_init_work_handler [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.782156] RIP: 
0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.782219] Code: 00 00 00 00 89 55 
a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 00 00 c6 
45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 49 8b b9 40 
01 00 00 31 f6 4c 89 4d 90 48 89
Nov 19 09:39:04 jz-tester kernel: [  123.782382] RSP: 
0018:ffffb0cc40123d18 EFLAGS: 00010206
Nov 19 09:39:04 jz-tester kernel: [  123.782435] RAX: 0000000000000021 
RBX: ffffb0cc40123de0 RCX: 0000000000000004
Nov 19 09:39:04 jz-tester kernel: [  123.782502] RDX: 0000000000001000 
RSI: 0000000000000400 RDI: ffff9de4d4a80000
Nov 19 09:39:04 jz-tester kernel: [  123.782569] RBP: ffffb0cc40123d98 
R08: ffffb0cc40123de0 R09: 00000000000000fa
Nov 19 09:39:04 jz-tester kernel: [  123.782636] R10: 0000000000000015 
R11: ffff9de50ea699e0 R12: 0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.782702] R13: 0000000000000004 
R14: ffffb0cc40123db0 R15: 0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.782771] FS: 
0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.782846] CS:  0010 DS: 0000 ES: 
0000 CR0: 0000000080050033
Nov 19 09:39:04 jz-tester kernel: [  123.782901] CR2: 000000000000028a 
CR3: 00000007aa00a003 CR4: 00000000003606e0
Nov 19 09:39:04 jz-tester kernel: [  123.782968] DR0: 0000000000000000 
DR1: 0000000000000000 DR2: 0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.783035] DR3: 0000000000000000 
DR6: 00000000fffe0ff0 DR7: 0000000000000400
Nov 19 09:39:04 jz-tester kernel: [  123.783101] Call Trace:
Nov 19 09:39:04 jz-tester kernel: [  123.783138]  ? call_rcu+0x10/0x20
Nov 19 09:39:04 jz-tester kernel: [  123.783391] 
amdgpu_vcn_dec_get_create_msg.isra.0.constprop.0+0x3b/0xd0 [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.783676] 
amdgpu_vcn_dec_ring_test_ib+0x3a/0xf0 [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.783898] 
amdgpu_ib_ring_tests+0xf5/0x160 [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.784094] 
amdgpu_device_delayed_init_work_handler+0x15/0x30 [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.784163] 
process_one_work+0x1eb/0x3b0
Nov 19 09:39:04 jz-tester kernel: [  123.784206] worker_thread+0x4d/0x400
Nov 19 09:39:04 jz-tester kernel: [  123.784248] kthread+0x104/0x140
Nov 19 09:39:04 jz-tester kernel: [  123.784285]  ? 
process_one_work+0x3b0/0x3b0
Nov 19 09:39:04 jz-tester kernel: [  123.784329]  ? kthread_park+0x90/0x90
Nov 19 09:39:04 jz-tester kernel: [  123.784371] ret_from_fork+0x35/0x40
Nov 19 09:39:04 jz-tester kernel: [  123.784411] Modules linked in: 
amdgpu(OE) amd_iommu_v2 amd_sched(OE) amdttm(OE) amdkcl(OE) 
drm_kms_helper i2c_algo_bit fb_sys_fops syscopyarea sysfillrect 
sysimgblt binfmt_misc nls_iso8859_1 intel_rapl_msr intel_rapl_common 
x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel 
snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio 
snd_hda_codec_hdmi kvm snd_hda_intel snd_intel_dspcfg snd_hda_codec 
snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event 
snd_rawmidi crct10dif_pclmul ghash_clmulni_intel snd_seq aesni_intel 
crypto_simd cryptd glue_helper snd_seq_device intel_cstate snd_timer 
intel_rapl_perf input_leds joydev snd serio_raw mxm_wmi soundcore mei_me 
mei intel_pch_thermal mac_hid acpi_pad sch_fq_codel parport_pc ppdev lp 
parport drm ip_tables x_tables autofs4 hid_generic usbhid hid 
crc32_pclmul psmouse r8169 ahci i2c_i801 realtek libahci wmi video
Nov 19 09:39:04 jz-tester kernel: [  123.785115] CR2: 000000000000028a
Nov 19 09:39:04 jz-tester kernel: [  123.785152] ---[ end trace 
58c4ccffcda9e3c8 ]---
Nov 19 09:39:04 jz-tester kernel: [  123.785354] RIP: 
0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
Nov 19 09:39:04 jz-tester kernel: [  123.785416] Code: 00 00 00 00 89 55 
a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 00 00 c6 
45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 49 8b b9 40 
01 00 00 31 f6 4c 89 4d 90 48 89
Nov 19 09:39:04 jz-tester kernel: [  123.785579] RSP: 
0018:ffffb0cc40123d18 EFLAGS: 00010206
Nov 19 09:39:04 jz-tester kernel: [  123.785631] RAX: 0000000000000021 
RBX: ffffb0cc40123de0 RCX: 0000000000000004
Nov 19 09:39:04 jz-tester kernel: [  123.785698] RDX: 0000000000001000 
RSI: 0000000000000400 RDI: ffff9de4d4a80000
Nov 19 09:39:04 jz-tester kernel: [  123.785764] RBP: ffffb0cc40123d98 
R08: ffffb0cc40123de0 R09: 00000000000000fa
Nov 19 09:39:04 jz-tester kernel: [  123.785831] R10: 0000000000000015 
R11: ffff9de50ea699e0 R12: 0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.785898] R13: 0000000000000004 
R14: ffffb0cc40123db0 R15: 0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.785965] FS: 
0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
Nov 19 09:39:04 jz-tester kernel: [  123.786041] CS:  0010 DS: 0000 ES: 
0000 CR0: 0000000080050033
Nov 19 09:39:04 jz-tester kernel: [  123.786096] CR2: 000000000000028a 
CR3: 00000007aa00a003 CR4: 00000000003606e0
Nov 19 09:39:04 jz-tester kernel: [  123.786163] DR0: 0000000000000000 
DR1: 0000000000000000 DR2: 0000000000000000

>
>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>                         AMDGPU_GEM_DOMAIN_VRAM,
>> -                      &bo, NULL, (void **)&msg);
>> +                      bo, NULL, (void **)&msg);
>>       if (r)
>>           return r;
>>   @@ -540,20 +540,20 @@ static int 
>> amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>>       for (i = 14; i < 1024; ++i)
>>           msg[i] = cpu_to_le32(0x0);
>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>> +    return 0;
>>   }
>>     static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring 
>> *ring, uint32_t handle,
>> -                   struct dma_fence **fence)
>> +                      struct amdgpu_bo **bo)
>>   {
>>       struct amdgpu_device *adev = ring->adev;
>> -    struct amdgpu_bo *bo = NULL;
>>       uint32_t *msg;
>>       int r, i;
>>   +    *bo = NULL;
>
> Same here.
>
> Apart from that looks good to me.
>
> With that fixed the patch is Reviewed-by: Christian König 
> <christian.koenig@amd.com>
>
> Regards,
> Christian.
>
>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>                         AMDGPU_GEM_DOMAIN_VRAM,
>> -                      &bo, NULL, (void **)&msg);
>> +                      bo, NULL, (void **)&msg);
>>       if (r)
>>           return r;
>>   @@ -566,19 +566,27 @@ static int 
>> amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>>       for (i = 6; i < 1024; ++i)
>>           msg[i] = cpu_to_le32(0x0);
>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>> +    return 0;
>>   }
>>     int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long 
>> timeout)
>>   {
>> -    struct dma_fence *fence;
>> +    struct dma_fence *fence = NULL;
>> +    struct amdgpu_bo *bo;
>>       long r;
>>   -    r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
>> +    r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
>> +    if (r)
>> +        goto error;
>> +
>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
>> +    if (r)
>> +        goto error;
>> +    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
>>       if (r)
>>           goto error;
>>   -    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
>>       if (r)
>>           goto error;
>
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Re: [PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions

[Christian König]

Am 19.11.20 um 15:52 schrieb James Zhu:
>
> On 2020-11-19 2:59 a.m., Christian König wrote:
>> Am 18.11.20 um 17:23 schrieb James Zhu:
>>> refactor dec message functions to add dec software ring support.
>>>
>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 30 
>>> +++++++++++++++++++-----------
>>>   1 file changed, 19 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> index 7e19a66..32251db 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> @@ -510,16 +510,16 @@ static int amdgpu_vcn_dec_send_msg(struct 
>>> amdgpu_ring *ring,
>>>   }
>>>     static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring 
>>> *ring, uint32_t handle,
>>> -                  struct dma_fence **fence)
>>> +                     struct amdgpu_bo **bo)
>>>   {
>>>       struct amdgpu_device *adev = ring->adev;
>>> -    struct amdgpu_bo *bo = NULL;
>>>       uint32_t *msg;
>>>       int r, i;
>>>   +    *bo = NULL;
>>
>> This looks unnecessary to me.
>
> Hi Christian,
>
> I saw the code has such initialization before refactor. So  I kept them.
>
> But If I remove this initialization, I will have kernel panic. Did I 
> miss any other step.

Ah, yes that's because the allocator thinks there is already a BO.

I thought that this is for error handling. You need to initialize BO to 
zero in the caller and not here.

Regards,
Christian

>
> Thanks!
>
> James
>
> Nov 19 09:39:04 jz-tester kernel: [  123.781336] BUG: kernel NULL 
> pointer dereference, address: 000000000000028a
> Nov 19 09:39:04 jz-tester kernel: [  123.781412] #PF: supervisor read 
> access in kernel mode
> Nov 19 09:39:04 jz-tester kernel: [  123.781463] #PF: 
> error_code(0x0000) - not-present page
> Nov 19 09:39:04 jz-tester kernel: [  123.781514] PGD 0 P4D 0
> Nov 19 09:39:04 jz-tester kernel: [  123.781547] Oops: 0000 [#1] SMP PTI
> Nov 19 09:39:04 jz-tester kernel: [  123.781586] CPU: 1 PID: 19 Comm: 
> kworker/1:0 Tainted: G           OE     5.4.0-39-generic #43-Ubuntu
> Nov 19 09:39:04 jz-tester kernel: [  123.781670] Hardware name: MSI 
> MS-7971/Z170A PC MATE (MS-7971), BIOS A.D0 12/22/2016
> Nov 19 09:39:04 jz-tester kernel: [  123.781922] Workqueue: events 
> amdgpu_device_delayed_init_work_handler [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.782156] RIP: 
> 0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.782219] Code: 00 00 00 00 89 
> 55 a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 00 
> 00 c6 45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 49 8b 
> b9 40 01 00 00 31 f6 4c 89 4d 90 48 89
> Nov 19 09:39:04 jz-tester kernel: [  123.782382] RSP: 
> 0018:ffffb0cc40123d18 EFLAGS: 00010206
> Nov 19 09:39:04 jz-tester kernel: [  123.782435] RAX: 0000000000000021 
> RBX: ffffb0cc40123de0 RCX: 0000000000000004
> Nov 19 09:39:04 jz-tester kernel: [  123.782502] RDX: 0000000000001000 
> RSI: 0000000000000400 RDI: ffff9de4d4a80000
> Nov 19 09:39:04 jz-tester kernel: [  123.782569] RBP: ffffb0cc40123d98 
> R08: ffffb0cc40123de0 R09: 00000000000000fa
> Nov 19 09:39:04 jz-tester kernel: [  123.782636] R10: 0000000000000015 
> R11: ffff9de50ea699e0 R12: 0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.782702] R13: 0000000000000004 
> R14: ffffb0cc40123db0 R15: 0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.782771] FS: 
> 0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.782846] CS:  0010 DS: 0000 
> ES: 0000 CR0: 0000000080050033
> Nov 19 09:39:04 jz-tester kernel: [  123.782901] CR2: 000000000000028a 
> CR3: 00000007aa00a003 CR4: 00000000003606e0
> Nov 19 09:39:04 jz-tester kernel: [  123.782968] DR0: 0000000000000000 
> DR1: 0000000000000000 DR2: 0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.783035] DR3: 0000000000000000 
> DR6: 00000000fffe0ff0 DR7: 0000000000000400
> Nov 19 09:39:04 jz-tester kernel: [  123.783101] Call Trace:
> Nov 19 09:39:04 jz-tester kernel: [  123.783138]  ? call_rcu+0x10/0x20
> Nov 19 09:39:04 jz-tester kernel: [  123.783391] 
> amdgpu_vcn_dec_get_create_msg.isra.0.constprop.0+0x3b/0xd0 [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.783676] 
> amdgpu_vcn_dec_ring_test_ib+0x3a/0xf0 [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.783898] 
> amdgpu_ib_ring_tests+0xf5/0x160 [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.784094] 
> amdgpu_device_delayed_init_work_handler+0x15/0x30 [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.784163] 
> process_one_work+0x1eb/0x3b0
> Nov 19 09:39:04 jz-tester kernel: [  123.784206] worker_thread+0x4d/0x400
> Nov 19 09:39:04 jz-tester kernel: [  123.784248] kthread+0x104/0x140
> Nov 19 09:39:04 jz-tester kernel: [  123.784285]  ? 
> process_one_work+0x3b0/0x3b0
> Nov 19 09:39:04 jz-tester kernel: [  123.784329]  ? 
> kthread_park+0x90/0x90
> Nov 19 09:39:04 jz-tester kernel: [  123.784371] ret_from_fork+0x35/0x40
> Nov 19 09:39:04 jz-tester kernel: [  123.784411] Modules linked in: 
> amdgpu(OE) amd_iommu_v2 amd_sched(OE) amdttm(OE) amdkcl(OE) 
> drm_kms_helper i2c_algo_bit fb_sys_fops syscopyarea sysfillrect 
> sysimgblt binfmt_misc nls_iso8859_1 intel_rapl_msr intel_rapl_common 
> x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel 
> snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio 
> snd_hda_codec_hdmi kvm snd_hda_intel snd_intel_dspcfg snd_hda_codec 
> snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event 
> snd_rawmidi crct10dif_pclmul ghash_clmulni_intel snd_seq aesni_intel 
> crypto_simd cryptd glue_helper snd_seq_device intel_cstate snd_timer 
> intel_rapl_perf input_leds joydev snd serio_raw mxm_wmi soundcore 
> mei_me mei intel_pch_thermal mac_hid acpi_pad sch_fq_codel parport_pc 
> ppdev lp parport drm ip_tables x_tables autofs4 hid_generic usbhid hid 
> crc32_pclmul psmouse r8169 ahci i2c_i801 realtek libahci wmi video
> Nov 19 09:39:04 jz-tester kernel: [  123.785115] CR2: 000000000000028a
> Nov 19 09:39:04 jz-tester kernel: [  123.785152] ---[ end trace 
> 58c4ccffcda9e3c8 ]---
> Nov 19 09:39:04 jz-tester kernel: [  123.785354] RIP: 
> 0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
> Nov 19 09:39:04 jz-tester kernel: [  123.785416] Code: 00 00 00 00 89 
> 55 a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 00 
> 00 c6 45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 49 8b 
> b9 40 01 00 00 31 f6 4c 89 4d 90 48 89
> Nov 19 09:39:04 jz-tester kernel: [  123.785579] RSP: 
> 0018:ffffb0cc40123d18 EFLAGS: 00010206
> Nov 19 09:39:04 jz-tester kernel: [  123.785631] RAX: 0000000000000021 
> RBX: ffffb0cc40123de0 RCX: 0000000000000004
> Nov 19 09:39:04 jz-tester kernel: [  123.785698] RDX: 0000000000001000 
> RSI: 0000000000000400 RDI: ffff9de4d4a80000
> Nov 19 09:39:04 jz-tester kernel: [  123.785764] RBP: ffffb0cc40123d98 
> R08: ffffb0cc40123de0 R09: 00000000000000fa
> Nov 19 09:39:04 jz-tester kernel: [  123.785831] R10: 0000000000000015 
> R11: ffff9de50ea699e0 R12: 0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.785898] R13: 0000000000000004 
> R14: ffffb0cc40123db0 R15: 0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.785965] FS: 
> 0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
> Nov 19 09:39:04 jz-tester kernel: [  123.786041] CS:  0010 DS: 0000 
> ES: 0000 CR0: 0000000080050033
> Nov 19 09:39:04 jz-tester kernel: [  123.786096] CR2: 000000000000028a 
> CR3: 00000007aa00a003 CR4: 00000000003606e0
> Nov 19 09:39:04 jz-tester kernel: [  123.786163] DR0: 0000000000000000 
> DR1: 0000000000000000 DR2: 0000000000000000
>
>>
>>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>>                         AMDGPU_GEM_DOMAIN_VRAM,
>>> -                      &bo, NULL, (void **)&msg);
>>> +                      bo, NULL, (void **)&msg);
>>>       if (r)
>>>           return r;
>>>   @@ -540,20 +540,20 @@ static int 
>>> amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>>>       for (i = 14; i < 1024; ++i)
>>>           msg[i] = cpu_to_le32(0x0);
>>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>>> +    return 0;
>>>   }
>>>     static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring 
>>> *ring, uint32_t handle,
>>> -                   struct dma_fence **fence)
>>> +                      struct amdgpu_bo **bo)
>>>   {
>>>       struct amdgpu_device *adev = ring->adev;
>>> -    struct amdgpu_bo *bo = NULL;
>>>       uint32_t *msg;
>>>       int r, i;
>>>   +    *bo = NULL;
>>
>> Same here.
>>
>> Apart from that looks good to me.
>>
>> With that fixed the patch is Reviewed-by: Christian König 
>> <christian.koenig@amd.com>
>>
>> Regards,
>> Christian.
>>
>>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>>                         AMDGPU_GEM_DOMAIN_VRAM,
>>> -                      &bo, NULL, (void **)&msg);
>>> +                      bo, NULL, (void **)&msg);
>>>       if (r)
>>>           return r;
>>>   @@ -566,19 +566,27 @@ static int 
>>> amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>>>       for (i = 6; i < 1024; ++i)
>>>           msg[i] = cpu_to_le32(0x0);
>>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>>> +    return 0;
>>>   }
>>>     int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long 
>>> timeout)
>>>   {
>>> -    struct dma_fence *fence;
>>> +    struct dma_fence *fence = NULL;
>>> +    struct amdgpu_bo *bo;
>>>       long r;
>>>   -    r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
>>> +    r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
>>> +    if (r)
>>> +        goto error;
>>> +
>>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
>>> +    if (r)
>>> +        goto error;
>>> +    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
>>>       if (r)
>>>           goto error;
>>>   -    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
>>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
>>>       if (r)
>>>           goto error;
>>

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Re: [PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions

[James Zhu]

On 2020-11-19 9:58 a.m., Christian König wrote:
> Am 19.11.20 um 15:52 schrieb James Zhu:
>>
>> On 2020-11-19 2:59 a.m., Christian König wrote:
>>> Am 18.11.20 um 17:23 schrieb James Zhu:
>>>> refactor dec message functions to add dec software ring support.
>>>>
>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 30 
>>>> +++++++++++++++++++-----------
>>>>   1 file changed, 19 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>> index 7e19a66..32251db 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>> @@ -510,16 +510,16 @@ static int amdgpu_vcn_dec_send_msg(struct 
>>>> amdgpu_ring *ring,
>>>>   }
>>>>     static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring 
>>>> *ring, uint32_t handle,
>>>> -                  struct dma_fence **fence)
>>>> +                     struct amdgpu_bo **bo)
>>>>   {
>>>>       struct amdgpu_device *adev = ring->adev;
>>>> -    struct amdgpu_bo *bo = NULL;
>>>>       uint32_t *msg;
>>>>       int r, i;
>>>>   +    *bo = NULL;
>>>
>>> This looks unnecessary to me.
>>
>> Hi Christian,
>>
>> I saw the code has such initialization before refactor. So  I kept them.
>>
>> But If I remove this initialization, I will have kernel panic. Did I 
>> miss any other step.
>
> Ah, yes that's because the allocator thinks there is already a BO.
>
> I thought that this is for error handling. You need to initialize BO 
> to zero in the caller and not here.

[JZ] Since this BO reference point is shared between create/destroy 
messages, so it needs initialization

before bo create separately. So is it better to keep the initialization 
inside each functions?

Best Regars!

James

>
> Regards,
> Christian
>
>>
>> Thanks!
>>
>> James
>>
>> Nov 19 09:39:04 jz-tester kernel: [  123.781336] BUG: kernel NULL 
>> pointer dereference, address: 000000000000028a
>> Nov 19 09:39:04 jz-tester kernel: [  123.781412] #PF: supervisor read 
>> access in kernel mode
>> Nov 19 09:39:04 jz-tester kernel: [  123.781463] #PF: 
>> error_code(0x0000) - not-present page
>> Nov 19 09:39:04 jz-tester kernel: [  123.781514] PGD 0 P4D 0
>> Nov 19 09:39:04 jz-tester kernel: [  123.781547] Oops: 0000 [#1] SMP PTI
>> Nov 19 09:39:04 jz-tester kernel: [  123.781586] CPU: 1 PID: 19 Comm: 
>> kworker/1:0 Tainted: G           OE     5.4.0-39-generic #43-Ubuntu
>> Nov 19 09:39:04 jz-tester kernel: [  123.781670] Hardware name: MSI 
>> MS-7971/Z170A PC MATE (MS-7971), BIOS A.D0 12/22/2016
>> Nov 19 09:39:04 jz-tester kernel: [  123.781922] Workqueue: events 
>> amdgpu_device_delayed_init_work_handler [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.782156] RIP: 
>> 0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.782219] Code: 00 00 00 00 89 
>> 55 a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 00 
>> 00 c6 45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 49 
>> 8b b9 40 01 00 00 31 f6 4c 89 4d 90 48 89
>> Nov 19 09:39:04 jz-tester kernel: [  123.782382] RSP: 
>> 0018:ffffb0cc40123d18 EFLAGS: 00010206
>> Nov 19 09:39:04 jz-tester kernel: [  123.782435] RAX: 
>> 0000000000000021 RBX: ffffb0cc40123de0 RCX: 0000000000000004
>> Nov 19 09:39:04 jz-tester kernel: [  123.782502] RDX: 
>> 0000000000001000 RSI: 0000000000000400 RDI: ffff9de4d4a80000
>> Nov 19 09:39:04 jz-tester kernel: [  123.782569] RBP: 
>> ffffb0cc40123d98 R08: ffffb0cc40123de0 R09: 00000000000000fa
>> Nov 19 09:39:04 jz-tester kernel: [  123.782636] R10: 
>> 0000000000000015 R11: ffff9de50ea699e0 R12: 0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.782702] R13: 
>> 0000000000000004 R14: ffffb0cc40123db0 R15: 0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.782771] FS: 
>> 0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.782846] CS:  0010 DS: 0000 
>> ES: 0000 CR0: 0000000080050033
>> Nov 19 09:39:04 jz-tester kernel: [  123.782901] CR2: 
>> 000000000000028a CR3: 00000007aa00a003 CR4: 00000000003606e0
>> Nov 19 09:39:04 jz-tester kernel: [  123.782968] DR0: 
>> 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.783035] DR3: 
>> 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>> Nov 19 09:39:04 jz-tester kernel: [  123.783101] Call Trace:
>> Nov 19 09:39:04 jz-tester kernel: [  123.783138]  ? call_rcu+0x10/0x20
>> Nov 19 09:39:04 jz-tester kernel: [  123.783391] 
>> amdgpu_vcn_dec_get_create_msg.isra.0.constprop.0+0x3b/0xd0 [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.783676] 
>> amdgpu_vcn_dec_ring_test_ib+0x3a/0xf0 [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.783898] 
>> amdgpu_ib_ring_tests+0xf5/0x160 [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.784094] 
>> amdgpu_device_delayed_init_work_handler+0x15/0x30 [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.784163] 
>> process_one_work+0x1eb/0x3b0
>> Nov 19 09:39:04 jz-tester kernel: [  123.784206] 
>> worker_thread+0x4d/0x400
>> Nov 19 09:39:04 jz-tester kernel: [  123.784248] kthread+0x104/0x140
>> Nov 19 09:39:04 jz-tester kernel: [  123.784285]  ? 
>> process_one_work+0x3b0/0x3b0
>> Nov 19 09:39:04 jz-tester kernel: [  123.784329]  ? 
>> kthread_park+0x90/0x90
>> Nov 19 09:39:04 jz-tester kernel: [  123.784371] ret_from_fork+0x35/0x40
>> Nov 19 09:39:04 jz-tester kernel: [  123.784411] Modules linked in: 
>> amdgpu(OE) amd_iommu_v2 amd_sched(OE) amdttm(OE) amdkcl(OE) 
>> drm_kms_helper i2c_algo_bit fb_sys_fops syscopyarea sysfillrect 
>> sysimgblt binfmt_misc nls_iso8859_1 intel_rapl_msr intel_rapl_common 
>> x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel 
>> snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio 
>> snd_hda_codec_hdmi kvm snd_hda_intel snd_intel_dspcfg snd_hda_codec 
>> snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event 
>> snd_rawmidi crct10dif_pclmul ghash_clmulni_intel snd_seq aesni_intel 
>> crypto_simd cryptd glue_helper snd_seq_device intel_cstate snd_timer 
>> intel_rapl_perf input_leds joydev snd serio_raw mxm_wmi soundcore 
>> mei_me mei intel_pch_thermal mac_hid acpi_pad sch_fq_codel parport_pc 
>> ppdev lp parport drm ip_tables x_tables autofs4 hid_generic usbhid 
>> hid crc32_pclmul psmouse r8169 ahci i2c_i801 realtek libahci wmi video
>> Nov 19 09:39:04 jz-tester kernel: [  123.785115] CR2: 000000000000028a
>> Nov 19 09:39:04 jz-tester kernel: [  123.785152] ---[ end trace 
>> 58c4ccffcda9e3c8 ]---
>> Nov 19 09:39:04 jz-tester kernel: [  123.785354] RIP: 
>> 0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
>> Nov 19 09:39:04 jz-tester kernel: [  123.785416] Code: 00 00 00 00 89 
>> 55 a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 00 
>> 00 c6 45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 49 
>> 8b b9 40 01 00 00 31 f6 4c 89 4d 90 48 89
>> Nov 19 09:39:04 jz-tester kernel: [  123.785579] RSP: 
>> 0018:ffffb0cc40123d18 EFLAGS: 00010206
>> Nov 19 09:39:04 jz-tester kernel: [  123.785631] RAX: 
>> 0000000000000021 RBX: ffffb0cc40123de0 RCX: 0000000000000004
>> Nov 19 09:39:04 jz-tester kernel: [  123.785698] RDX: 
>> 0000000000001000 RSI: 0000000000000400 RDI: ffff9de4d4a80000
>> Nov 19 09:39:04 jz-tester kernel: [  123.785764] RBP: 
>> ffffb0cc40123d98 R08: ffffb0cc40123de0 R09: 00000000000000fa
>> Nov 19 09:39:04 jz-tester kernel: [  123.785831] R10: 
>> 0000000000000015 R11: ffff9de50ea699e0 R12: 0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.785898] R13: 
>> 0000000000000004 R14: ffffb0cc40123db0 R15: 0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.785965] FS: 
>> 0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
>> Nov 19 09:39:04 jz-tester kernel: [  123.786041] CS:  0010 DS: 0000 
>> ES: 0000 CR0: 0000000080050033
>> Nov 19 09:39:04 jz-tester kernel: [  123.786096] CR2: 
>> 000000000000028a CR3: 00000007aa00a003 CR4: 00000000003606e0
>> Nov 19 09:39:04 jz-tester kernel: [  123.786163] DR0: 
>> 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>>
>>>
>>>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>>>                         AMDGPU_GEM_DOMAIN_VRAM,
>>>> -                      &bo, NULL, (void **)&msg);
>>>> +                      bo, NULL, (void **)&msg);
>>>>       if (r)
>>>>           return r;
>>>>   @@ -540,20 +540,20 @@ static int 
>>>> amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>>>>       for (i = 14; i < 1024; ++i)
>>>>           msg[i] = cpu_to_le32(0x0);
>>>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>>>> +    return 0;
>>>>   }
>>>>     static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring 
>>>> *ring, uint32_t handle,
>>>> -                   struct dma_fence **fence)
>>>> +                      struct amdgpu_bo **bo)
>>>>   {
>>>>       struct amdgpu_device *adev = ring->adev;
>>>> -    struct amdgpu_bo *bo = NULL;
>>>>       uint32_t *msg;
>>>>       int r, i;
>>>>   +    *bo = NULL;
>>>
>>> Same here.
>>>
>>> Apart from that looks good to me.
>>>
>>> With that fixed the patch is Reviewed-by: Christian König 
>>> <christian.koenig@amd.com>
>>>
>>> Regards,
>>> Christian.
>>>
>>>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>>>                         AMDGPU_GEM_DOMAIN_VRAM,
>>>> -                      &bo, NULL, (void **)&msg);
>>>> +                      bo, NULL, (void **)&msg);
>>>>       if (r)
>>>>           return r;
>>>>   @@ -566,19 +566,27 @@ static int 
>>>> amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>>>>       for (i = 6; i < 1024; ++i)
>>>>           msg[i] = cpu_to_le32(0x0);
>>>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>>>> +    return 0;
>>>>   }
>>>>     int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long 
>>>> timeout)
>>>>   {
>>>> -    struct dma_fence *fence;
>>>> +    struct dma_fence *fence = NULL;
>>>> +    struct amdgpu_bo *bo;
>>>>       long r;
>>>>   -    r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
>>>> +    r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
>>>> +    if (r)
>>>> +        goto error;
>>>> +
>>>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
>>>> +    if (r)
>>>> +        goto error;
>>>> +    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
>>>>       if (r)
>>>>           goto error;
>>>>   -    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
>>>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
>>>>       if (r)
>>>>           goto error;
>>>
>
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Re: [PATCH v3 1/5] drm/amdgpu/vcn: refactor dec message functions

[Christian König]

Am 19.11.20 um 16:37 schrieb James Zhu:
>
> On 2020-11-19 9:58 a.m., Christian König wrote:
>> Am 19.11.20 um 15:52 schrieb James Zhu:
>>>
>>> On 2020-11-19 2:59 a.m., Christian König wrote:
>>>> Am 18.11.20 um 17:23 schrieb James Zhu:
>>>>> refactor dec message functions to add dec software ring support.
>>>>>
>>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>>> ---
>>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 30 
>>>>> +++++++++++++++++++-----------
>>>>>   1 file changed, 19 insertions(+), 11 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>>> index 7e19a66..32251db 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>>> @@ -510,16 +510,16 @@ static int amdgpu_vcn_dec_send_msg(struct 
>>>>> amdgpu_ring *ring,
>>>>>   }
>>>>>     static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring 
>>>>> *ring, uint32_t handle,
>>>>> -                  struct dma_fence **fence)
>>>>> +                     struct amdgpu_bo **bo)
>>>>>   {
>>>>>       struct amdgpu_device *adev = ring->adev;
>>>>> -    struct amdgpu_bo *bo = NULL;
>>>>>       uint32_t *msg;
>>>>>       int r, i;
>>>>>   +    *bo = NULL;
>>>>
>>>> This looks unnecessary to me.
>>>
>>> Hi Christian,
>>>
>>> I saw the code has such initialization before refactor. So  I kept 
>>> them.
>>>
>>> But If I remove this initialization, I will have kernel panic. Did I 
>>> miss any other step.
>>
>> Ah, yes that's because the allocator thinks there is already a BO.
>>
>> I thought that this is for error handling. You need to initialize BO 
>> to zero in the caller and not here.
>
> [JZ] Since this BO reference point is shared between create/destroy 
> messages, so it needs initialization
>
> before bo create separately. So is it better to keep the 
> initialization inside each functions?

Ok, good point. Feel free to add my rb as it is.

Thanks,
Christian.

>
> Best Regars!
>
> James
>
>>
>> Regards,
>> Christian
>>
>>>
>>> Thanks!
>>>
>>> James
>>>
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781336] BUG: kernel NULL 
>>> pointer dereference, address: 000000000000028a
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781412] #PF: supervisor 
>>> read access in kernel mode
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781463] #PF: 
>>> error_code(0x0000) - not-present page
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781514] PGD 0 P4D 0
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781547] Oops: 0000 [#1] SMP 
>>> PTI
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781586] CPU: 1 PID: 19 
>>> Comm: kworker/1:0 Tainted: G           OE 5.4.0-39-generic #43-Ubuntu
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781670] Hardware name: MSI 
>>> MS-7971/Z170A PC MATE (MS-7971), BIOS A.D0 12/22/2016
>>> Nov 19 09:39:04 jz-tester kernel: [  123.781922] Workqueue: events 
>>> amdgpu_device_delayed_init_work_handler [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782156] RIP: 
>>> 0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782219] Code: 00 00 00 00 
>>> 89 55 a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 
>>> 00 00 c6 45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 
>>> 49 8b b9 40 01 00 00 31 f6 4c 89 4d 90 48 89
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782382] RSP: 
>>> 0018:ffffb0cc40123d18 EFLAGS: 00010206
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782435] RAX: 
>>> 0000000000000021 RBX: ffffb0cc40123de0 RCX: 0000000000000004
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782502] RDX: 
>>> 0000000000001000 RSI: 0000000000000400 RDI: ffff9de4d4a80000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782569] RBP: 
>>> ffffb0cc40123d98 R08: ffffb0cc40123de0 R09: 00000000000000fa
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782636] R10: 
>>> 0000000000000015 R11: ffff9de50ea699e0 R12: 0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782702] R13: 
>>> 0000000000000004 R14: ffffb0cc40123db0 R15: 0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782771] FS: 
>>> 0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782846] CS:  0010 DS: 0000 
>>> ES: 0000 CR0: 0000000080050033
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782901] CR2: 
>>> 000000000000028a CR3: 00000007aa00a003 CR4: 00000000003606e0
>>> Nov 19 09:39:04 jz-tester kernel: [  123.782968] DR0: 
>>> 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.783035] DR3: 
>>> 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>>> Nov 19 09:39:04 jz-tester kernel: [  123.783101] Call Trace:
>>> Nov 19 09:39:04 jz-tester kernel: [  123.783138]  ? call_rcu+0x10/0x20
>>> Nov 19 09:39:04 jz-tester kernel: [  123.783391] 
>>> amdgpu_vcn_dec_get_create_msg.isra.0.constprop.0+0x3b/0xd0 [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.783676] 
>>> amdgpu_vcn_dec_ring_test_ib+0x3a/0xf0 [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.783898] 
>>> amdgpu_ib_ring_tests+0xf5/0x160 [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784094] 
>>> amdgpu_device_delayed_init_work_handler+0x15/0x30 [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784163] 
>>> process_one_work+0x1eb/0x3b0
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784206] 
>>> worker_thread+0x4d/0x400
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784248] kthread+0x104/0x140
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784285]  ? 
>>> process_one_work+0x3b0/0x3b0
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784329]  ? 
>>> kthread_park+0x90/0x90
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784371] 
>>> ret_from_fork+0x35/0x40
>>> Nov 19 09:39:04 jz-tester kernel: [  123.784411] Modules linked in: 
>>> amdgpu(OE) amd_iommu_v2 amd_sched(OE) amdttm(OE) amdkcl(OE) 
>>> drm_kms_helper i2c_algo_bit fb_sys_fops syscopyarea sysfillrect 
>>> sysimgblt binfmt_misc nls_iso8859_1 intel_rapl_msr intel_rapl_common 
>>> x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel 
>>> snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio 
>>> snd_hda_codec_hdmi kvm snd_hda_intel snd_intel_dspcfg snd_hda_codec 
>>> snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event 
>>> snd_rawmidi crct10dif_pclmul ghash_clmulni_intel snd_seq aesni_intel 
>>> crypto_simd cryptd glue_helper snd_seq_device intel_cstate snd_timer 
>>> intel_rapl_perf input_leds joydev snd serio_raw mxm_wmi soundcore 
>>> mei_me mei intel_pch_thermal mac_hid acpi_pad sch_fq_codel 
>>> parport_pc ppdev lp parport drm ip_tables x_tables autofs4 
>>> hid_generic usbhid hid crc32_pclmul psmouse r8169 ahci i2c_i801 
>>> realtek libahci wmi video
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785115] CR2: 000000000000028a
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785152] ---[ end trace 
>>> 58c4ccffcda9e3c8 ]---
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785354] RIP: 
>>> 0010:amdgpu_bo_create_reserved+0xc1/0x1c0 [amdgpu]
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785416] Code: 00 00 00 00 
>>> 89 55 a8 89 4d ac 48 89 45 b8 c7 45 c0 01 00 00 00 48 c7 45 c8 00 00 
>>> 00 00 c6 45 8f 00 4d 85 c9 0f 84 98 00 00 00 <49> 8b 81 90 01 00 00 
>>> 49 8b b9 40 01 00 00 31 f6 4c 89 4d 90 48 89
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785579] RSP: 
>>> 0018:ffffb0cc40123d18 EFLAGS: 00010206
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785631] RAX: 
>>> 0000000000000021 RBX: ffffb0cc40123de0 RCX: 0000000000000004
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785698] RDX: 
>>> 0000000000001000 RSI: 0000000000000400 RDI: ffff9de4d4a80000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785764] RBP: 
>>> ffffb0cc40123d98 R08: ffffb0cc40123de0 R09: 00000000000000fa
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785831] R10: 
>>> 0000000000000015 R11: ffff9de50ea699e0 R12: 0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785898] R13: 
>>> 0000000000000004 R14: ffffb0cc40123db0 R15: 0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.785965] FS: 
>>> 0000000000000000(0000) GS:ffff9de50ea40000(0000) knlGS:0000000000000000
>>> Nov 19 09:39:04 jz-tester kernel: [  123.786041] CS:  0010 DS: 0000 
>>> ES: 0000 CR0: 0000000080050033
>>> Nov 19 09:39:04 jz-tester kernel: [  123.786096] CR2: 
>>> 000000000000028a CR3: 00000007aa00a003 CR4: 00000000003606e0
>>> Nov 19 09:39:04 jz-tester kernel: [  123.786163] DR0: 
>>> 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>>>
>>>>
>>>>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>>>>                         AMDGPU_GEM_DOMAIN_VRAM,
>>>>> -                      &bo, NULL, (void **)&msg);
>>>>> +                      bo, NULL, (void **)&msg);
>>>>>       if (r)
>>>>>           return r;
>>>>>   @@ -540,20 +540,20 @@ static int 
>>>>> amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>>>>>       for (i = 14; i < 1024; ++i)
>>>>>           msg[i] = cpu_to_le32(0x0);
>>>>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>>>>> +    return 0;
>>>>>   }
>>>>>     static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring 
>>>>> *ring, uint32_t handle,
>>>>> -                   struct dma_fence **fence)
>>>>> +                      struct amdgpu_bo **bo)
>>>>>   {
>>>>>       struct amdgpu_device *adev = ring->adev;
>>>>> -    struct amdgpu_bo *bo = NULL;
>>>>>       uint32_t *msg;
>>>>>       int r, i;
>>>>>   +    *bo = NULL;
>>>>
>>>> Same here.
>>>>
>>>> Apart from that looks good to me.
>>>>
>>>> With that fixed the patch is Reviewed-by: Christian König 
>>>> <christian.koenig@amd.com>
>>>>
>>>> Regards,
>>>> Christian.
>>>>
>>>>>       r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>>>>>                         AMDGPU_GEM_DOMAIN_VRAM,
>>>>> -                      &bo, NULL, (void **)&msg);
>>>>> +                      bo, NULL, (void **)&msg);
>>>>>       if (r)
>>>>>           return r;
>>>>>   @@ -566,19 +566,27 @@ static int 
>>>>> amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>>>>>       for (i = 6; i < 1024; ++i)
>>>>>           msg[i] = cpu_to_le32(0x0);
>>>>>   -    return amdgpu_vcn_dec_send_msg(ring, bo, fence);
>>>>> +    return 0;
>>>>>   }
>>>>>     int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long 
>>>>> timeout)
>>>>>   {
>>>>> -    struct dma_fence *fence;
>>>>> +    struct dma_fence *fence = NULL;
>>>>> +    struct amdgpu_bo *bo;
>>>>>       long r;
>>>>>   -    r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
>>>>> +    r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
>>>>> +    if (r)
>>>>> +        goto error;
>>>>> +
>>>>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
>>>>> +    if (r)
>>>>> +        goto error;
>>>>> +    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
>>>>>       if (r)
>>>>>           goto error;
>>>>>   -    r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
>>>>> +    r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
>>>>>       if (r)
>>>>>           goto error;
>>>>
>>

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