[PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

[PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---

Changes from V2 -> V3:
- add mutex to protect the is_powergated flag.

---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 +++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 +++++++++++++++++++++++++++++++++--
 3 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 530549b..afb3ded 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1183,6 +1183,8 @@ struct amdgpu_uvd {
 	bool			use_ctx_buf;
 	struct amd_sched_entity entity;
 	uint32_t                srbm_soft_reset;
+	bool			is_powergated;
+	struct mutex		pg_mutex;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 03a35d9..bf797b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void *handle,
 	 * the smc and the hw blocks
 	 */
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int ret = 0;
 
 	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
 		return 0;
 
+	mutex_lock(&adev->uvd.pg_mutex);
+
 	if (state == AMD_PG_STATE_GATE) {
+		adev->uvd.is_powergated = true;
 		uvd_v5_0_stop(adev);
-		return 0;
 	} else {
-		return uvd_v5_0_start(adev);
+		ret = uvd_v5_0_start(adev);
+		if (ret)
+			goto out;
+		adev->uvd.is_powergated = false;
+	}
+
+out:
+	mutex_unlock(&adev->uvd.pg_mutex);
+
+	return ret;
+}
+
+static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	mutex_lock(&adev->uvd.pg_mutex);
+
+	if (adev->uvd.is_powergated) {
+		DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
+		goto out;
 	}
+
+	/* AMD_CG_SUPPORT_UVD_MGCG */
+	data = RREG32(mmUVD_CGC_CTRL);
+	if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+		*flags |= AMD_CG_SUPPORT_UVD_MGCG;
+
+out:
+	mutex_unlock(&adev->uvd.pg_mutex);
 }
 
 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
@@ -808,6 +840,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 	.soft_reset = uvd_v5_0_soft_reset,
 	.set_clockgating_state = uvd_v5_0_set_clockgating_state,
 	.set_powergating_state = uvd_v5_0_set_powergating_state,
+	.get_clockgating_state = uvd_v5_0_get_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8779d4b..0ec692d 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void *handle,
 	 * the smc and the hw blocks
 	 */
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int ret = 0;
 
 	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
 		return 0;
 
 	WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
 
+	mutex_lock(&adev->uvd.pg_mutex);
+
 	if (state == AMD_PG_STATE_GATE) {
+		adev->uvd.is_powergated = true;
 		uvd_v6_0_stop(adev);
-		return 0;
 	} else {
-		return uvd_v6_0_start(adev);
+		ret = uvd_v6_0_start(adev);
+		if (ret)
+			goto out;
+		adev->uvd.is_powergated = false;
+	}
+
+out:
+	mutex_unlock(&adev->uvd.pg_mutex);
+
+	return ret;
+}
+
+static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	mutex_lock(&adev->uvd.pg_mutex);
+
+	if (adev->uvd.is_powergated) {
+		DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
+		goto out;
 	}
+
+	/* AMD_CG_SUPPORT_UVD_MGCG */
+	data = RREG32(mmUVD_CGC_CTRL);
+	if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+		*flags |= AMD_CG_SUPPORT_UVD_MGCG;
+
+out:
+	mutex_unlock(&adev->uvd.pg_mutex);
 }
 
 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
@@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 	.post_soft_reset = uvd_v6_0_post_soft_reset,
 	.set_clockgating_state = uvd_v6_0_set_clockgating_state,
 	.set_powergating_state = uvd_v6_0_set_powergating_state,
+	.get_clockgating_state = uvd_v6_0_get_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
-- 
2.7.4

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[PART1 PATCH v3 8/8] drm/amdgpu: add get clockgating_state method for vce v3

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---

Changes from V2 -> V3:
- use mutex to protect the is_powergated flag.

---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 44 +++++++++++++++++++++++++++++++----
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index afb3ded..5d31e4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1213,6 +1213,7 @@ struct amdgpu_vce {
 	struct amd_sched_entity	entity;
 	uint32_t                srbm_soft_reset;
 	unsigned		num_rings;
+	bool			is_powergated;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 35ff1c3..dbd8e87 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -770,15 +770,50 @@ static int vce_v3_0_set_powergating_state(void *handle,
 	 * the smc and the hw blocks
 	 */
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int ret = 0;
 
 	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
 		return 0;
 
-	if (state == AMD_PG_STATE_GATE)
+	mutex_lock(&adev->grbm_idx_mutex);
+
+	if (state == AMD_PG_STATE_GATE) {
+		adev->vce.is_powergated = true;
 		/* XXX do we need a vce_v3_0_stop()? */
-		return 0;
-	else
-		return vce_v3_0_start(adev);
+	} else {
+		ret = vce_v3_0_start(adev);
+		if (ret)
+			goto out;
+		adev->vce.is_powergated = false;
+	}
+
+out:
+	mutex_unlock(&adev->grbm_idx_mutex);
+
+	return ret;
+}
+
+static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int data;
+
+	mutex_lock(&adev->grbm_idx_mutex);
+
+	if (adev->vce.is_powergated) {
+		DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
+		goto out;
+	}
+
+	WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
+
+	/* AMD_CG_SUPPORT_VCE_MGCG */
+	data = RREG32(mmVCE_CLOCK_GATING_A);
+	if (data & (0x04 << 4))
+		*flags |= AMD_CG_SUPPORT_VCE_MGCG;
+
+out:
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 
 static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
@@ -832,6 +867,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
 	.post_soft_reset = vce_v3_0_post_soft_reset,
 	.set_clockgating_state = vce_v3_0_set_clockgating_state,
 	.set_powergating_state = vce_v3_0_set_powergating_state,
+	.get_clockgating_state = vce_v3_0_get_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
-- 
2.7.4

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Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

[Christian König]

Am 06.01.2017 um 11:51 schrieb Huang Rui:
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>
> Changes from V2 -> V3:
> - add mutex to protect the is_powergated flag.
>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 +++++++++++++++++++++++++++++++++--
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 +++++++++++++++++++++++++++++++++--
>   3 files changed, 72 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 530549b..afb3ded 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1183,6 +1183,8 @@ struct amdgpu_uvd {
>   	bool			use_ctx_buf;
>   	struct amd_sched_entity entity;
>   	uint32_t                srbm_soft_reset;
> +	bool			is_powergated;
> +	struct mutex		pg_mutex;

You are missing a mutex_init for pg_mutex, probably best to put this 
into amdgpu_uvd_sw_init().

Apart from that the patch looks good to me now.

Regards,
Christian.

>   };
>   
>   /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 03a35d9..bf797b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void *handle,
>   	 * the smc and the hw blocks
>   	 */
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +	int ret = 0;
>   
>   	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
>   		return 0;
>   
> +	mutex_lock(&adev->uvd.pg_mutex);
> +
>   	if (state == AMD_PG_STATE_GATE) {
> +		adev->uvd.is_powergated = true;
>   		uvd_v5_0_stop(adev);
> -		return 0;
>   	} else {
> -		return uvd_v5_0_start(adev);
> +		ret = uvd_v5_0_start(adev);
> +		if (ret)
> +			goto out;
> +		adev->uvd.is_powergated = false;
> +	}
> +
> +out:
> +	mutex_unlock(&adev->uvd.pg_mutex);
> +
> +	return ret;
> +}
> +
> +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> +	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +	int data;
> +
> +	mutex_lock(&adev->uvd.pg_mutex);
> +
> +	if (adev->uvd.is_powergated) {
> +		DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> +		goto out;
>   	}
> +
> +	/* AMD_CG_SUPPORT_UVD_MGCG */
> +	data = RREG32(mmUVD_CGC_CTRL);
> +	if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> +		*flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> +	mutex_unlock(&adev->uvd.pg_mutex);
>   }
>   
>   static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> @@ -808,6 +840,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
>   	.soft_reset = uvd_v5_0_soft_reset,
>   	.set_clockgating_state = uvd_v5_0_set_clockgating_state,
>   	.set_powergating_state = uvd_v5_0_set_powergating_state,
> +	.get_clockgating_state = uvd_v5_0_get_clockgating_state,
>   };
>   
>   static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 8779d4b..0ec692d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void *handle,
>   	 * the smc and the hw blocks
>   	 */
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +	int ret = 0;
>   
>   	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
>   		return 0;
>   
>   	WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
>   
> +	mutex_lock(&adev->uvd.pg_mutex);
> +
>   	if (state == AMD_PG_STATE_GATE) {
> +		adev->uvd.is_powergated = true;
>   		uvd_v6_0_stop(adev);
> -		return 0;
>   	} else {
> -		return uvd_v6_0_start(adev);
> +		ret = uvd_v6_0_start(adev);
> +		if (ret)
> +			goto out;
> +		adev->uvd.is_powergated = false;
> +	}
> +
> +out:
> +	mutex_unlock(&adev->uvd.pg_mutex);
> +
> +	return ret;
> +}
> +
> +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> +	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +	int data;
> +
> +	mutex_lock(&adev->uvd.pg_mutex);
> +
> +	if (adev->uvd.is_powergated) {
> +		DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> +		goto out;
>   	}
> +
> +	/* AMD_CG_SUPPORT_UVD_MGCG */
> +	data = RREG32(mmUVD_CGC_CTRL);
> +	if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> +		*flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> +	mutex_unlock(&adev->uvd.pg_mutex);
>   }
>   
>   static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> @@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
>   	.post_soft_reset = uvd_v6_0_post_soft_reset,
>   	.set_clockgating_state = uvd_v6_0_set_clockgating_state,
>   	.set_powergating_state = uvd_v6_0_set_powergating_state,
> +	.get_clockgating_state = uvd_v6_0_get_clockgating_state,
>   };
>   
>   static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {


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Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 6708 bytes --]

There's already the adev->pm.mutex which is held while gating/ungating blocks.  There's no need for a second mutex right?


Tom


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, January 6, 2017 07:52
To: Huang, Ray; Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Kuehling, Felix; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David
Subject: Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

Am 06.01.2017 um 11:51 schrieb Huang Rui:
> Signed-off-by: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
> ---
>
> Changes from V2 -> V3:
> - add mutex to protect the is_powergated flag.
>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 +++++++++++++++++++++++++++++++++--
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 +++++++++++++++++++++++++++++++++--
>   3 files changed, 72 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 530549b..afb3ded 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1183,6 +1183,8 @@ struct amdgpu_uvd {
>        bool                    use_ctx_buf;
>        struct amd_sched_entity entity;
>        uint32_t                srbm_soft_reset;
> +     bool                    is_powergated;
> +     struct mutex            pg_mutex;

You are missing a mutex_init for pg_mutex, probably best to put this
into amdgpu_uvd_sw_init().

Apart from that the patch looks good to me now.

Regards,
Christian.

>   };
>
>   /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 03a35d9..bf797b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void *handle,
>         * the smc and the hw blocks
>         */
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int ret = 0;
>
>        if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
>                return 0;
>
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
>        if (state == AMD_PG_STATE_GATE) {
> +             adev->uvd.is_powergated = true;
>                uvd_v5_0_stop(adev);
> -             return 0;
>        } else {
> -             return uvd_v5_0_start(adev);
> +             ret = uvd_v5_0_start(adev);
> +             if (ret)
> +                     goto out;
> +             adev->uvd.is_powergated = false;
> +     }
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
> +
> +     return ret;
> +}
> +
> +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> +     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int data;
> +
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
> +     if (adev->uvd.is_powergated) {
> +             DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> +             goto out;
>        }
> +
> +     /* AMD_CG_SUPPORT_UVD_MGCG */
> +     data = RREG32(mmUVD_CGC_CTRL);
> +     if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> +             *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
>   }
>
>   static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> @@ -808,6 +840,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
>        .soft_reset = uvd_v5_0_soft_reset,
>        .set_clockgating_state = uvd_v5_0_set_clockgating_state,
>        .set_powergating_state = uvd_v5_0_set_powergating_state,
> +     .get_clockgating_state = uvd_v5_0_get_clockgating_state,
>   };
>
>   static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 8779d4b..0ec692d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void *handle,
>         * the smc and the hw blocks
>         */
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int ret = 0;
>
>        if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
>                return 0;
>
>        WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
>
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
>        if (state == AMD_PG_STATE_GATE) {
> +             adev->uvd.is_powergated = true;
>                uvd_v6_0_stop(adev);
> -             return 0;
>        } else {
> -             return uvd_v6_0_start(adev);
> +             ret = uvd_v6_0_start(adev);
> +             if (ret)
> +                     goto out;
> +             adev->uvd.is_powergated = false;
> +     }
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
> +
> +     return ret;
> +}
> +
> +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> +     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int data;
> +
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
> +     if (adev->uvd.is_powergated) {
> +             DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> +             goto out;
>        }
> +
> +     /* AMD_CG_SUPPORT_UVD_MGCG */
> +     data = RREG32(mmUVD_CGC_CTRL);
> +     if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> +             *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
>   }
>
>   static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> @@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
>        .post_soft_reset = uvd_v6_0_post_soft_reset,
>        .set_clockgating_state = uvd_v6_0_set_clockgating_state,
>        .set_powergating_state = uvd_v6_0_set_powergating_state,
> +     .get_clockgating_state = uvd_v6_0_get_clockgating_state,
>   };
>
>   static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {


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Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

[Christian König]

[-- Attachment #1.1: Type: text/plain, Size: 7139 bytes --]

Good point, I wasn't ware that the pm mutex still existed and is taken 
under all code flows.

Christian.

Am 06.01.2017 um 14:42 schrieb StDenis, Tom:
>
> There's already the adev->pm.mutex which is held while gating/ungating 
> blocks.  There's no need for a second mutex right?
>
>
> Tom
>
>
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of 
> Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Friday, January 6, 2017 07:52
> *To:* Huang, Ray; Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Cc:* Kuehling, Felix; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David
> *Subject:* Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get 
> clockgating_state method for uvd v5&v6
> Am 06.01.2017 um 11:51 schrieb Huang Rui:
> > Signed-off-by: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
> > ---
> >
> > Changes from V2 -> V3:
> > - add mutex to protect the is_powergated flag.
> >
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
> >   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 
> +++++++++++++++++++++++++++++++++--
> >   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 
> +++++++++++++++++++++++++++++++++--
> >   3 files changed, 72 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 530549b..afb3ded 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1183,6 +1183,8 @@ struct amdgpu_uvd {
> >        bool                    use_ctx_buf;
> >        struct amd_sched_entity entity;
> >        uint32_t                srbm_soft_reset;
> > +     bool                    is_powergated;
> > +     struct mutex            pg_mutex;
>
> You are missing a mutex_init for pg_mutex, probably best to put this
> into amdgpu_uvd_sw_init().
>
> Apart from that the patch looks good to me now.
>
> Regards,
> Christian.
>
> >   };
> >
> >   /*
> > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> > index 03a35d9..bf797b8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> > @@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void 
> *handle,
> >         * the smc and the hw blocks
> >         */
> >        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > +     int ret = 0;
> >
> >        if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
> >                return 0;
> >
> > +     mutex_lock(&adev->uvd.pg_mutex);
> > +
> >        if (state == AMD_PG_STATE_GATE) {
> > +             adev->uvd.is_powergated = true;
> >                uvd_v5_0_stop(adev);
> > -             return 0;
> >        } else {
> > -             return uvd_v5_0_start(adev);
> > +             ret = uvd_v5_0_start(adev);
> > +             if (ret)
> > +                     goto out;
> > +             adev->uvd.is_powergated = false;
> > +     }
> > +
> > +out:
> > +     mutex_unlock(&adev->uvd.pg_mutex);
> > +
> > +     return ret;
> > +}
> > +
> > +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
> > +{
> > +     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > +     int data;
> > +
> > +     mutex_lock(&adev->uvd.pg_mutex);
> > +
> > +     if (adev->uvd.is_powergated) {
> > +             DRM_INFO("Cannot get clockgating state when UVD is 
> powergated.\n");
> > +             goto out;
> >        }
> > +
> > +     /* AMD_CG_SUPPORT_UVD_MGCG */
> > +     data = RREG32(mmUVD_CGC_CTRL);
> > +     if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> > +             *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> > +
> > +out:
> > +     mutex_unlock(&adev->uvd.pg_mutex);
> >   }
> >
> >   static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> > @@ -808,6 +840,7 @@ static const struct amd_ip_funcs 
> uvd_v5_0_ip_funcs = {
> >        .soft_reset = uvd_v5_0_soft_reset,
> >        .set_clockgating_state = uvd_v5_0_set_clockgating_state,
> >        .set_powergating_state = uvd_v5_0_set_powergating_state,
> > +     .get_clockgating_state = uvd_v5_0_get_clockgating_state,
> >   };
> >
> >   static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> > index 8779d4b..0ec692d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> > @@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void 
> *handle,
> >         * the smc and the hw blocks
> >         */
> >        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > +     int ret = 0;
> >
> >        if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
> >                return 0;
> >
> >        WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
> >
> > +     mutex_lock(&adev->uvd.pg_mutex);
> > +
> >        if (state == AMD_PG_STATE_GATE) {
> > +             adev->uvd.is_powergated = true;
> >                uvd_v6_0_stop(adev);
> > -             return 0;
> >        } else {
> > -             return uvd_v6_0_start(adev);
> > +             ret = uvd_v6_0_start(adev);
> > +             if (ret)
> > +                     goto out;
> > +             adev->uvd.is_powergated = false;
> > +     }
> > +
> > +out:
> > +     mutex_unlock(&adev->uvd.pg_mutex);
> > +
> > +     return ret;
> > +}
> > +
> > +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
> > +{
> > +     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> > +     int data;
> > +
> > +     mutex_lock(&adev->uvd.pg_mutex);
> > +
> > +     if (adev->uvd.is_powergated) {
> > +             DRM_INFO("Cannot get clockgating state when UVD is 
> powergated.\n");
> > +             goto out;
> >        }
> > +
> > +     /* AMD_CG_SUPPORT_UVD_MGCG */
> > +     data = RREG32(mmUVD_CGC_CTRL);
> > +     if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> > +             *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> > +
> > +out:
> > +     mutex_unlock(&adev->uvd.pg_mutex);
> >   }
> >
> >   static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> > @@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs 
> uvd_v6_0_ip_funcs = {
> >        .post_soft_reset = uvd_v6_0_post_soft_reset,
> >        .set_clockgating_state = uvd_v6_0_set_clockgating_state,
> >        .set_powergating_state = uvd_v6_0_set_powergating_state,
> > +     .get_clockgating_state = uvd_v6_0_get_clockgating_state,
> >   };
> >
> >   static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> amd-gfx Info Page - lists.freedesktop.org 
> <https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
> lists.freedesktop.org
> To see the collection of prior postings to the list, visit the amd-gfx 
> Archives. Using amd-gfx: To post a message to all the list members, 
> send email ...
>
>
>


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Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 7660 bytes --]

It was added late last year so that debugfs mmio could read vce/uvd registers without triggering a race condition between transitions.


Cheers,

Tom


________________________________
From: Koenig, Christian
Sent: Friday, January 6, 2017 08:45
To: StDenis, Tom; Huang, Ray; Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp93gSJqDPrsil@public.gmane.org.org
Cc: Kuehling, Felix; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David
Subject: Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

Good point, I wasn't ware that the pm mutex still existed and is taken under all code flows.

Christian.

Am 06.01.2017 um 14:42 schrieb StDenis, Tom:

There's already the adev->pm.mutex which is held while gating/ungating blocks.  There's no need for a second mutex right?


Tom


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org><mailto:amd-gfx-bounces@lists.freedesktop.org> on behalf of Christian König <christian.koenig@amd.com><mailto:christian.koenig-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, January 6, 2017 07:52
To: Huang, Ray; Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Kuehling, Felix; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David
Subject: Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6

Am 06.01.2017 um 11:51 schrieb Huang Rui:
> Signed-off-by: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org><mailto:ray.huang-5C7GfCeVMHo@public.gmane.org>
> ---
>
> Changes from V2 -> V3:
> - add mutex to protect the is_powergated flag.
>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 +++++++++++++++++++++++++++++++++--
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 +++++++++++++++++++++++++++++++++--
>   3 files changed, 72 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 530549b..afb3ded 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1183,6 +1183,8 @@ struct amdgpu_uvd {
>        bool                    use_ctx_buf;
>        struct amd_sched_entity entity;
>        uint32_t                srbm_soft_reset;
> +     bool                    is_powergated;
> +     struct mutex            pg_mutex;

You are missing a mutex_init for pg_mutex, probably best to put this
into amdgpu_uvd_sw_init().

Apart from that the patch looks good to me now.

Regards,
Christian.

>   };
>
>   /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 03a35d9..bf797b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void *handle,
>         * the smc and the hw blocks
>         */
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int ret = 0;
>
>        if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
>                return 0;
>
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
>        if (state == AMD_PG_STATE_GATE) {
> +             adev->uvd.is_powergated = true;
>                uvd_v5_0_stop(adev);
> -             return 0;
>        } else {
> -             return uvd_v5_0_start(adev);
> +             ret = uvd_v5_0_start(adev);
> +             if (ret)
> +                     goto out;
> +             adev->uvd.is_powergated = false;
> +     }
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
> +
> +     return ret;
> +}
> +
> +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> +     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int data;
> +
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
> +     if (adev->uvd.is_powergated) {
> +             DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> +             goto out;
>        }
> +
> +     /* AMD_CG_SUPPORT_UVD_MGCG */
> +     data = RREG32(mmUVD_CGC_CTRL);
> +     if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> +             *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
>   }
>
>   static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> @@ -808,6 +840,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
>        .soft_reset = uvd_v5_0_soft_reset,
>        .set_clockgating_state = uvd_v5_0_set_clockgating_state,
>        .set_powergating_state = uvd_v5_0_set_powergating_state,
> +     .get_clockgating_state = uvd_v5_0_get_clockgating_state,
>   };
>
>   static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 8779d4b..0ec692d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void *handle,
>         * the smc and the hw blocks
>         */
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int ret = 0;
>
>        if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
>                return 0;
>
>        WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
>
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
>        if (state == AMD_PG_STATE_GATE) {
> +             adev->uvd.is_powergated = true;
>                uvd_v6_0_stop(adev);
> -             return 0;
>        } else {
> -             return uvd_v6_0_start(adev);
> +             ret = uvd_v6_0_start(adev);
> +             if (ret)
> +                     goto out;
> +             adev->uvd.is_powergated = false;
> +     }
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
> +
> +     return ret;
> +}
> +
> +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
> +{
> +     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +     int data;
> +
> +     mutex_lock(&adev->uvd.pg_mutex);
> +
> +     if (adev->uvd.is_powergated) {
> +             DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
> +             goto out;
>        }
> +
> +     /* AMD_CG_SUPPORT_UVD_MGCG */
> +     data = RREG32(mmUVD_CGC_CTRL);
> +     if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
> +             *flags |= AMD_CG_SUPPORT_UVD_MGCG;
> +
> +out:
> +     mutex_unlock(&adev->uvd.pg_mutex);
>   }
>
>   static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> @@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
>        .post_soft_reset = uvd_v6_0_post_soft_reset,
>        .set_clockgating_state = uvd_v6_0_set_clockgating_state,
>        .set_powergating_state = uvd_v6_0_set_powergating_state,
> +     .get_clockgating_state = uvd_v6_0_get_clockgating_state,
>   };
>
>   static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {


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