More debugfs entries

More debugfs entries

[Tom St Denis]

Resending the MMIO upgrades for completeness.  Christian offered
an ACK but I'd like to see a RB or NAK.

This also adds a debugfs entry used to read wave data on CZ/VI
platforms (tested on my Carrizo).  

The patch #3 already has a use in reading SQ information from
user space so I'd like to advocate for that one as well.

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[PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

[Tom St Denis]

Currently supports CZ/VI.  Allows nearly atomic read
of wave data from GPU.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 74 ++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 89b353418195..b1ab6358fa0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2914,6 +2914,72 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
 	return !r ? 4 : r;
 }
 
+static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address)
+{
+	WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
+	return RREG32(SQ_DATA);
+}
+
+static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
+					size_t size, loff_t *pos)
+{
+	struct amdgpu_device *adev = f->f_inode->i_private;
+	int r, x;
+	ssize_t result=0;
+	uint32_t offset, se, sh, cu, wave, simd, data[16];
+	
+	if (size & 3 || *pos & 3)
+		return -EINVAL;
+
+	/* decode offset */
+	offset = (*pos & 0x7F);
+	se = ((*pos >> 7) & 0xFF);
+	sh = ((*pos >> 15) & 0xFF);
+	cu = ((*pos >> 23) & 0xFF);
+	wave = ((*pos >> 31) & 0xFF);
+	simd = ((*pos >> 37) & 0xFF);
+	*pos &= 0x7F;
+
+	/* switch to the specific se/sh/cu */
+	mutex_lock(&adev->grbm_idx_mutex);
+	amdgpu_gfx_select_se_sh(adev, se, sh, cu);
+
+	x = 0;
+	if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) {
+		/* type 0 wave data */
+		data[x++] = 0;
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A);
+		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B);
+	} else {
+		return -EINVAL;
+	}
+
+	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
+	mutex_unlock(&adev->grbm_idx_mutex);
+
+	while (size && (*pos < x * 4)) {
+		uint32_t value;
+
+		value = data[*pos >> 2];
+		r = put_user(value, (uint32_t *)buf);
+		if (r)
+			return r;
+
+		result += 4;
+		buf += 4;
+		*pos += 4;
+		size -= 4;
+	}
+
+	return result;
+}
+
 static const struct file_operations amdgpu_debugfs_regs_fops = {
 	.owner = THIS_MODULE,
 	.read = amdgpu_debugfs_regs_read,
@@ -2951,6 +3017,12 @@ static const struct file_operations amdgpu_debugfs_sensors_fops = {
 	.llseek = default_llseek
 };
 
+static const struct file_operations amdgpu_debugfs_wave_fops = {
+	.owner = THIS_MODULE,
+	.read = amdgpu_debugfs_wave_read,
+	.llseek = default_llseek
+};
+
 static const struct file_operations *debugfs_regs[] = {
 	&amdgpu_debugfs_regs_fops,
 	&amdgpu_debugfs_regs_didt_fops,
@@ -2958,6 +3030,7 @@ static const struct file_operations *debugfs_regs[] = {
 	&amdgpu_debugfs_regs_smc_fops,
 	&amdgpu_debugfs_gca_config_fops,
 	&amdgpu_debugfs_sensors_fops,
+	&amdgpu_debugfs_wave_fops,
 };
 
 static const char *debugfs_regs_names[] = {
@@ -2967,6 +3040,7 @@ static const char *debugfs_regs_names[] = {
 	"amdgpu_regs_smc",
 	"amdgpu_gca_config",
 	"amdgpu_sensors",
+	"amdgpu_wave",
 };
 
 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
-- 
2.10.0

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[PATCH 2/3] drm/amd/amdgpu: Allow broadcast on debugfs read (v2)

[Tom St Denis]

Allow any of the se/sh/instance fields to be
specified as a broadcast by submitting 0x3FF.

(v2) Fix broadcast range checking

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b1ab6358fa0f..c37d016b6256 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2574,6 +2574,13 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 		se_bank = (*pos >> 24) & 0x3FF;
 		sh_bank = (*pos >> 34) & 0x3FF;
 		instance_bank = (*pos >> 44) & 0x3FF;
+
+		if (se_bank == 0x3FF)
+			se_bank = 0xFFFFFFFF;
+		if (sh_bank == 0x3FF)
+			sh_bank = 0xFFFFFFFF;
+		if (instance_bank == 0x3FF)
+			instance_bank = 0xFFFFFFFF;
 		use_bank = 1;
 	} else {
 		use_bank = 0;
@@ -2582,8 +2589,8 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 	*pos &= 0x3FFFF;
 
 	if (use_bank) {
-		if (sh_bank >= adev->gfx.config.max_sh_per_se ||
-		    se_bank >= adev->gfx.config.max_shader_engines)
+		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
+		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
 			return -EINVAL;
 		mutex_lock(&adev->grbm_idx_mutex);
 		amdgpu_gfx_select_se_sh(adev, se_bank,
-- 
2.10.0

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[PATCH 3/3] drm/amd/amdgpu: Make debugfs write compliment read

[Tom St Denis]

Add PG lock support as well as bank selection to
the MMIO write function.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 43 ++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c37d016b6256..6f8bd16205db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2637,10 +2637,45 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 	struct amdgpu_device *adev = f->f_inode->i_private;
 	ssize_t result = 0;
 	int r;
+	bool pm_pg_lock, use_bank;
+	unsigned instance_bank, sh_bank, se_bank;
 
 	if (size & 0x3 || *pos & 0x3)
 		return -EINVAL;
 
+	/* are we reading registers for which a PG lock is necessary? */
+	pm_pg_lock = (*pos >> 23) & 1;
+
+	if (*pos & (1ULL << 62)) {
+		se_bank = (*pos >> 24) & 0x3FF;
+		sh_bank = (*pos >> 34) & 0x3FF;
+		instance_bank = (*pos >> 44) & 0x3FF;
+
+		if (se_bank == 0x3FF)
+			se_bank = 0xFFFFFFFF;
+		if (sh_bank == 0x3FF)
+			sh_bank = 0xFFFFFFFF;
+		if (instance_bank == 0x3FF)
+			instance_bank = 0xFFFFFFFF;
+		use_bank = 1;
+	} else {
+		use_bank = 0;
+	}
+
+	*pos &= 0x3FFFF;
+
+	if (use_bank) {
+		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
+		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
+			return -EINVAL;
+		mutex_lock(&adev->grbm_idx_mutex);
+		amdgpu_gfx_select_se_sh(adev, se_bank,
+					sh_bank, instance_bank);
+	}
+
+	if (pm_pg_lock)
+		mutex_lock(&adev->pm.mutex);
+
 	while (size) {
 		uint32_t value;
 
@@ -2659,6 +2694,14 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 		size -= 4;
 	}
 
+	if (use_bank) {
+		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+		mutex_unlock(&adev->grbm_idx_mutex);
+	}
+
+	if (pm_pg_lock)
+		mutex_unlock(&adev->pm.mutex);
+
 	return result;
 }
 
-- 
2.10.0

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Re: More debugfs entries

[Alex Deucher]

On Tue, Oct 11, 2016 at 3:18 PM, Tom St Denis <tstdenis82@gmail.com> wrote:
> Resending the MMIO upgrades for completeness.  Christian offered
> an ACK but I'd like to see a RB or NAK.
>
> This also adds a debugfs entry used to read wave data on CZ/VI
> platforms (tested on my Carrizo).
>
> The patch #3 already has a use in reading SQ information from
> user space so I'd like to advocate for that one as well.

For the series:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

[Nicolai Hähnle]

On 11.10.2016 21:18, Tom St Denis wrote:
> Currently supports CZ/VI.  Allows nearly atomic read
> of wave data from GPU.
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 74 ++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 89b353418195..b1ab6358fa0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2914,6 +2914,72 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
>  	return !r ? 4 : r;
>  }
>
> +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address)
> +{
> +	WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
> +	return RREG32(SQ_DATA);
> +}
> +
> +static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
> +					size_t size, loff_t *pos)
> +{
> +	struct amdgpu_device *adev = f->f_inode->i_private;
> +	int r, x;
> +	ssize_t result=0;
> +	uint32_t offset, se, sh, cu, wave, simd, data[16];
> +	
> +	if (size & 3 || *pos & 3)
> +		return -EINVAL;
> +
> +	/* decode offset */
> +	offset = (*pos & 0x7F);
> +	se = ((*pos >> 7) & 0xFF);
> +	sh = ((*pos >> 15) & 0xFF);
> +	cu = ((*pos >> 23) & 0xFF);
> +	wave = ((*pos >> 31) & 0xFF);
> +	simd = ((*pos >> 37) & 0xFF);
> +	*pos &= 0x7F;
> +
> +	/* switch to the specific se/sh/cu */
> +	mutex_lock(&adev->grbm_idx_mutex);
> +	amdgpu_gfx_select_se_sh(adev, se, sh, cu);
> +
> +	x = 0;
> +	if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) {
> +		/* type 0 wave data */
> +		data[x++] = 0;
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A);
> +		data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B);

I know this is just debug code, but it's still annoying to have all 
these magic constants here, when there are perfectly good ixSQ_WAVE_* 
etc. defines in the asic_reg headers.

Nicolai

> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
> +	mutex_unlock(&adev->grbm_idx_mutex);
> +
> +	while (size && (*pos < x * 4)) {
> +		uint32_t value;
> +
> +		value = data[*pos >> 2];
> +		r = put_user(value, (uint32_t *)buf);
> +		if (r)
> +			return r;
> +
> +		result += 4;
> +		buf += 4;
> +		*pos += 4;
> +		size -= 4;
> +	}
> +
> +	return result;
> +}
> +
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>  	.owner = THIS_MODULE,
>  	.read = amdgpu_debugfs_regs_read,
> @@ -2951,6 +3017,12 @@ static const struct file_operations amdgpu_debugfs_sensors_fops = {
>  	.llseek = default_llseek
>  };
>
> +static const struct file_operations amdgpu_debugfs_wave_fops = {
> +	.owner = THIS_MODULE,
> +	.read = amdgpu_debugfs_wave_read,
> +	.llseek = default_llseek
> +};
> +
>  static const struct file_operations *debugfs_regs[] = {
>  	&amdgpu_debugfs_regs_fops,
>  	&amdgpu_debugfs_regs_didt_fops,
> @@ -2958,6 +3030,7 @@ static const struct file_operations *debugfs_regs[] = {
>  	&amdgpu_debugfs_regs_smc_fops,
>  	&amdgpu_debugfs_gca_config_fops,
>  	&amdgpu_debugfs_sensors_fops,
> +	&amdgpu_debugfs_wave_fops,
>  };
>
>  static const char *debugfs_regs_names[] = {
> @@ -2967,6 +3040,7 @@ static const char *debugfs_regs_names[] = {
>  	"amdgpu_regs_smc",
>  	"amdgpu_gca_config",
>  	"amdgpu_sensors",
> +	"amdgpu_wave",
>  };
>
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
>
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Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 5266 bytes --]

Hi Nicolai,


I was trying to avoid having ASIC specific includes/etc in the amdgpu_device.c file.  Agreed that de-numberifying it would be nice.  Maybe we can add some /**/ comments to clear it up.  I imagine in the future we'll add more fields (upto 32 in this design) anyways.


Cheers,

Tom


________________________________
From: Nicolai Hähnle <nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Friday, October 14, 2016 03:25
To: Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: StDenis, Tom
Subject: Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

On 11.10.2016 21:18, Tom St Denis wrote:
> Currently supports CZ/VI.  Allows nearly atomic read
> of wave data from GPU.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 74 ++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 89b353418195..b1ab6358fa0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2914,6 +2914,72 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
>        return !r ? 4 : r;
>  }
>
> +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address)
> +{
> +     WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
> +     return RREG32(SQ_DATA);
> +}
> +
> +static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
> +                                     size_t size, loff_t *pos)
> +{
> +     struct amdgpu_device *adev = f->f_inode->i_private;
> +     int r, x;
> +     ssize_t result=0;
> +     uint32_t offset, se, sh, cu, wave, simd, data[16];
> +
> +     if (size & 3 || *pos & 3)
> +             return -EINVAL;
> +
> +     /* decode offset */
> +     offset = (*pos & 0x7F);
> +     se = ((*pos >> 7) & 0xFF);
> +     sh = ((*pos >> 15) & 0xFF);
> +     cu = ((*pos >> 23) & 0xFF);
> +     wave = ((*pos >> 31) & 0xFF);
> +     simd = ((*pos >> 37) & 0xFF);
> +     *pos &= 0x7F;
> +
> +     /* switch to the specific se/sh/cu */
> +     mutex_lock(&adev->grbm_idx_mutex);
> +     amdgpu_gfx_select_se_sh(adev, se, sh, cu);
> +
> +     x = 0;
> +     if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) {
> +             /* type 0 wave data */
> +             data[x++] = 0;
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B);

I know this is just debug code, but it's still annoying to have all
these magic constants here, when there are perfectly good ixSQ_WAVE_*
etc. defines in the asic_reg headers.

Nicolai

> +     } else {
> +             return -EINVAL;
> +     }
> +
> +     amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
> +     mutex_unlock(&adev->grbm_idx_mutex);
> +
> +     while (size && (*pos < x * 4)) {
> +             uint32_t value;
> +
> +             value = data[*pos >> 2];
> +             r = put_user(value, (uint32_t *)buf);
> +             if (r)
> +                     return r;
> +
> +             result += 4;
> +             buf += 4;
> +             *pos += 4;
> +             size -= 4;
> +     }
> +
> +     return result;
> +}
> +
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>        .owner = THIS_MODULE,
>        .read = amdgpu_debugfs_regs_read,
> @@ -2951,6 +3017,12 @@ static const struct file_operations amdgpu_debugfs_sensors_fops = {
>        .llseek = default_llseek
>  };
>
> +static const struct file_operations amdgpu_debugfs_wave_fops = {
> +     .owner = THIS_MODULE,
> +     .read = amdgpu_debugfs_wave_read,
> +     .llseek = default_llseek
> +};
> +
>  static const struct file_operations *debugfs_regs[] = {
>        &amdgpu_debugfs_regs_fops,
>        &amdgpu_debugfs_regs_didt_fops,
> @@ -2958,6 +3030,7 @@ static const struct file_operations *debugfs_regs[] = {
>        &amdgpu_debugfs_regs_smc_fops,
>        &amdgpu_debugfs_gca_config_fops,
>        &amdgpu_debugfs_sensors_fops,
> +     &amdgpu_debugfs_wave_fops,
>  };
>
>  static const char *debugfs_regs_names[] = {
> @@ -2967,6 +3040,7 @@ static const char *debugfs_regs_names[] = {
>        "amdgpu_regs_smc",
>        "amdgpu_gca_config",
>        "amdgpu_sensors",
> +     "amdgpu_wave",
>  };
>
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
>

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RE: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

[Deucher, Alexander]

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You could make the wave decode a gfx callback and move the code into the IP modules.

Alex

From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of StDenis, Tom
Sent: Friday, October 14, 2016 6:56 AM
To: Nicolai Hähnle
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs


Hi Nicolai,



I was trying to avoid having ASIC specific includes/etc in the amdgpu_device.c file.  Agreed that de-numberifying it would be nice.  Maybe we can add some /**/ comments to clear it up.  I imagine in the future we'll add more fields (upto 32 in this design) anyways.



Cheers,

Tom

________________________________
From: Nicolai Hähnle <nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org<mailto:nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
Sent: Friday, October 14, 2016 03:25
To: Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lMiVNPc3mojA@public.gmane.orgsktop.org>
Cc: StDenis, Tom
Subject: Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

On 11.10.2016 21:18, Tom St Denis wrote:
> Currently supports CZ/VI.  Allows nearly atomic read
> of wave data from GPU.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org<mailto:tom.stdenis@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 74 ++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 89b353418195..b1ab6358fa0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2914,6 +2914,72 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
>        return !r ? 4 : r;
>  }
>
> +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address)
> +{
> +     WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
> +     return RREG32(SQ_DATA);
> +}
> +
> +static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
> +                                     size_t size, loff_t *pos)
> +{
> +     struct amdgpu_device *adev = f->f_inode->i_private;
> +     int r, x;
> +     ssize_t result=0;
> +     uint32_t offset, se, sh, cu, wave, simd, data[16];
> +
> +     if (size & 3 || *pos & 3)
> +             return -EINVAL;
> +
> +     /* decode offset */
> +     offset = (*pos & 0x7F);
> +     se = ((*pos >> 7) & 0xFF);
> +     sh = ((*pos >> 15) & 0xFF);
> +     cu = ((*pos >> 23) & 0xFF);
> +     wave = ((*pos >> 31) & 0xFF);
> +     simd = ((*pos >> 37) & 0xFF);
> +     *pos &= 0x7F;
> +
> +     /* switch to the specific se/sh/cu */
> +     mutex_lock(&adev->grbm_idx_mutex);
> +     amdgpu_gfx_select_se_sh(adev, se, sh, cu);
> +
> +     x = 0;
> +     if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) {
> +             /* type 0 wave data */
> +             data[x++] = 0;
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B);

I know this is just debug code, but it's still annoying to have all
these magic constants here, when there are perfectly good ixSQ_WAVE_*
etc. defines in the asic_reg headers.

Nicolai

> +     } else {
> +             return -EINVAL;
> +     }
> +
> +     amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
> +     mutex_unlock(&adev->grbm_idx_mutex);
> +
> +     while (size && (*pos < x * 4)) {
> +             uint32_t value;
> +
> +             value = data[*pos >> 2];
> +             r = put_user(value, (uint32_t *)buf);
> +             if (r)
> +                     return r;
> +
> +             result += 4;
> +             buf += 4;
> +             *pos += 4;
> +             size -= 4;
> +     }
> +
> +     return result;
> +}
> +
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>        .owner = THIS_MODULE,
>        .read = amdgpu_debugfs_regs_read,
> @@ -2951,6 +3017,12 @@ static const struct file_operations amdgpu_debugfs_sensors_fops = {
>        .llseek = default_llseek
>  };
>
> +static const struct file_operations amdgpu_debugfs_wave_fops = {
> +     .owner = THIS_MODULE,
> +     .read = amdgpu_debugfs_wave_read,
> +     .llseek = default_llseek
> +};
> +
>  static const struct file_operations *debugfs_regs[] = {
>        &amdgpu_debugfs_regs_fops,
>        &amdgpu_debugfs_regs_didt_fops,
> @@ -2958,6 +3030,7 @@ static const struct file_operations *debugfs_regs[] = {
>        &amdgpu_debugfs_regs_smc_fops,
>        &amdgpu_debugfs_gca_config_fops,
>        &amdgpu_debugfs_sensors_fops,
> +     &amdgpu_debugfs_wave_fops,
>  };
>
>  static const char *debugfs_regs_names[] = {
> @@ -2967,6 +3040,7 @@ static const char *debugfs_regs_names[] = {
>        "amdgpu_regs_smc",
>        "amdgpu_gca_config",
>        "amdgpu_sensors",
> +     "amdgpu_wave",
>  };
>
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
>

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Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 6203 bytes --]

Hi Alex,


Sounds like a plan since I want to add a few fields anyways.


Tom


________________________________
From: Deucher, Alexander
Sent: Friday, October 14, 2016 09:33
To: StDenis, Tom; Nicolai Hähnle
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs


You could make the wave decode a gfx callback and move the code into the IP modules.



Alex



From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of StDenis, Tom
Sent: Friday, October 14, 2016 6:56 AM
To: Nicolai Hähnle
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs



Hi Nicolai,



I was trying to avoid having ASIC specific includes/etc in the amdgpu_device.c file.  Agreed that de-numberifying it would be nice.  Maybe we can add some /**/ comments to clear it up.  I imagine in the future we'll add more fields (upto 32 in this design) anyways.



Cheers,

Tom



________________________________

From: Nicolai Hähnle <nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org<mailto:nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
Sent: Friday, October 14, 2016 03:25
To: Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lMiVNPc3mojA@public.gmane.orgsktop.org>
Cc: StDenis, Tom
Subject: Re: [PATCH 1/3] drm/amd/amdgpu: Add wave reader to debugfs



On 11.10.2016 21:18, Tom St Denis wrote:
> Currently supports CZ/VI.  Allows nearly atomic read
> of wave data from GPU.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org<mailto:tom.stdenis@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 74 ++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 89b353418195..b1ab6358fa0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2914,6 +2914,72 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
>        return !r ? 4 : r;
>  }
>
> +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t SQ_INDEX, uint32_t SQ_DATA, uint32_t simd, uint32_t wave, uint32_t address)
> +{
> +     WREG32(SQ_INDEX, (wave & 0xF) | ((simd & 0x3) << 4) | (address << 16) | (1 << 13));
> +     return RREG32(SQ_DATA);
> +}
> +
> +static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
> +                                     size_t size, loff_t *pos)
> +{
> +     struct amdgpu_device *adev = f->f_inode->i_private;
> +     int r, x;
> +     ssize_t result=0;
> +     uint32_t offset, se, sh, cu, wave, simd, data[16];
> +
> +     if (size & 3 || *pos & 3)
> +             return -EINVAL;
> +
> +     /* decode offset */
> +     offset = (*pos & 0x7F);
> +     se = ((*pos >> 7) & 0xFF);
> +     sh = ((*pos >> 15) & 0xFF);
> +     cu = ((*pos >> 23) & 0xFF);
> +     wave = ((*pos >> 31) & 0xFF);
> +     simd = ((*pos >> 37) & 0xFF);
> +     *pos &= 0x7F;
> +
> +     /* switch to the specific se/sh/cu */
> +     mutex_lock(&adev->grbm_idx_mutex);
> +     amdgpu_gfx_select_se_sh(adev, se, sh, cu);
> +
> +     x = 0;
> +     if (adev->family == AMDGPU_FAMILY_CZ || adev->family == AMDGPU_FAMILY_VI) {
> +             /* type 0 wave data */
> +             data[x++] = 0;
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x12);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x18);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x19);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27E);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x27F);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x14);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1A);
> +             data[x++] = wave_read_ind(adev, 0x2378, 0x2379, simd, wave, 0x1B);

I know this is just debug code, but it's still annoying to have all
these magic constants here, when there are perfectly good ixSQ_WAVE_*
etc. defines in the asic_reg headers.

Nicolai

> +     } else {
> +             return -EINVAL;
> +     }
> +
> +     amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
> +     mutex_unlock(&adev->grbm_idx_mutex);
> +
> +     while (size && (*pos < x * 4)) {
> +             uint32_t value;
> +
> +             value = data[*pos >> 2];
> +             r = put_user(value, (uint32_t *)buf);
> +             if (r)
> +                     return r;
> +
> +             result += 4;
> +             buf += 4;
> +             *pos += 4;
> +             size -= 4;
> +     }
> +
> +     return result;
> +}
> +
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>        .owner = THIS_MODULE,
>        .read = amdgpu_debugfs_regs_read,
> @@ -2951,6 +3017,12 @@ static const struct file_operations amdgpu_debugfs_sensors_fops = {
>        .llseek = default_llseek
>  };
>
> +static const struct file_operations amdgpu_debugfs_wave_fops = {
> +     .owner = THIS_MODULE,
> +     .read = amdgpu_debugfs_wave_read,
> +     .llseek = default_llseek
> +};
> +
>  static const struct file_operations *debugfs_regs[] = {
>        &amdgpu_debugfs_regs_fops,
>        &amdgpu_debugfs_regs_didt_fops,
> @@ -2958,6 +3030,7 @@ static const struct file_operations *debugfs_regs[] = {
>        &amdgpu_debugfs_regs_smc_fops,
>        &amdgpu_debugfs_gca_config_fops,
>        &amdgpu_debugfs_sensors_fops,
> +     &amdgpu_debugfs_wave_fops,
>  };
>
>  static const char *debugfs_regs_names[] = {
> @@ -2967,6 +3040,7 @@ static const char *debugfs_regs_names[] = {
>        "amdgpu_regs_smc",
>        "amdgpu_gca_config",
>        "amdgpu_sensors",
> +     "amdgpu_wave",
>  };
>
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
>

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