Re: [PART1 PATCH 0/8] Introduce a method to get clock gating status dynamically

[Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>]

On Thu, Jan 05, 2017 at 11:40:33PM +0800, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: Huang Rui [mailto:ray.huang@amd.com]
> > Sent: Thursday, January 05, 2017 8:50 AM
> > To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> > Cc: Zhu, Rex; Mao, David; Fu, Ping; Zhang, Hawking; Huang, Ray
> > Subject: [PART1 PATCH 0/8] Introduce a method to get clock gating status
> > dynamically
> > 
> > This series patches implement to get the clock gating status
> > dynamically into debugfs. User will enter profiling mode to runtime
> > disable clockgating, so it needs an interface to expose clock gating
> > states. Part 1 works for VI, I will implement it on CI/SI in following
> > days.
> 
> Patches 1-6:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> 
> Patches 7, 8:
> I'm not sure if the UVD and VCE status registers are available if the blocks are powergated.  Reading them back while powergated can cause a hang.  Might want to check the PG sw state before reading back the registers.
> 

OK, so I should check whether UVD/VCE is in AMD_PG_STATE_UNGATE before
reading the registers.

Thanks,
Rui
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