[PATCH 1/3] drm/amdgpu: add optional ring to *_hdp callbacks

[PATCH 1/3] drm/amdgpu: add optional ring to *_hdp callbacks

[Christian König]

This adds an optional ring to the invalidate_hdp and flush_hdp
callbacks. If the ring isn't specified or the emit_wreg function not
available the HDP operation will be done with the CPU otherwise by
writing on the ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      | 11 ++++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/cik.c         | 21 +++++++++++++++------
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c   | 11 +++++++++--
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c   |  9 +++++++--
 drivers/gpu/drm/amd/amdgpu/si.c          | 21 +++++++++++++++------
 drivers/gpu/drm/amd/amdgpu/soc15.c       | 13 +++++++++----
 drivers/gpu/drm/amd/amdgpu/vi.c          | 21 +++++++++++++++------
 10 files changed, 81 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 230826718c98..cf55086c9823 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1221,9 +1221,10 @@ struct amdgpu_asic_funcs {
 	/* get config memsize register */
 	u32 (*get_config_memsize)(struct amdgpu_device *adev);
 	/* flush hdp write queue */
-	void (*flush_hdp)(struct amdgpu_device *adev);
+	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 	/* invalidate hdp read cache */
-	void (*invalidate_hdp)(struct amdgpu_device *adev);
+	void (*invalidate_hdp)(struct amdgpu_device *adev,
+			       struct amdgpu_ring *ring);
 };
 
 /*
@@ -1370,7 +1371,7 @@ struct amdgpu_nbio_funcs {
 	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
 	u32 (*get_rev_id)(struct amdgpu_device *adev);
 	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
-	void (*hdp_flush)(struct amdgpu_device *adev);
+	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
 	u32 (*get_memsize)(struct amdgpu_device *adev);
 	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
 				    bool use_doorbell, int doorbell_index);
@@ -1776,8 +1777,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
-#define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
-#define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
+#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
+#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 18d23878ad14..56b0b305a9fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -247,7 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 		}
 	}
 	mb();
-	amdgpu_asic_flush_hdp(adev);
+	amdgpu_asic_flush_hdp(adev, NULL);
 	amdgpu_gmc_flush_gpu_tlb(adev, 0);
 	return 0;
 }
@@ -330,7 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
 		return r;
 
 	mb();
-	amdgpu_asic_flush_hdp(adev);
+	amdgpu_asic_flush_hdp(adev, NULL);
 	amdgpu_gmc_flush_gpu_tlb(adev, 0);
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0872620a808f..6f7141168838 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -854,7 +854,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 	if (vm->use_cpu_for_update) {
 		/* Flush HDP */
 		mb();
-		amdgpu_asic_flush_hdp(adev);
+		amdgpu_asic_flush_hdp(adev, NULL);
 	} else if (params.ib->length_dw == 0) {
 		amdgpu_job_free(job);
 	} else {
@@ -1436,7 +1436,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 	if (vm->use_cpu_for_update) {
 		/* Flush HDP */
 		mb();
-		amdgpu_asic_flush_hdp(adev);
+		amdgpu_asic_flush_hdp(adev, NULL);
 	}
 
 	spin_lock(&vm->status_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 204ce807372c..4324184996a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1715,16 +1715,25 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
 		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 }
 
-static void cik_flush_hdp(struct amdgpu_device *adev)
+static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 {
-	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
-	RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
+	if (!ring || !ring->funcs->emit_wreg) {
+		WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+		RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
+	} else {
+		amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+	}
 }
 
-static void cik_invalidate_hdp(struct amdgpu_device *adev)
+static void cik_invalidate_hdp(struct amdgpu_device *adev,
+			       struct amdgpu_ring *ring)
 {
-	WREG32(mmHDP_DEBUG0, 1);
-	RREG32(mmHDP_DEBUG0);
+	if (!ring || !ring->funcs->emit_wreg) {
+		WREG32(mmHDP_DEBUG0, 1);
+		RREG32(mmHDP_DEBUG0);
+	} else {
+		amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
+	}
 }
 
 static const struct amdgpu_asic_funcs cik_asic_funcs =
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 263da4f3e70b..2b251df94684 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1007,7 +1007,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 
 	/* After HDP is initialized, flush HDP.*/
-	adev->nbio_funcs->hdp_flush(adev);
+	adev->nbio_funcs->hdp_flush(adev, NULL);
 
 	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 		value = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index d4da663d5eb0..2daeef6e9345 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -53,9 +53,16 @@ static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
 		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
 }
 
-static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
+static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
+				struct amdgpu_ring *ring)
 {
-	WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+	if (!ring || !ring->funcs->emit_wreg)
+		WREG32_SOC15_NO_KIQ(NBIO, 0,
+				    mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
+				    0);
+	else
+		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+			NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
 }
 
 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 17a9131a4598..cd10c76a76e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -53,9 +53,14 @@ static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
 		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
 }
 
-static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
+static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
+				struct amdgpu_ring *ring)
 {
-	WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+	if (!ring || !ring->funcs->emit_wreg)
+		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
+	else
+		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
 }
 
 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f61a431b9553..f20c4b7414e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1230,16 +1230,25 @@ static void si_detect_hw_virtualization(struct amdgpu_device *adev)
 		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 }
 
-static void si_flush_hdp(struct amdgpu_device *adev)
+static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 {
-	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
-	RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
+	if (!ring || !ring->funcs->emit_wreg) {
+		WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+		RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
+	} else {
+		amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+	}
 }
 
-static void si_invalidate_hdp(struct amdgpu_device *adev)
+static void si_invalidate_hdp(struct amdgpu_device *adev,
+			      struct amdgpu_ring *ring)
 {
-	WREG32(mmHDP_DEBUG0, 1);
-	RREG32(mmHDP_DEBUG0);
+	if (!ring || !ring->funcs->emit_wreg) {
+		WREG32(mmHDP_DEBUG0, 1);
+		RREG32(mmHDP_DEBUG0);
+	} else {
+		amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
+	}
 }
 
 static const struct amdgpu_asic_funcs si_asic_funcs =
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index ad39ffd012bc..04a471b80064 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -583,14 +583,19 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 	return adev->nbio_funcs->get_rev_id(adev);
 }
 
-static void soc15_flush_hdp(struct amdgpu_device *adev)
+static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 {
-	adev->nbio_funcs->hdp_flush(adev);
+	adev->nbio_funcs->hdp_flush(adev, ring);
 }
 
-static void soc15_invalidate_hdp(struct amdgpu_device *adev)
+static void soc15_invalidate_hdp(struct amdgpu_device *adev,
+				 struct amdgpu_ring *ring)
 {
-	WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+	if (!ring || !ring->funcs->emit_wreg)
+		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+	else
+		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 }
 
 static const struct amdgpu_asic_funcs soc15_asic_funcs =
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9dd5350d9504..3b66e1abb37f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -856,16 +856,25 @@ static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
 			>> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
 }
 
-static void vi_flush_hdp(struct amdgpu_device *adev)
+static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 {
-	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
-	RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
+	if (!ring || !ring->funcs->emit_wreg) {
+		WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+		RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
+	} else {
+		amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+	}
 }
 
-static void vi_invalidate_hdp(struct amdgpu_device *adev)
+static void vi_invalidate_hdp(struct amdgpu_device *adev,
+			      struct amdgpu_ring *ring)
 {
-	WREG32(mmHDP_DEBUG0, 1);
-	RREG32(mmHDP_DEBUG0);
+	if (!ring || !ring->funcs->emit_wreg) {
+		WREG32(mmHDP_DEBUG0, 1);
+		RREG32(mmHDP_DEBUG0);
+	} else {
+		amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
+	}
 }
 
 static const struct amdgpu_asic_funcs vi_asic_funcs =
-- 
2.14.1

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[PATCH 2/3] drm/amdgpu: fallback to generic HDP operation

[Christian König]

When ring special operations aren't available we can fallback to the
generic ASIC operations.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a162d87ca0c8..e87c9952c901 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -184,12 +184,15 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (ring->funcs->init_cond_exec)
 		patch_offset = amdgpu_ring_init_cond_exec(ring);
 
-	if (ring->funcs->emit_hdp_flush
 #ifdef CONFIG_X86_64
-	    && !(adev->flags & AMD_IS_APU)
+	if (!(adev->flags & AMD_IS_APU))
 #endif
-	   )
-		amdgpu_ring_emit_hdp_flush(ring);
+	{
+		if (ring->funcs->emit_hdp_flush)
+			amdgpu_ring_emit_hdp_flush(ring);
+		else
+			amdgpu_asic_flush_hdp(adev, ring);
+	}
 
 	skip_preamble = ring->current_ctx == fence_ctx;
 	need_ctx_switch = ring->current_ctx != fence_ctx;
@@ -219,12 +222,15 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (ring->funcs->emit_tmz)
 		amdgpu_ring_emit_tmz(ring, false);
 
-	if (ring->funcs->emit_hdp_invalidate
 #ifdef CONFIG_X86_64
-	    && !(adev->flags & AMD_IS_APU)
+	if (!(adev->flags & AMD_IS_APU))
 #endif
-	   )
-		amdgpu_ring_emit_hdp_invalidate(ring);
+	{
+		if (ring->funcs->emit_hdp_invalidate)
+			amdgpu_ring_emit_hdp_invalidate(ring);
+		else
+			amdgpu_asic_invalidate_hdp(adev, ring);
+	}
 
 	r = amdgpu_fence_emit(ring, f);
 	if (r) {
-- 
2.14.1

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[PATCH 3/3] drm/amdgpu: remove now superflous *_hdp operation

[Christian König]

All HDP invalidation and most flush can now be replaced by the generic
ASIC function.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  7 +-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 -
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 10 +-------
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    | 39 ++------------------------------
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    | 26 ++-------------------
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 19 ++--------------
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 14 ++----------
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 10 +-------
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 11 +--------
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 13 +----------
 drivers/gpu/drm/amd/amdgpu/si_dma.c      | 19 +---------------
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    | 30 ------------------------
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    | 30 ------------------------
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    | 35 +---------------------------
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 37 ++----------------------------
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c    | 18 +--------------
 17 files changed, 18 insertions(+), 302 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cf55086c9823..9127dbd9a478 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1799,7 +1799,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
-#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e87c9952c901..8ea342dc6376 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -225,12 +225,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 #ifdef CONFIG_X86_64
 	if (!(adev->flags & AMD_IS_APU))
 #endif
-	{
-		if (ring->funcs->emit_hdp_invalidate)
-			amdgpu_ring_emit_hdp_invalidate(ring);
-		else
-			amdgpu_asic_invalidate_hdp(adev, ring);
-	}
+		amdgpu_asic_invalidate_hdp(adev, ring);
 
 	r = amdgpu_fence_emit(ring, f);
 	if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 12b9a06f4d21..70d05ec7bc07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -128,7 +128,6 @@ struct amdgpu_ring_funcs {
 	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
 			      unsigned pasid, uint64_t pd_addr);
 	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
-	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
 	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
 				uint32_t gds_base, uint32_t gds_size,
 				uint32_t gws_base, uint32_t gws_size,
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 1d32dedb2534..5d18512cd090 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -261,13 +261,6 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 }
 
-static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
  *
@@ -1277,7 +1270,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
 	.set_wptr = cik_sdma_ring_set_wptr,
 	.emit_frame_size =
 		6 + /* cik_sdma_ring_emit_hdp_flush */
-		3 + /* cik_sdma_ring_emit_hdp_invalidate */
+		3 + /* hdp invalidate */
 		6 + /* cik_sdma_ring_emit_pipeline_sync */
 		CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
 		9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
@@ -1287,7 +1280,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
 	.emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
 	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
 	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
 	.test_ring = cik_sdma_ring_test_ring,
 	.test_ib = cik_sdma_ring_test_ib,
 	.insert_nop = cik_sdma_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index e6c3a2465ba4..3517fd9e11c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1809,17 +1809,6 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 	return r;
 }
 
-static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
-{
-	/* flush hdp cache */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
-				 WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 0x1);
-}
-
 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
 {
 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
@@ -1827,24 +1816,6 @@ static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
 		EVENT_INDEX(0));
 }
 
-/**
- * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
- *
- * @adev: amdgpu_device pointer
- * @ridx: amdgpu ring index
- *
- * Emits an hdp invalidate on the cp.
- */
-static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
-				 WRITE_DATA_DST_SEL(0)));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 0x1);
-}
-
 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 				     u64 seq, unsigned flags)
 {
@@ -3507,8 +3478,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
 	.get_wptr = gfx_v6_0_ring_get_wptr,
 	.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
 	.emit_frame_size =
-		5 + /* gfx_v6_0_ring_emit_hdp_flush */
-		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
+		5 + 5 + /* hdp flush / invalidate */
 		14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
 		7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
 		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
@@ -3518,8 +3488,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
 	.emit_fence = gfx_v6_0_ring_emit_fence,
 	.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
 	.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
-	.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v6_0_ring_test_ring,
 	.test_ib = gfx_v6_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -3535,8 +3503,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
 	.get_wptr = gfx_v6_0_ring_get_wptr,
 	.set_wptr = gfx_v6_0_ring_set_wptr_compute,
 	.emit_frame_size =
-		5 + /* gfx_v6_0_ring_emit_hdp_flush */
-		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
+		5 + 5 + /* hdp flush / invalidate */
 		7 + /* gfx_v6_0_ring_emit_pipeline_sync */
 		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
 		14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
@@ -3545,8 +3512,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
 	.emit_fence = gfx_v6_0_ring_emit_fence,
 	.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
 	.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
-	.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v6_0_ring_test_ring,
 	.test_ib = gfx_v6_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 3c2b678436f2..764e068fc2dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2147,26 +2147,6 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
 		EVENT_INDEX(0));
 }
 
-
-/**
- * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
- *
- * @adev: amdgpu_device pointer
- * @ridx: amdgpu ring index
- *
- * Emits an hdp invalidate on the cp.
- */
-static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(0) |
-				 WR_CONFIRM));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
  *
@@ -5110,7 +5090,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
 	.emit_frame_size =
 		20 + /* gfx_v7_0_ring_emit_gds_switch */
 		7 + /* gfx_v7_0_ring_emit_hdp_flush */
-		5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
+		5 + /* hdp invalidate */
 		12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
 		7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
 		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
@@ -5122,7 +5102,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v7_0_ring_test_ring,
 	.test_ib = gfx_v7_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -5142,7 +5121,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
 	.emit_frame_size =
 		20 + /* gfx_v7_0_ring_emit_gds_switch */
 		7 + /* gfx_v7_0_ring_emit_hdp_flush */
-		5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
+		5 + /* hdp invalidate */
 		7 + /* gfx_v7_0_ring_emit_pipeline_sync */
 		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
 		7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
@@ -5153,7 +5132,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
 	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v7_0_ring_test_ring,
 	.test_ib = gfx_v7_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e4d209b5c879..5a2e4d5a5bd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6230,19 +6230,6 @@ static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
 		EVENT_INDEX(0));
 }
 
-
-static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-				 WRITE_DATA_DST_SEL(0) |
-				 WR_CONFIRM));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 0);
-	amdgpu_ring_write(ring, 1);
-
-}
-
 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 				      struct amdgpu_ib *ib,
 				      unsigned vmid, bool ctx_switch)
@@ -6887,7 +6874,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v8_0_ring_test_ring,
 	.test_ib = gfx_v8_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -6910,7 +6896,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 	.emit_frame_size =
 		20 + /* gfx_v8_0_ring_emit_gds_switch */
 		7 + /* gfx_v8_0_ring_emit_hdp_flush */
-		5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
+		5 + /* hdp_invalidate */
 		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
 		VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
 		7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
@@ -6921,7 +6907,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
 	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v8_0_ring_test_ring,
 	.test_ib = gfx_v8_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -6941,7 +6926,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
 	.emit_frame_size =
 		20 + /* gfx_v8_0_ring_emit_gds_switch */
 		7 + /* gfx_v8_0_ring_emit_hdp_flush */
-		5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
+		5 + /* hdp_invalidate */
 		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
 		17 + /* gfx_v8_0_ring_emit_vm_flush */
 		7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index afdf57206efa..cd2b24ce785b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3585,14 +3585,6 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 			      ref_and_mask, ref_and_mask, 0x20);
 }
 
-static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	gfx_v9_0_write_data_to_reg(ring, 0, true,
-				   SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
-}
-
 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                       struct amdgpu_ib *ib,
                                       unsigned vmid, bool ctx_switch)
@@ -4319,7 +4311,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
 	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v9_0_ring_test_ring,
 	.test_ib = gfx_v9_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -4344,7 +4335,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.emit_frame_size =
 		20 + /* gfx_v9_0_ring_emit_gds_switch */
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
-		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
+		5 + /* hdp invalidate */
 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
@@ -4355,7 +4346,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
 	.test_ring = gfx_v9_0_ring_test_ring,
 	.test_ib = gfx_v9_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -4376,7 +4366,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
 	.emit_frame_size =
 		20 + /* gfx_v9_0_ring_emit_gds_switch */
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
-		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
+		5 + /* hdp invalidate */
 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0aa336371816..6a7a82a8c65d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -289,13 +289,6 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 }
 
-static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 1);
-}
 /**
  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
  *
@@ -1200,7 +1193,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
 	.set_wptr = sdma_v2_4_ring_set_wptr,
 	.emit_frame_size =
 		6 + /* sdma_v2_4_ring_emit_hdp_flush */
-		3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
+		3 + /* hdp invalidate */
 		6 + /* sdma_v2_4_ring_emit_pipeline_sync */
 		VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
 		10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
@@ -1210,7 +1203,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
 	.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
 	.test_ring = sdma_v2_4_ring_test_ring,
 	.test_ib = sdma_v2_4_ring_test_ib,
 	.insert_nop = sdma_v2_4_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index e417546e2048..88178d81bd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -460,14 +460,6 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 }
 
-static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, mmHDP_DEBUG0);
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
  *
@@ -1634,7 +1626,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
 	.set_wptr = sdma_v3_0_ring_set_wptr,
 	.emit_frame_size =
 		6 + /* sdma_v3_0_ring_emit_hdp_flush */
-		3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
+		3 + /* hdp invalidate */
 		6 + /* sdma_v3_0_ring_emit_pipeline_sync */
 		12 + /* sdma_v3_0_ring_emit_vm_flush */
 		10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
@@ -1644,7 +1636,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
 	.emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
 	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
 	.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
 	.test_ring = sdma_v3_0_ring_test_ring,
 	.test_ib = sdma_v3_0_ring_test_ib,
 	.insert_nop = sdma_v3_0_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ee919477d7ed..e9b1b834fee1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -375,16 +375,6 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 }
 
-static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-	amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
  *
@@ -1583,7 +1573,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
 	.set_wptr = sdma_v4_0_ring_set_wptr,
 	.emit_frame_size =
 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
-		3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
+		3 + /* hdp invalidate */
 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v4_0_ring_emit_vm_flush */
 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
@@ -1593,7 +1583,6 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
 	.test_ring = sdma_v4_0_ring_test_ring,
 	.test_ib = sdma_v4_0_ring_test_ib,
 	.insert_nop = sdma_v4_0_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 8f9509f6f15b..e59521bacf0b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -75,20 +75,6 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
 
 }
 
-static void si_dma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
-	amdgpu_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL));
-	amdgpu_ring_write(ring, 1);
-}
-
-static void si_dma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
-	amdgpu_ring_write(ring, (0xf << 16) | (HDP_DEBUG0));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * si_dma_ring_emit_fence - emit a fence on the DMA ring
  *
@@ -772,8 +758,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
 	.get_wptr = si_dma_ring_get_wptr,
 	.set_wptr = si_dma_ring_set_wptr,
 	.emit_frame_size =
-		3 + /* si_dma_ring_emit_hdp_flush */
-		3 + /* si_dma_ring_emit_hdp_invalidate */
+		3 + 3 + /* hdp flush / invalidate */
 		6 + /* si_dma_ring_emit_pipeline_sync */
 		SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */
 		9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */
@@ -782,8 +767,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
 	.emit_fence = si_dma_ring_emit_fence,
 	.emit_pipeline_sync = si_dma_ring_emit_pipeline_sync,
 	.emit_vm_flush = si_dma_ring_emit_vm_flush,
-	.emit_hdp_flush = si_dma_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = si_dma_ring_emit_hdp_invalidate,
 	.test_ring = si_dma_ring_test_ring,
 	.test_ib = si_dma_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 8ab10c220910..948bb9437757 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -463,32 +463,6 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
 	amdgpu_ring_write(ring, 2);
 }
 
-/**
- * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp flush.
- */
-static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
-	amdgpu_ring_write(ring, 0);
-}
-
-/**
- * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp invalidate.
- */
-static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * uvd_v4_2_ring_test_ring - register write test
  *
@@ -765,14 +739,10 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
 	.set_wptr = uvd_v4_2_ring_set_wptr,
 	.parse_cs = amdgpu_uvd_ring_parse_cs,
 	.emit_frame_size =
-		2 + /* uvd_v4_2_ring_emit_hdp_flush */
-		2 + /* uvd_v4_2_ring_emit_hdp_invalidate */
 		14, /* uvd_v4_2_ring_emit_fence  x1 no user fence */
 	.emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */
 	.emit_ib = uvd_v4_2_ring_emit_ib,
 	.emit_fence = uvd_v4_2_ring_emit_fence,
-	.emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate,
 	.test_ring = uvd_v4_2_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index c1fe30cdba32..6445d55e7d5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -478,32 +478,6 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
 	amdgpu_ring_write(ring, 2);
 }
 
-/**
- * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp flush.
- */
-static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
-	amdgpu_ring_write(ring, 0);
-}
-
-/**
- * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp invalidate.
- */
-static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * uvd_v5_0_ring_test_ring - register write test
  *
@@ -873,14 +847,10 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
 	.set_wptr = uvd_v5_0_ring_set_wptr,
 	.parse_cs = amdgpu_uvd_ring_parse_cs,
 	.emit_frame_size =
-		2 + /* uvd_v5_0_ring_emit_hdp_flush */
-		2 + /* uvd_v5_0_ring_emit_hdp_invalidate */
 		14, /* uvd_v5_0_ring_emit_fence  x1 no user fence */
 	.emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
 	.emit_ib = uvd_v5_0_ring_emit_ib,
 	.emit_fence = uvd_v5_0_ring_emit_fence,
-	.emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate,
 	.test_ring = uvd_v5_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index b9869f638abe..d0e6c6964452 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -950,32 +950,6 @@ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
 
-/**
- * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp flush.
- */
-static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
-	amdgpu_ring_write(ring, 0);
-}
-
-/**
- * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp invalidate.
- */
-static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * uvd_v6_0_ring_test_ring - register write test
  *
@@ -1543,15 +1517,11 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
 	.set_wptr = uvd_v6_0_ring_set_wptr,
 	.parse_cs = amdgpu_uvd_ring_parse_cs,
 	.emit_frame_size =
-		2 + /* uvd_v6_0_ring_emit_hdp_flush */
-		2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
 		10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 		14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
 	.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
 	.emit_ib = uvd_v6_0_ring_emit_ib,
 	.emit_fence = uvd_v6_0_ring_emit_fence,
-	.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
 	.test_ring = uvd_v6_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
@@ -1569,8 +1539,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
 	.get_wptr = uvd_v6_0_ring_get_wptr,
 	.set_wptr = uvd_v6_0_ring_set_wptr,
 	.emit_frame_size =
-		2 + /* uvd_v6_0_ring_emit_hdp_flush */
-		2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
+		6 + 6 + /* hdp flush / invalidate */
 		10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 		20 + /* uvd_v6_0_ring_emit_vm_flush */
 		14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
@@ -1579,8 +1548,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
 	.emit_fence = uvd_v6_0_ring_emit_fence,
 	.emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
 	.emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
-	.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
 	.test_ring = uvd_v6_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 241e73022cd7..d317c764cc91 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1135,37 +1135,6 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 }
 
-/**
- * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp flush.
- */
-static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
-		mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
-	amdgpu_ring_write(ring, 0);
-}
-
-/**
- * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp invalidate.
- */
-static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * uvd_v7_0_ring_test_ring - register write test
  *
@@ -1693,16 +1662,13 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
 	.get_wptr = uvd_v7_0_ring_get_wptr,
 	.set_wptr = uvd_v7_0_ring_set_wptr,
 	.emit_frame_size =
-		2 + /* uvd_v7_0_ring_emit_hdp_flush */
-		2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
+		6 + 6 + /* hdp flush / invalidate */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* uvd_v7_0_ring_emit_vm_flush */
 		14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
 	.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
 	.emit_ib = uvd_v7_0_ring_emit_ib,
 	.emit_fence = uvd_v7_0_ring_emit_fence,
 	.emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
-	.emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
-	.emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
 	.test_ring = uvd_v7_0_ring_test_ring,
 	.test_ib = amdgpu_uvd_ring_test_ib,
 	.insert_nop = uvd_v7_0_ring_insert_nop,
@@ -1722,6 +1688,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
 	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
 	.emit_frame_size =
+		3 + 3 + /* hdp flush / invalidate */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* uvd_v7_0_enc_ring_emit_vm_flush */
 		5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
 		1, /* uvd_v7_0_enc_ring_insert_end */
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 76cdef29b9d1..44c041a1fe68 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -809,21 +809,6 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
 	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
 }
 
-/**
- * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate
- *
- * @ring: amdgpu_ring pointer
- *
- * Emits an hdp invalidate.
- */
-static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
-	amdgpu_ring_write(ring, 1);
-}
-
 /**
  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
  *
@@ -1096,7 +1081,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
 	.get_wptr = vcn_v1_0_dec_ring_get_wptr,
 	.set_wptr = vcn_v1_0_dec_ring_set_wptr,
 	.emit_frame_size =
-		2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
+		6 + 6 + /* hdp invalidate / flush */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* vcn_v1_0_dec_ring_emit_vm_flush */
 		14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
 		6,
@@ -1104,7 +1089,6 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
 	.emit_ib = vcn_v1_0_dec_ring_emit_ib,
 	.emit_fence = vcn_v1_0_dec_ring_emit_fence,
 	.emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
-	.emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate,
 	.test_ring = amdgpu_vcn_dec_ring_test_ring,
 	.test_ib = amdgpu_vcn_dec_ring_test_ib,
 	.insert_nop = vcn_v1_0_ring_insert_nop,
-- 
2.14.1

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amd-gfx@lists.freedesktop.org
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Re: [PATCH 3/3] drm/amdgpu: remove now superflous *_hdp operation

[Chunming Zhou]

Acked-by: Chunming Zhou <david1.zhou@amd.com> for series.


On 2018年01月22日 18:00, Christian König wrote:
> All HDP invalidation and most flush can now be replaced by the generic
> ASIC function.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  1 -
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  7 +-----
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 -
>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 10 +-------
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    | 39 ++------------------------------
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    | 26 ++-------------------
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 19 ++--------------
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 14 ++----------
>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 10 +-------
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 11 +--------
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 13 +----------
>   drivers/gpu/drm/amd/amdgpu/si_dma.c      | 19 +---------------
>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    | 30 ------------------------
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    | 30 ------------------------
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    | 35 +---------------------------
>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 37 ++----------------------------
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c    | 18 +--------------
>   17 files changed, 18 insertions(+), 302 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index cf55086c9823..9127dbd9a478 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1799,7 +1799,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
>   #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
>   #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
>   #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
> -#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
>   #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
>   #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
>   #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index e87c9952c901..8ea342dc6376 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -225,12 +225,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   #ifdef CONFIG_X86_64
>   	if (!(adev->flags & AMD_IS_APU))
>   #endif
> -	{
> -		if (ring->funcs->emit_hdp_invalidate)
> -			amdgpu_ring_emit_hdp_invalidate(ring);
> -		else
> -			amdgpu_asic_invalidate_hdp(adev, ring);
> -	}
> +		amdgpu_asic_invalidate_hdp(adev, ring);
>   
>   	r = amdgpu_fence_emit(ring, f);
>   	if (r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 12b9a06f4d21..70d05ec7bc07 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -128,7 +128,6 @@ struct amdgpu_ring_funcs {
>   	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
>   			      unsigned pasid, uint64_t pd_addr);
>   	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
> -	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
>   	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
>   				uint32_t gds_base, uint32_t gds_size,
>   				uint32_t gws_base, uint32_t gws_size,
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index 1d32dedb2534..5d18512cd090 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -261,13 +261,6 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
>   }
>   
> -static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
> -	amdgpu_ring_write(ring, mmHDP_DEBUG0);
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
>    *
> @@ -1277,7 +1270,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
>   	.set_wptr = cik_sdma_ring_set_wptr,
>   	.emit_frame_size =
>   		6 + /* cik_sdma_ring_emit_hdp_flush */
> -		3 + /* cik_sdma_ring_emit_hdp_invalidate */
> +		3 + /* hdp invalidate */
>   		6 + /* cik_sdma_ring_emit_pipeline_sync */
>   		CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
>   		9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
> @@ -1287,7 +1280,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
>   	.emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
>   	.emit_vm_flush = cik_sdma_ring_emit_vm_flush,
>   	.emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
>   	.test_ring = cik_sdma_ring_test_ring,
>   	.test_ib = cik_sdma_ring_test_ib,
>   	.insert_nop = cik_sdma_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index e6c3a2465ba4..3517fd9e11c9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1809,17 +1809,6 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
>   	return r;
>   }
>   
> -static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> -{
> -	/* flush hdp cache */
> -	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> -	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
> -				 WRITE_DATA_DST_SEL(0)));
> -	amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL);
> -	amdgpu_ring_write(ring, 0);
> -	amdgpu_ring_write(ring, 0x1);
> -}
> -
>   static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
>   {
>   	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
> @@ -1827,24 +1816,6 @@ static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
>   		EVENT_INDEX(0));
>   }
>   
> -/**
> - * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
> - *
> - * @adev: amdgpu_device pointer
> - * @ridx: amdgpu ring index
> - *
> - * Emits an hdp invalidate on the cp.
> - */
> -static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> -	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
> -				 WRITE_DATA_DST_SEL(0)));
> -	amdgpu_ring_write(ring, mmHDP_DEBUG0);
> -	amdgpu_ring_write(ring, 0);
> -	amdgpu_ring_write(ring, 0x1);
> -}
> -
>   static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
>   				     u64 seq, unsigned flags)
>   {
> @@ -3507,8 +3478,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
>   	.get_wptr = gfx_v6_0_ring_get_wptr,
>   	.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
>   	.emit_frame_size =
> -		5 + /* gfx_v6_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
> +		5 + 5 + /* hdp flush / invalidate */
>   		14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
>   		7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
>   		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
> @@ -3518,8 +3488,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
>   	.emit_fence = gfx_v6_0_ring_emit_fence,
>   	.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
>   	.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
> -	.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v6_0_ring_test_ring,
>   	.test_ib = gfx_v6_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -3535,8 +3503,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
>   	.get_wptr = gfx_v6_0_ring_get_wptr,
>   	.set_wptr = gfx_v6_0_ring_set_wptr_compute,
>   	.emit_frame_size =
> -		5 + /* gfx_v6_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v6_0_ring_emit_hdp_invalidate */
> +		5 + 5 + /* hdp flush / invalidate */
>   		7 + /* gfx_v6_0_ring_emit_pipeline_sync */
>   		SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
>   		14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
> @@ -3545,8 +3512,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
>   	.emit_fence = gfx_v6_0_ring_emit_fence,
>   	.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
>   	.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
> -	.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v6_0_ring_test_ring,
>   	.test_ib = gfx_v6_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 3c2b678436f2..764e068fc2dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2147,26 +2147,6 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
>   		EVENT_INDEX(0));
>   }
>   
> -
> -/**
> - * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
> - *
> - * @adev: amdgpu_device pointer
> - * @ridx: amdgpu ring index
> - *
> - * Emits an hdp invalidate on the cp.
> - */
> -static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> -	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
> -				 WRITE_DATA_DST_SEL(0) |
> -				 WR_CONFIRM));
> -	amdgpu_ring_write(ring, mmHDP_DEBUG0);
> -	amdgpu_ring_write(ring, 0);
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
>    *
> @@ -5110,7 +5090,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
>   	.emit_frame_size =
>   		20 + /* gfx_v7_0_ring_emit_gds_switch */
>   		7 + /* gfx_v7_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
> +		5 + /* hdp invalidate */
>   		12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
>   		7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
>   		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
> @@ -5122,7 +5102,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
>   	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v7_0_ring_test_ring,
>   	.test_ib = gfx_v7_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -5142,7 +5121,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
>   	.emit_frame_size =
>   		20 + /* gfx_v7_0_ring_emit_gds_switch */
>   		7 + /* gfx_v7_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
> +		5 + /* hdp invalidate */
>   		7 + /* gfx_v7_0_ring_emit_pipeline_sync */
>   		CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
>   		7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
> @@ -5153,7 +5132,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
>   	.emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v7_0_ring_test_ring,
>   	.test_ib = gfx_v7_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index e4d209b5c879..5a2e4d5a5bd1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6230,19 +6230,6 @@ static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
>   		EVENT_INDEX(0));
>   }
>   
> -
> -static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> -	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
> -				 WRITE_DATA_DST_SEL(0) |
> -				 WR_CONFIRM));
> -	amdgpu_ring_write(ring, mmHDP_DEBUG0);
> -	amdgpu_ring_write(ring, 0);
> -	amdgpu_ring_write(ring, 1);
> -
> -}
> -
>   static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   				      struct amdgpu_ib *ib,
>   				      unsigned vmid, bool ctx_switch)
> @@ -6887,7 +6874,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
>   	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v8_0_ring_test_ring,
>   	.test_ib = gfx_v8_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -6910,7 +6896,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
>   	.emit_frame_size =
>   		20 + /* gfx_v8_0_ring_emit_gds_switch */
>   		7 + /* gfx_v8_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
> +		5 + /* hdp_invalidate */
>   		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
>   		VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
>   		7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
> @@ -6921,7 +6907,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
>   	.emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v8_0_ring_test_ring,
>   	.test_ib = gfx_v8_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -6941,7 +6926,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
>   	.emit_frame_size =
>   		20 + /* gfx_v8_0_ring_emit_gds_switch */
>   		7 + /* gfx_v8_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v8_0_ring_emit_hdp_invalidate */
> +		5 + /* hdp_invalidate */
>   		7 + /* gfx_v8_0_ring_emit_pipeline_sync */
>   		17 + /* gfx_v8_0_ring_emit_vm_flush */
>   		7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index afdf57206efa..cd2b24ce785b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3585,14 +3585,6 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   			      ref_and_mask, ref_and_mask, 0x20);
>   }
>   
> -static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	struct amdgpu_device *adev = ring->adev;
> -
> -	gfx_v9_0_write_data_to_reg(ring, 0, true,
> -				   SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
> -}
> -
>   static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>                                         struct amdgpu_ib *ib,
>                                         unsigned vmid, bool ctx_switch)
> @@ -4319,7 +4311,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>   	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v9_0_ring_test_ring,
>   	.test_ib = gfx_v9_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -4344,7 +4335,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
>   	.emit_frame_size =
>   		20 + /* gfx_v9_0_ring_emit_gds_switch */
>   		7 + /* gfx_v9_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
> +		5 + /* hdp invalidate */
>   		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
>   		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
> @@ -4355,7 +4346,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
>   	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
>   	.test_ring = gfx_v9_0_ring_test_ring,
>   	.test_ib = gfx_v9_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -4376,7 +4366,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
>   	.emit_frame_size =
>   		20 + /* gfx_v9_0_ring_emit_gds_switch */
>   		7 + /* gfx_v9_0_ring_emit_hdp_flush */
> -		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
> +		5 + /* hdp invalidate */
>   		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */
>   		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 0aa336371816..6a7a82a8c65d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -289,13 +289,6 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
>   }
>   
> -static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
> -			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
> -	amdgpu_ring_write(ring, mmHDP_DEBUG0);
> -	amdgpu_ring_write(ring, 1);
> -}
>   /**
>    * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
>    *
> @@ -1200,7 +1193,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
>   	.set_wptr = sdma_v2_4_ring_set_wptr,
>   	.emit_frame_size =
>   		6 + /* sdma_v2_4_ring_emit_hdp_flush */
> -		3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
> +		3 + /* hdp invalidate */
>   		6 + /* sdma_v2_4_ring_emit_pipeline_sync */
>   		VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
>   		10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
> @@ -1210,7 +1203,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
>   	.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
>   	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
>   	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
>   	.test_ring = sdma_v2_4_ring_test_ring,
>   	.test_ib = sdma_v2_4_ring_test_ib,
>   	.insert_nop = sdma_v2_4_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index e417546e2048..88178d81bd5a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -460,14 +460,6 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
>   }
>   
> -static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
> -			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
> -	amdgpu_ring_write(ring, mmHDP_DEBUG0);
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
>    *
> @@ -1634,7 +1626,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
>   	.set_wptr = sdma_v3_0_ring_set_wptr,
>   	.emit_frame_size =
>   		6 + /* sdma_v3_0_ring_emit_hdp_flush */
> -		3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
> +		3 + /* hdp invalidate */
>   		6 + /* sdma_v3_0_ring_emit_pipeline_sync */
>   		12 + /* sdma_v3_0_ring_emit_vm_flush */
>   		10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
> @@ -1644,7 +1636,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
>   	.emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
>   	.emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
>   	.emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
>   	.test_ring = sdma_v3_0_ring_test_ring,
>   	.test_ib = sdma_v3_0_ring_test_ib,
>   	.insert_nop = sdma_v3_0_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index ee919477d7ed..e9b1b834fee1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -375,16 +375,6 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
>   }
>   
> -static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	struct amdgpu_device *adev = ring->adev;
> -
> -	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
> -			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
> -	amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
>    *
> @@ -1583,7 +1573,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
>   	.set_wptr = sdma_v4_0_ring_set_wptr,
>   	.emit_frame_size =
>   		6 + /* sdma_v4_0_ring_emit_hdp_flush */
> -		3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
> +		3 + /* hdp invalidate */
>   		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v4_0_ring_emit_vm_flush */
>   		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
> @@ -1593,7 +1583,6 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
>   	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
>   	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
>   	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
>   	.test_ring = sdma_v4_0_ring_test_ring,
>   	.test_ib = sdma_v4_0_ring_test_ib,
>   	.insert_nop = sdma_v4_0_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 8f9509f6f15b..e59521bacf0b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -75,20 +75,6 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
>   
>   }
>   
> -static void si_dma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
> -	amdgpu_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
> -static void si_dma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
> -	amdgpu_ring_write(ring, (0xf << 16) | (HDP_DEBUG0));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * si_dma_ring_emit_fence - emit a fence on the DMA ring
>    *
> @@ -772,8 +758,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
>   	.get_wptr = si_dma_ring_get_wptr,
>   	.set_wptr = si_dma_ring_set_wptr,
>   	.emit_frame_size =
> -		3 + /* si_dma_ring_emit_hdp_flush */
> -		3 + /* si_dma_ring_emit_hdp_invalidate */
> +		3 + 3 + /* hdp flush / invalidate */
>   		6 + /* si_dma_ring_emit_pipeline_sync */
>   		SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */
>   		9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */
> @@ -782,8 +767,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
>   	.emit_fence = si_dma_ring_emit_fence,
>   	.emit_pipeline_sync = si_dma_ring_emit_pipeline_sync,
>   	.emit_vm_flush = si_dma_ring_emit_vm_flush,
> -	.emit_hdp_flush = si_dma_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = si_dma_ring_emit_hdp_invalidate,
>   	.test_ring = si_dma_ring_test_ring,
>   	.test_ib = si_dma_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 8ab10c220910..948bb9437757 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -463,32 +463,6 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
>   	amdgpu_ring_write(ring, 2);
>   }
>   
> -/**
> - * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp flush.
> - */
> -static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
> -	amdgpu_ring_write(ring, 0);
> -}
> -
> -/**
> - * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp invalidate.
> - */
> -static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * uvd_v4_2_ring_test_ring - register write test
>    *
> @@ -765,14 +739,10 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
>   	.set_wptr = uvd_v4_2_ring_set_wptr,
>   	.parse_cs = amdgpu_uvd_ring_parse_cs,
>   	.emit_frame_size =
> -		2 + /* uvd_v4_2_ring_emit_hdp_flush */
> -		2 + /* uvd_v4_2_ring_emit_hdp_invalidate */
>   		14, /* uvd_v4_2_ring_emit_fence  x1 no user fence */
>   	.emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */
>   	.emit_ib = uvd_v4_2_ring_emit_ib,
>   	.emit_fence = uvd_v4_2_ring_emit_fence,
> -	.emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate,
>   	.test_ring = uvd_v4_2_ring_test_ring,
>   	.test_ib = amdgpu_uvd_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index c1fe30cdba32..6445d55e7d5a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -478,32 +478,6 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
>   	amdgpu_ring_write(ring, 2);
>   }
>   
> -/**
> - * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp flush.
> - */
> -static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
> -	amdgpu_ring_write(ring, 0);
> -}
> -
> -/**
> - * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp invalidate.
> - */
> -static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * uvd_v5_0_ring_test_ring - register write test
>    *
> @@ -873,14 +847,10 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
>   	.set_wptr = uvd_v5_0_ring_set_wptr,
>   	.parse_cs = amdgpu_uvd_ring_parse_cs,
>   	.emit_frame_size =
> -		2 + /* uvd_v5_0_ring_emit_hdp_flush */
> -		2 + /* uvd_v5_0_ring_emit_hdp_invalidate */
>   		14, /* uvd_v5_0_ring_emit_fence  x1 no user fence */
>   	.emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
>   	.emit_ib = uvd_v5_0_ring_emit_ib,
>   	.emit_fence = uvd_v5_0_ring_emit_fence,
> -	.emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate,
>   	.test_ring = uvd_v5_0_ring_test_ring,
>   	.test_ib = amdgpu_uvd_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index b9869f638abe..d0e6c6964452 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -950,32 +950,6 @@ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
>   	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
>   }
>   
> -/**
> - * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp flush.
> - */
> -static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
> -	amdgpu_ring_write(ring, 0);
> -}
> -
> -/**
> - * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp invalidate.
> - */
> -static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * uvd_v6_0_ring_test_ring - register write test
>    *
> @@ -1543,15 +1517,11 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
>   	.set_wptr = uvd_v6_0_ring_set_wptr,
>   	.parse_cs = amdgpu_uvd_ring_parse_cs,
>   	.emit_frame_size =
> -		2 + /* uvd_v6_0_ring_emit_hdp_flush */
> -		2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
>   		10 + /* uvd_v6_0_ring_emit_pipeline_sync */
>   		14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
>   	.emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
>   	.emit_ib = uvd_v6_0_ring_emit_ib,
>   	.emit_fence = uvd_v6_0_ring_emit_fence,
> -	.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
>   	.test_ring = uvd_v6_0_ring_test_ring,
>   	.test_ib = amdgpu_uvd_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> @@ -1569,8 +1539,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>   	.get_wptr = uvd_v6_0_ring_get_wptr,
>   	.set_wptr = uvd_v6_0_ring_set_wptr,
>   	.emit_frame_size =
> -		2 + /* uvd_v6_0_ring_emit_hdp_flush */
> -		2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
> +		6 + 6 + /* hdp flush / invalidate */
>   		10 + /* uvd_v6_0_ring_emit_pipeline_sync */
>   		20 + /* uvd_v6_0_ring_emit_vm_flush */
>   		14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
> @@ -1579,8 +1548,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>   	.emit_fence = uvd_v6_0_ring_emit_fence,
>   	.emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
>   	.emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
> -	.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
>   	.test_ring = uvd_v6_0_ring_test_ring,
>   	.test_ib = amdgpu_uvd_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 241e73022cd7..d317c764cc91 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1135,37 +1135,6 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
>   	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
>   }
>   
> -/**
> - * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp flush.
> - */
> -static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> -{
> -	struct amdgpu_device *adev = ring->adev;
> -
> -	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
> -		mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
> -	amdgpu_ring_write(ring, 0);
> -}
> -
> -/**
> - * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp invalidate.
> - */
> -static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	struct amdgpu_device *adev = ring->adev;
> -
> -	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * uvd_v7_0_ring_test_ring - register write test
>    *
> @@ -1693,16 +1662,13 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
>   	.get_wptr = uvd_v7_0_ring_get_wptr,
>   	.set_wptr = uvd_v7_0_ring_set_wptr,
>   	.emit_frame_size =
> -		2 + /* uvd_v7_0_ring_emit_hdp_flush */
> -		2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
> +		6 + 6 + /* hdp flush / invalidate */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* uvd_v7_0_ring_emit_vm_flush */
>   		14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
>   	.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
>   	.emit_ib = uvd_v7_0_ring_emit_ib,
>   	.emit_fence = uvd_v7_0_ring_emit_fence,
>   	.emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
> -	.emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
> -	.emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
>   	.test_ring = uvd_v7_0_ring_test_ring,
>   	.test_ib = amdgpu_uvd_ring_test_ib,
>   	.insert_nop = uvd_v7_0_ring_insert_nop,
> @@ -1722,6 +1688,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
>   	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
>   	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
>   	.emit_frame_size =
> +		3 + 3 + /* hdp flush / invalidate */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* uvd_v7_0_enc_ring_emit_vm_flush */
>   		5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
>   		1, /* uvd_v7_0_enc_ring_insert_end */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 76cdef29b9d1..44c041a1fe68 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -809,21 +809,6 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
>   	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
>   }
>   
> -/**
> - * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate
> - *
> - * @ring: amdgpu_ring pointer
> - *
> - * Emits an hdp invalidate.
> - */
> -static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
> -{
> -	struct amdgpu_device *adev = ring->adev;
> -
> -	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
> -	amdgpu_ring_write(ring, 1);
> -}
> -
>   /**
>    * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
>    *
> @@ -1096,7 +1081,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
>   	.get_wptr = vcn_v1_0_dec_ring_get_wptr,
>   	.set_wptr = vcn_v1_0_dec_ring_set_wptr,
>   	.emit_frame_size =
> -		2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
> +		6 + 6 + /* hdp invalidate / flush */
>   		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* vcn_v1_0_dec_ring_emit_vm_flush */
>   		14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
>   		6,
> @@ -1104,7 +1089,6 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
>   	.emit_ib = vcn_v1_0_dec_ring_emit_ib,
>   	.emit_fence = vcn_v1_0_dec_ring_emit_fence,
>   	.emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
> -	.emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate,
>   	.test_ring = amdgpu_vcn_dec_ring_test_ring,
>   	.test_ib = amdgpu_vcn_dec_ring_test_ib,
>   	.insert_nop = vcn_v1_0_ring_insert_nop,

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