* [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup
@ 2018-06-25 17:42 Alex Deucher
[not found] ` <20180625174235.29172-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2018-06-25 17:42 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Set the me instance in early init and use that rather than
calculating the instance based on the ring pointer.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++++++--------
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 +++++++++++------------
4 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index a7576255cc30..dbd553a8d584 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
- return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
+ return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
}
/**
@@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
- WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
+ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
(lower_32_bits(ring->wptr) << 2) & 0x3fffc);
}
@@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
u32 ref_and_mask;
- if (ring == &ring->adev->sdma.instance[0].ring)
+ if (ring->me == 0)
ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
else
ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
@@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
+ adev->sdma.instance[i].ring.me = i;
+ }
}
static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index c7190c39c4f5..cee4fae76d20 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
- u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
+ u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
return wptr;
}
@@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
- WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
+ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
}
static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
u32 ref_and_mask = 0;
- if (ring == &ring->adev->sdma.instance[0].ring)
+ if (ring->me == 0)
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
else
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
+ adev->sdma.instance[i].ring.me = i;
+ }
}
static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index aa9ab299fd32..99616dd9594f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
/* XXX check if swapping is necessary on BE */
wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
} else {
- int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
-
- wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
+ wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
}
return wptr;
@@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
} else {
- int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
-
- WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
+ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
}
}
@@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
u32 ref_and_mask = 0;
- if (ring == &ring->adev->sdma.instance[0].ring)
+ if (ring->me == 0)
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
else
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
+ adev->sdma.instance[i].ring.me = i;
+ }
}
static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ca53b3fba422..572ca63cf676 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
u32 lowbit, highbit;
- int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
- lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
- highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
+ lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
+ highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
- me, highbit, lowbit);
+ ring->me, highbit, lowbit);
wptr = highbit;
wptr = wptr << 32;
wptr |= lowbit;
@@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
ring->doorbell_index, ring->wptr << 2);
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
} else {
- int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
-
DRM_DEBUG("Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
- me,
+ ring->me,
lower_32_bits(ring->wptr << 2),
- me,
+ ring->me,
upper_32_bits(ring->wptr << 2));
- WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
- WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
+ WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
+ WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
}
}
@@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
u32 ref_and_mask = 0;
const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
- if (ring == &ring->adev->sdma.instance[0].ring)
+ if (ring->me == 0)
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
else
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
@@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
+ adev->sdma.instance[i].ring.me = i;
+ }
}
static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
--
2.13.6
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/amdgpu/vce: simplify vce instance setup
[not found] ` <20180625174235.29172-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-25 17:42 ` Alex Deucher
2018-06-29 14:58 ` [PATCH 1/2] drm/amdgpu/sdma: simplify sdma " Alex Deucher
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2018-06-25 17:42 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Set the me instance in early init and use that rather than
calculating the instance based on the ring pointer.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 10 ++++++----
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 20 ++++++++++++--------
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 16 +++++++++-------
3 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 47f70827195b..d48e877b682e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -56,7 +56,7 @@ static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
return RREG32(mmVCE_RB_RPTR);
else
return RREG32(mmVCE_RB_RPTR2);
@@ -73,7 +73,7 @@ static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
return RREG32(mmVCE_RB_WPTR);
else
return RREG32(mmVCE_RB_WPTR2);
@@ -90,7 +90,7 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
else
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
@@ -627,8 +627,10 @@ static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
- for (i = 0; i < adev->vce.num_rings; i++)
+ for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
+ adev->vce.ring[i].me = i;
+ }
}
static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 0999c843f623..23927cdfbc23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -86,9 +86,9 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
v = RREG32(mmVCE_RB_RPTR);
- else if (ring == &adev->vce.ring[1])
+ else if (ring->me == 1)
v = RREG32(mmVCE_RB_RPTR2);
else
v = RREG32(mmVCE_RB_RPTR3);
@@ -118,9 +118,9 @@ static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
v = RREG32(mmVCE_RB_WPTR);
- else if (ring == &adev->vce.ring[1])
+ else if (ring->me == 1)
v = RREG32(mmVCE_RB_WPTR2);
else
v = RREG32(mmVCE_RB_WPTR3);
@@ -149,9 +149,9 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
- else if (ring == &adev->vce.ring[1])
+ else if (ring->me == 1)
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
else
WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
@@ -942,12 +942,16 @@ static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
int i;
if (adev->asic_type >= CHIP_STONEY) {
- for (i = 0; i < adev->vce.num_rings; i++)
+ for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
+ adev->vce.ring[i].me = i;
+ }
DRM_INFO("VCE enabled in VM mode\n");
} else {
- for (i = 0; i < adev->vce.num_rings; i++)
+ for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
+ adev->vce.ring[i].me = i;
+ }
DRM_INFO("VCE enabled in physical mode\n");
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 8fd1b742985a..575bf9709389 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -60,9 +60,9 @@ static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
- else if (ring == &adev->vce.ring[1])
+ else if (ring->me == 1)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
else
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
@@ -82,9 +82,9 @@ static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
if (ring->use_doorbell)
return adev->wb.wb[ring->wptr_offs];
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
- else if (ring == &adev->vce.ring[1])
+ else if (ring->me == 1)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
else
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
@@ -108,10 +108,10 @@ static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
return;
}
- if (ring == &adev->vce.ring[0])
+ if (ring->me == 0)
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
lower_32_bits(ring->wptr));
- else if (ring == &adev->vce.ring[1])
+ else if (ring->me == 1)
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
lower_32_bits(ring->wptr));
else
@@ -1088,8 +1088,10 @@ static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
- for (i = 0; i < adev->vce.num_rings; i++)
+ for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs;
+ adev->vce.ring[i].me = i;
+ }
DRM_INFO("VCE enabled in VM mode\n");
}
--
2.13.6
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup
[not found] ` <20180625174235.29172-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-06-25 17:42 ` [PATCH 2/2] drm/amdgpu/vce: simplify vce " Alex Deucher
@ 2018-06-29 14:58 ` Alex Deucher
[not found] ` <CADnq5_M5DnXH9rF9HgKhPi32FS5PdKj-OjbM13P0uKSJ4Y3sHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-02 12:34 ` Christian König
2018-07-03 13:38 ` James Zhu
3 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2018-06-29 14:58 UTC (permalink / raw)
To: amd-gfx list; +Cc: Alex Deucher
Ping on this series?
On Mon, Jun 25, 2018 at 1:42 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Set the me instance in early init and use that rather than
> calculating the instance based on the ring pointer.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++++++--------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 +++++++++++------------
> 4 files changed, 29 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index a7576255cc30..dbd553a8d584 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
> static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
> + return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
> }
>
> /**
> @@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
> (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
> }
>
> @@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
> u32 ref_and_mask;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
> else
> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
> @@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index c7190c39c4f5..cee4fae76d20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
> static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> - u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
> + u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
>
> return wptr;
> }
> @@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
> }
>
> static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> @@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> {
> u32 ref_and_mask = 0;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
> else
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
> @@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index aa9ab299fd32..99616dd9594f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
> /* XXX check if swapping is necessary on BE */
> wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> - wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
> + wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
> }
>
> return wptr;
> @@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>
> WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
> }
> }
>
> @@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> {
> u32 ref_and_mask = 0;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
> else
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
> @@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index ca53b3fba422..572ca63cf676 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
> DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
> } else {
> u32 lowbit, highbit;
> - int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
> - highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
> + lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
> + highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>
> DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
> - me, highbit, lowbit);
> + ring->me, highbit, lowbit);
> wptr = highbit;
> wptr = wptr << 32;
> wptr |= lowbit;
> @@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
> ring->doorbell_index, ring->wptr << 2);
> WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> DRM_DEBUG("Not using doorbell -- "
> "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
> "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
> - me,
> + ring->me,
> lower_32_bits(ring->wptr << 2),
> - me,
> + ring->me,
> upper_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> }
> }
>
> @@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> u32 ref_and_mask = 0;
> const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
> else
> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
> @@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
> --
> 2.13.6
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup
[not found] ` <CADnq5_M5DnXH9rF9HgKhPi32FS5PdKj-OjbM13P0uKSJ4Y3sHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-06-29 16:52 ` Leo Liu
[not found] ` <4487ebe1-8046-a678-1f79-3280f707ee17-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Leo Liu @ 2018-06-29 16:52 UTC (permalink / raw)
To: Alex Deucher, amd-gfx list; +Cc: Alex Deucher
Looks good to me. Both patches are
Reviewed-by: Leo Liu <leo.liu@amd.com>
On 06/29/2018 10:58 AM, Alex Deucher wrote:
> Ping on this series?
>
> On Mon, Jun 25, 2018 at 1:42 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
>> Set the me instance in early init and use that rather than
>> calculating the instance based on the ring pointer.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12 ++++++------
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 ++++++------
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++++++--------
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 +++++++++++------------
>> 4 files changed, 29 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index a7576255cc30..dbd553a8d584 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
>> static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>>
>> - return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
>> + return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
>> }
>>
>> /**
>> @@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
>> static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>>
>> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
>> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
>> (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
>> }
>>
>> @@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>> SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
>> u32 ref_and_mask;
>>
>> - if (ring == &ring->adev->sdma.instance[0].ring)
>> + if (ring->me == 0)
>> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
>> else
>> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
>> @@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
>> {
>> int i;
>>
>> - for (i = 0; i < adev->sdma.num_instances; i++)
>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>> adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
>> + adev->sdma.instance[i].ring.me = i;
>> + }
>> }
>>
>> static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> index c7190c39c4f5..cee4fae76d20 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> @@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
>> static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>> - u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
>> + u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
>>
>> return wptr;
>> }
>> @@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
>> static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>>
>> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
>> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
>> }
>>
>> static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
>> @@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>> {
>> u32 ref_and_mask = 0;
>>
>> - if (ring == &ring->adev->sdma.instance[0].ring)
>> + if (ring->me == 0)
>> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
>> else
>> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
>> @@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
>> {
>> int i;
>>
>> - for (i = 0; i < adev->sdma.num_instances; i++)
>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>> adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
>> + adev->sdma.instance[i].ring.me = i;
>> + }
>> }
>>
>> static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> index aa9ab299fd32..99616dd9594f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> @@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
>> /* XXX check if swapping is necessary on BE */
>> wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
>> } else {
>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>> -
>> - wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
>> + wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
>> }
>>
>> return wptr;
>> @@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>>
>> WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
>> } else {
>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>> -
>> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
>> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
>> }
>> }
>>
>> @@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>> {
>> u32 ref_and_mask = 0;
>>
>> - if (ring == &ring->adev->sdma.instance[0].ring)
>> + if (ring->me == 0)
>> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
>> else
>> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
>> @@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
>> {
>> int i;
>>
>> - for (i = 0; i < adev->sdma.num_instances; i++)
>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>> adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
>> + adev->sdma.instance[i].ring.me = i;
>> + }
>> }
>>
>> static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index ca53b3fba422..572ca63cf676 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
>> DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
>> } else {
>> u32 lowbit, highbit;
>> - int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>>
>> - lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
>> - highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>> + lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
>> + highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>>
>> DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
>> - me, highbit, lowbit);
>> + ring->me, highbit, lowbit);
>> wptr = highbit;
>> wptr = wptr << 32;
>> wptr |= lowbit;
>> @@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
>> ring->doorbell_index, ring->wptr << 2);
>> WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
>> } else {
>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>> -
>> DRM_DEBUG("Not using doorbell -- "
>> "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
>> "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
>> - me,
>> + ring->me,
>> lower_32_bits(ring->wptr << 2),
>> - me,
>> + ring->me,
>> upper_32_bits(ring->wptr << 2));
>> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
>> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
>> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
>> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
>> }
>> }
>>
>> @@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>> u32 ref_and_mask = 0;
>> const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
>>
>> - if (ring == &ring->adev->sdma.instance[0].ring)
>> + if (ring->me == 0)
>> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
>> else
>> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
>> @@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
>> {
>> int i;
>>
>> - for (i = 0; i < adev->sdma.num_instances; i++)
>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>> adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
>> + adev->sdma.instance[i].ring.me = i;
>> + }
>> }
>>
>> static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
>> --
>> 2.13.6
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup
[not found] ` <4487ebe1-8046-a678-1f79-3280f707ee17-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-29 19:14 ` Alex Deucher
0 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2018-06-29 19:14 UTC (permalink / raw)
To: Leo Liu; +Cc: Alex Deucher, amd-gfx list
On Fri, Jun 29, 2018 at 12:52 PM, Leo Liu <leo.liu@amd.com> wrote:
> Looks good to me. Both patches are
>
> Reviewed-by: Leo Liu <leo.liu@amd.com>
>
Thanks. Can you look at the UVD patch as well?
https://patchwork.freedesktop.org/patch/233507/
Alex
>
>
> On 06/29/2018 10:58 AM, Alex Deucher wrote:
>>
>> Ping on this series?
>>
>> On Mon, Jun 25, 2018 at 1:42 PM, Alex Deucher <alexdeucher@gmail.com>
>> wrote:
>>>
>>> Set the me instance in early init and use that rather than
>>> calculating the instance based on the ring pointer.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12 ++++++------
>>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 ++++++------
>>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++++++--------
>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 +++++++++++------------
>>> 4 files changed, 29 insertions(+), 32 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>>> index a7576255cc30..dbd553a8d584 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>>> @@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct
>>> amdgpu_ring *ring)
>>> static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
>>> {
>>> struct amdgpu_device *adev = ring->adev;
>>> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>>>
>>> - return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc)
>>> >> 2;
>>> + return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) &
>>> 0x3fffc) >> 2;
>>> }
>>>
>>> /**
>>> @@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct
>>> amdgpu_ring *ring)
>>> static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
>>> {
>>> struct amdgpu_device *adev = ring->adev;
>>> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>>>
>>> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
>>> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
>>> (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
>>> }
>>>
>>> @@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct
>>> amdgpu_ring *ring)
>>> SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
>>> u32 ref_and_mask;
>>>
>>> - if (ring == &ring->adev->sdma.instance[0].ring)
>>> + if (ring->me == 0)
>>> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
>>> else
>>> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
>>> @@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct
>>> amdgpu_device *adev)
>>> {
>>> int i;
>>>
>>> - for (i = 0; i < adev->sdma.num_instances; i++)
>>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>>> adev->sdma.instance[i].ring.funcs =
>>> &cik_sdma_ring_funcs;
>>> + adev->sdma.instance[i].ring.me = i;
>>> + }
>>> }
>>>
>>> static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>>> index c7190c39c4f5..cee4fae76d20 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>>> @@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct
>>> amdgpu_ring *ring)
>>> static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
>>> {
>>> struct amdgpu_device *adev = ring->adev;
>>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>>> - u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
>>> + u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me])
>>> >> 2;
>>>
>>> return wptr;
>>> }
>>> @@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct
>>> amdgpu_ring *ring)
>>> static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
>>> {
>>> struct amdgpu_device *adev = ring->adev;
>>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>>>
>>> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
>>> lower_32_bits(ring->wptr) << 2);
>>> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
>>> lower_32_bits(ring->wptr) << 2);
>>> }
>>>
>>> static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring,
>>> uint32_t count)
>>> @@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct
>>> amdgpu_ring *ring)
>>> {
>>> u32 ref_and_mask = 0;
>>>
>>> - if (ring == &ring->adev->sdma.instance[0].ring)
>>> + if (ring->me == 0)
>>> ref_and_mask = REG_SET_FIELD(ref_and_mask,
>>> GPU_HDP_FLUSH_DONE, SDMA0, 1);
>>> else
>>> ref_and_mask = REG_SET_FIELD(ref_and_mask,
>>> GPU_HDP_FLUSH_DONE, SDMA1, 1);
>>> @@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct
>>> amdgpu_device *adev)
>>> {
>>> int i;
>>>
>>> - for (i = 0; i < adev->sdma.num_instances; i++)
>>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>>> adev->sdma.instance[i].ring.funcs =
>>> &sdma_v2_4_ring_funcs;
>>> + adev->sdma.instance[i].ring.me = i;
>>> + }
>>> }
>>>
>>> static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>>> index aa9ab299fd32..99616dd9594f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>>> @@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct
>>> amdgpu_ring *ring)
>>> /* XXX check if swapping is necessary on BE */
>>> wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
>>> } else {
>>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0
>>> : 1;
>>> -
>>> - wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >>
>>> 2;
>>> + wptr = RREG32(mmSDMA0_GFX_RB_WPTR +
>>> sdma_offsets[ring->me]) >> 2;
>>> }
>>>
>>> return wptr;
>>> @@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct
>>> amdgpu_ring *ring)
>>>
>>> WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
>>> } else {
>>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0
>>> : 1;
>>> -
>>> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
>>> lower_32_bits(ring->wptr) << 2);
>>> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
>>> lower_32_bits(ring->wptr) << 2);
>>> }
>>> }
>>>
>>> @@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct
>>> amdgpu_ring *ring)
>>> {
>>> u32 ref_and_mask = 0;
>>>
>>> - if (ring == &ring->adev->sdma.instance[0].ring)
>>> + if (ring->me == 0)
>>> ref_and_mask = REG_SET_FIELD(ref_and_mask,
>>> GPU_HDP_FLUSH_DONE, SDMA0, 1);
>>> else
>>> ref_and_mask = REG_SET_FIELD(ref_and_mask,
>>> GPU_HDP_FLUSH_DONE, SDMA1, 1);
>>> @@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct
>>> amdgpu_device *adev)
>>> {
>>> int i;
>>>
>>> - for (i = 0; i < adev->sdma.num_instances; i++)
>>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>>> adev->sdma.instance[i].ring.funcs =
>>> &sdma_v3_0_ring_funcs;
>>> + adev->sdma.instance[i].ring.me = i;
>>> + }
>>> }
>>>
>>> static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> index ca53b3fba422..572ca63cf676 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> @@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct
>>> amdgpu_ring *ring)
>>> DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n",
>>> wptr);
>>> } else {
>>> u32 lowbit, highbit;
>>> - int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>>>
>>> - lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me,
>>> mmSDMA0_GFX_RB_WPTR)) >> 2;
>>> - highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me,
>>> mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>>> + lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
>>> mmSDMA0_GFX_RB_WPTR)) >> 2;
>>> + highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
>>> mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>>>
>>> DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
>>> - me, highbit, lowbit);
>>> + ring->me, highbit, lowbit);
>>> wptr = highbit;
>>> wptr = wptr << 32;
>>> wptr |= lowbit;
>>> @@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct
>>> amdgpu_ring *ring)
>>> ring->doorbell_index, ring->wptr << 2);
>>> WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
>>> } else {
>>> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0
>>> : 1;
>>> -
>>> DRM_DEBUG("Not using doorbell -- "
>>> "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
>>> "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
>>> - me,
>>> + ring->me,
>>> lower_32_bits(ring->wptr << 2),
>>> - me,
>>> + ring->me,
>>> upper_32_bits(ring->wptr << 2));
>>> - WREG32(sdma_v4_0_get_reg_offset(adev, me,
>>> mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
>>> - WREG32(sdma_v4_0_get_reg_offset(adev, me,
>>> mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
>>> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
>>> mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
>>> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me,
>>> mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
>>> }
>>> }
>>>
>>> @@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct
>>> amdgpu_ring *ring)
>>> u32 ref_and_mask = 0;
>>> const struct nbio_hdp_flush_reg *nbio_hf_reg =
>>> adev->nbio_funcs->hdp_flush_reg;
>>>
>>> - if (ring == &ring->adev->sdma.instance[0].ring)
>>> + if (ring->me == 0)
>>> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
>>> else
>>> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
>>> @@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct
>>> amdgpu_device *adev)
>>> {
>>> int i;
>>>
>>> - for (i = 0; i < adev->sdma.num_instances; i++)
>>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>>> adev->sdma.instance[i].ring.funcs =
>>> &sdma_v4_0_ring_funcs;
>>> + adev->sdma.instance[i].ring.me = i;
>>> + }
>>> }
>>>
>>> static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
>>> --
>>> 2.13.6
>>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup
[not found] ` <20180625174235.29172-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-06-25 17:42 ` [PATCH 2/2] drm/amdgpu/vce: simplify vce " Alex Deucher
2018-06-29 14:58 ` [PATCH 1/2] drm/amdgpu/sdma: simplify sdma " Alex Deucher
@ 2018-07-02 12:34 ` Christian König
2018-07-03 13:38 ` James Zhu
3 siblings, 0 replies; 7+ messages in thread
From: Christian König @ 2018-07-02 12:34 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Am 25.06.2018 um 19:42 schrieb Alex Deucher:
> Set the me instance in early init and use that rather than
> calculating the instance based on the ring pointer.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com> for the series.
> ---
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++++++--------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 +++++++++++------------
> 4 files changed, 29 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index a7576255cc30..dbd553a8d584 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
> static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
> + return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
> }
>
> /**
> @@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
> (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
> }
>
> @@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
> u32 ref_and_mask;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
> else
> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
> @@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index c7190c39c4f5..cee4fae76d20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
> static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> - u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
> + u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
>
> return wptr;
> }
> @@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
> }
>
> static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> @@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> {
> u32 ref_and_mask = 0;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
> else
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
> @@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index aa9ab299fd32..99616dd9594f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
> /* XXX check if swapping is necessary on BE */
> wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> - wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
> + wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
> }
>
> return wptr;
> @@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>
> WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
> }
> }
>
> @@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> {
> u32 ref_and_mask = 0;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
> else
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
> @@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index ca53b3fba422..572ca63cf676 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
> DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
> } else {
> u32 lowbit, highbit;
> - int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
> - highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
> + lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
> + highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>
> DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
> - me, highbit, lowbit);
> + ring->me, highbit, lowbit);
> wptr = highbit;
> wptr = wptr << 32;
> wptr |= lowbit;
> @@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
> ring->doorbell_index, ring->wptr << 2);
> WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> DRM_DEBUG("Not using doorbell -- "
> "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
> "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
> - me,
> + ring->me,
> lower_32_bits(ring->wptr << 2),
> - me,
> + ring->me,
> upper_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> }
> }
>
> @@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> u32 ref_and_mask = 0;
> const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
> else
> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
> @@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup
[not found] ` <20180625174235.29172-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-07-02 12:34 ` Christian König
@ 2018-07-03 13:38 ` James Zhu
3 siblings, 0 replies; 7+ messages in thread
From: James Zhu @ 2018-07-03 13:38 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Reviewed-by: James Zhu <James.Zhu@amd.com> for the series
On 2018-06-25 01:42 PM, Alex Deucher wrote:
> Set the me instance in early init and use that rather than
> calculating the instance based on the ring pointer.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 14 ++++++--------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 +++++++++++------------
> 4 files changed, 29 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index a7576255cc30..dbd553a8d584 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
> static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
> + return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
> }
>
> /**
> @@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
> (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
> }
>
> @@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
> u32 ref_and_mask;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
> else
> ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
> @@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index c7190c39c4f5..cee4fae76d20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
> static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> - u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
> + u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
>
> return wptr;
> }
> @@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
> }
>
> static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> @@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> {
> u32 ref_and_mask = 0;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
> else
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
> @@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index aa9ab299fd32..99616dd9594f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
> /* XXX check if swapping is necessary on BE */
> wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> - wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
> + wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
> }
>
> return wptr;
> @@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>
> WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
> }
> }
>
> @@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> {
> u32 ref_and_mask = 0;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
> else
> ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
> @@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index ca53b3fba422..572ca63cf676 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
> DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
> } else {
> u32 lowbit, highbit;
> - int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>
> - lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
> - highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
> + lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
> + highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
>
> DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
> - me, highbit, lowbit);
> + ring->me, highbit, lowbit);
> wptr = highbit;
> wptr = wptr << 32;
> wptr |= lowbit;
> @@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
> ring->doorbell_index, ring->wptr << 2);
> WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
> } else {
> - int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> -
> DRM_DEBUG("Not using doorbell -- "
> "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
> "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
> - me,
> + ring->me,
> lower_32_bits(ring->wptr << 2),
> - me,
> + ring->me,
> upper_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> - WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
> + WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
> }
> }
>
> @@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> u32 ref_and_mask = 0;
> const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
>
> - if (ring == &ring->adev->sdma.instance[0].ring)
> + if (ring->me == 0)
> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
> else
> ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
> @@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
> {
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
> + adev->sdma.instance[i].ring.me = i;
> + }
> }
>
> static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-07-03 13:38 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-06-25 17:42 [PATCH 1/2] drm/amdgpu/sdma: simplify sdma instance setup Alex Deucher
[not found] ` <20180625174235.29172-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-06-25 17:42 ` [PATCH 2/2] drm/amdgpu/vce: simplify vce " Alex Deucher
2018-06-29 14:58 ` [PATCH 1/2] drm/amdgpu/sdma: simplify sdma " Alex Deucher
[not found] ` <CADnq5_M5DnXH9rF9HgKhPi32FS5PdKj-OjbM13P0uKSJ4Y3sHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-06-29 16:52 ` Leo Liu
[not found] ` <4487ebe1-8046-a678-1f79-3280f707ee17-5C7GfCeVMHo@public.gmane.org>
2018-06-29 19:14 ` Alex Deucher
2018-07-02 12:34 ` Christian König
2018-07-03 13:38 ` James Zhu
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