[PATCH libdrm 1/5] [libdrm] sync drm.h for syncobj part

[PATCH libdrm 1/5] [libdrm] sync drm.h for syncobj part

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/drm.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index f0bd91de..d1688269 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -695,6 +695,7 @@ struct drm_prime_handle {
 struct drm_syncobj_create {
 	__u32 handle;
 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
+#define DRM_SYNCOBJ_CREATE_TYPE_TIMELINE (1 << 1)
 	__u32 flags;
 };
 
@@ -725,12 +726,32 @@ struct drm_syncobj_wait {
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_wait {
+        __u64 handles;
+        /* wait on specific timeline point for every handles*/
+        __u64 points;
+        /* absolute timeout */
+        __s64 timeout_nsec;
+        __u32 count_handles;
+        __u32 flags;
+        __u32 first_signaled; /* only valid when not waiting all */
+        __u32 pad;
+};
+
 struct drm_syncobj_array {
 	__u64 handles;
 	__u32 count_handles;
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_query {
+        __u64 handles;
+        /* points are timeline syncobjs payloads returned by query ioctl */
+        __u64 points;
+        __u32 count_handles;
+        __u32 pad;
+};
+
 /* Query current scanout sequence number */
 struct drm_crtc_get_sequence {
 	__u32 crtc_id;		/* requested crtc_id */
@@ -887,6 +908,9 @@ extern "C" {
 #define DRM_IOCTL_MODE_GET_LEASE	DRM_IOWR(0xC8, struct drm_mode_get_lease)
 #define DRM_IOCTL_MODE_REVOKE_LEASE	DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
 
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERY         DRM_IOWR(0xCB, struct drm_syncobj_timeline_query)
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
-- 
2.17.1

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[PATCH libdrm 4/5] [libdrm]: wrap syncobj timeline query and wait for amdgpu

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 amdgpu/amdgpu-symbol-check |  2 ++
 amdgpu/amdgpu.h            | 39 ++++++++++++++++++++++++++++++++++++++
 amdgpu/amdgpu_cs.c         | 24 +++++++++++++++++++++++
 3 files changed, 65 insertions(+)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 58646e85..4f91be54 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -50,6 +50,8 @@ amdgpu_cs_syncobj_import_sync_file
 amdgpu_cs_syncobj_reset
 amdgpu_cs_syncobj_signal
 amdgpu_cs_syncobj_wait
+amdgpu_cs_syncobj_timeline_wait
+amdgpu_cs_syncobj_query
 amdgpu_cs_wait_fences
 amdgpu_cs_wait_semaphore
 amdgpu_device_deinitialize
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index dc51659a..330658a0 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1489,6 +1489,45 @@ int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
 			   int64_t timeout_nsec, unsigned flags,
 			   uint32_t *first_signaled);
 
+/**
+ *  Wait for one or all sync objects on their points to signal.
+ *
+ * \param   dev	    - \c [in] self-explanatory
+ * \param   handles - \c [in] array of sync object handles
+ * \param   points - \c [in] array of sync points to wait
+ * \param   num_handles - \c [in] self-explanatory
+ * \param   timeout_nsec - \c [in] self-explanatory
+ * \param   flags   - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
+ * \param   first_signaled - \c [in] self-explanatory
+ *
+ * \return   0 on success\n
+ *          -ETIME - Timeout
+ *          <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
+				    uint32_t *handles, uint64_t *points,
+				    unsigned num_handles,
+				    int64_t timeout_nsec, unsigned flags,
+				    uint32_t *first_signaled);
+/**
+ *  Query sync objects payloads.
+ *
+ * \param   dev	    - \c [in] self-explanatory
+ * \param   handles - \c [in] array of sync object handles
+ * \param   points - \c [out] array of sync points returned, which presents
+ * syncobj payload.
+ * \param   num_handles - \c [in] self-explanatory
+ *
+ * \return   0 on success\n
+ *          -ETIME - Timeout
+ *          <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
+			    uint32_t *handles, uint64_t *points,
+			    unsigned num_handles);
+
 /**
  *  Export kernel sync object to shareable fd.
  *
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 3c9be6c2..b32c0a75 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -658,6 +658,30 @@ int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
 			      flags, first_signaled);
 }
 
+int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
+				    uint32_t *handles, uint64_t *points,
+				    unsigned num_handles,
+				    int64_t timeout_nsec, unsigned flags,
+				    uint32_t *first_signaled)
+{
+	if (NULL == dev)
+		return -EINVAL;
+
+	return drmSyncobjTimelineWait(dev->fd, handles, points, num_handles,
+				      timeout_nsec, flags, first_signaled);
+}
+
+int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
+			    uint32_t *handles, uint64_t *points,
+			    unsigned num_handles)
+{
+	if (NULL == dev)
+		return -EINVAL;
+
+	return drmSyncobjQuery(dev->fd, handles, points, num_handles);
+}
+
+
 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
 			     uint32_t handle,
 			     int *shared_fd)
-- 
2.17.1

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Re: [PATCH libdrm 4/5] [libdrm]: wrap syncobj timeline query and wait for amdgpu

[Michel Dänzer]

On 2018-09-12 11:50 a.m., Chunming Zhou wrote:
> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
> ---
>  amdgpu/amdgpu-symbol-check |  2 ++
>  amdgpu/amdgpu.h            | 39 ++++++++++++++++++++++++++++++++++++++
>  amdgpu/amdgpu_cs.c         | 24 +++++++++++++++++++++++
>  3 files changed, 65 insertions(+)
> 
> diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
> index 58646e85..4f91be54 100755
> --- a/amdgpu/amdgpu-symbol-check
> +++ b/amdgpu/amdgpu-symbol-check
> @@ -50,6 +50,8 @@ amdgpu_cs_syncobj_import_sync_file
>  amdgpu_cs_syncobj_reset
>  amdgpu_cs_syncobj_signal
>  amdgpu_cs_syncobj_wait
> +amdgpu_cs_syncobj_timeline_wait
> +amdgpu_cs_syncobj_query
>  amdgpu_cs_wait_fences
>  amdgpu_cs_wait_semaphore
>  amdgpu_device_deinitialize

This file should be sorted in lexical order.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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[PATCH libdrm 2/5] [libdrm] addr cs chunk for syncobj timeline

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/amdgpu_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index c363b67f..04663a13 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -482,6 +482,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_CHUNK_ID_DEPENDENCIES	0x03
 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x08
 
 struct drm_amdgpu_cs_chunk {
 	__u32		chunk_id;
@@ -553,6 +555,13 @@ struct drm_amdgpu_cs_chunk_sem {
 	__u32 handle;
 };
 
+struct drm_amdgpu_cs_chunk_syncobj {
+	__u32 handle;
+	__u32 pad;
+	__u64 point;
+};
+
+
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
-- 
2.17.1

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[PATCH libdrm 3/5] [libdrm]: add timeline wait/query ioctl

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 xf86drm.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 xf86drm.h |  6 ++++++
 2 files changed, 50 insertions(+)

diff --git a/xf86drm.c b/xf86drm.c
index b2388194..0cd1cb75 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4249,3 +4249,47 @@ int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count)
     ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_SIGNAL, &args);
     return ret;
 }
+
+int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
+			   unsigned num_handles,
+			   int64_t timeout_nsec, unsigned flags,
+			   uint32_t *first_signaled)
+{
+    struct drm_syncobj_timeline_wait args;
+    int ret;
+
+    memclear(args);
+    args.handles = (uintptr_t)handles;
+    args.points = (uint64_t)(uintptr_t)points;
+    args.timeout_nsec = timeout_nsec;
+    args.count_handles = num_handles;
+    args.flags = flags;
+
+    ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, &args);
+    if (ret < 0)
+        return -errno;
+
+    if (first_signaled)
+        *first_signaled = args.first_signaled;
+    return ret;
+}
+
+
+int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
+		    uint32_t handle_count)
+{
+    struct drm_syncobj_timeline_query args;
+    int ret;
+
+    memclear(args);
+    args.handles = (uintptr_t)handles;
+    args.points = (uint64_t)(uintptr_t)points;
+    args.count_handles = handle_count;
+
+    ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_QUERY, &args);
+    if (ret)
+        return ret;
+    return 0;
+}
+
+
diff --git a/xf86drm.h b/xf86drm.h
index 7773d71a..49a40633 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -875,6 +875,12 @@ extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
 			  uint32_t *first_signaled);
 extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count);
 extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count);
+extern int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
+				  unsigned num_handles,
+				  int64_t timeout_nsec, unsigned flags,
+				  uint32_t *first_signaled);
+extern int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
+			   uint32_t handle_count);
 
 #if defined(__cplusplus)
 }
-- 
2.17.1

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[PATCH libdrm 5/5] [libdrm] add syncobj timeline tests

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  12 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 258 +++++++++++++++++++++++++++++++++++
 5 files changed, 294 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index e79c1bd3..61f2b426 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -32,4 +32,5 @@ amdgpu_test_SOURCES = \
 	vcn_tests.c \
 	uve_ib.h \
 	deadlock_tests.c \
-	vm_tests.c
+	vm_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 96fcd687..cdcb93a5 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,6 +56,7 @@
 #define UVD_ENC_TESTS_STR "UVD ENC Tests"
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_vm_tests_clean,
 		.pTests = vm_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = VM_TESTS_STR,
 			.pActive = suite_vm_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
+
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index f2ece3c3..960df046 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
  */
 extern CU_TestInfo vm_tests[];
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 4c1237c6..3ceec715 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c',
+      'vm_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..196c66d2
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point;
+	int r;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, DRM_SYNCOBJ_CREATE_TYPE_TIMELINE,
+				       &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1,
+					    0x10000000000, //10s
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
+					    NULL);
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

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[PATCH libdrm 1/5] [libdrm] sync drm.h for syncobj part

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/drm.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index f0bd91de..d1688269 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -695,6 +695,7 @@ struct drm_prime_handle {
 struct drm_syncobj_create {
 	__u32 handle;
 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
+#define DRM_SYNCOBJ_CREATE_TYPE_TIMELINE (1 << 1)
 	__u32 flags;
 };
 
@@ -725,12 +726,32 @@ struct drm_syncobj_wait {
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_wait {
+        __u64 handles;
+        /* wait on specific timeline point for every handles*/
+        __u64 points;
+        /* absolute timeout */
+        __s64 timeout_nsec;
+        __u32 count_handles;
+        __u32 flags;
+        __u32 first_signaled; /* only valid when not waiting all */
+        __u32 pad;
+};
+
 struct drm_syncobj_array {
 	__u64 handles;
 	__u32 count_handles;
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_query {
+        __u64 handles;
+        /* points are timeline syncobjs payloads returned by query ioctl */
+        __u64 points;
+        __u32 count_handles;
+        __u32 pad;
+};
+
 /* Query current scanout sequence number */
 struct drm_crtc_get_sequence {
 	__u32 crtc_id;		/* requested crtc_id */
@@ -887,6 +908,9 @@ extern "C" {
 #define DRM_IOCTL_MODE_GET_LEASE	DRM_IOWR(0xC8, struct drm_mode_get_lease)
 #define DRM_IOCTL_MODE_REVOKE_LEASE	DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
 
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERY         DRM_IOWR(0xCB, struct drm_syncobj_timeline_query)
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
-- 
2.17.1

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[PATCH libdrm 5/5] [libdrm] add syncobj timeline tests

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  12 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 259 +++++++++++++++++++++++++++++++++++
 5 files changed, 295 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index e79c1bd3..61f2b426 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -32,4 +32,5 @@ amdgpu_test_SOURCES = \
 	vcn_tests.c \
 	uve_ib.h \
 	deadlock_tests.c \
-	vm_tests.c
+	vm_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 96fcd687..cdcb93a5 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,6 +56,7 @@
 #define UVD_ENC_TESTS_STR "UVD ENC Tests"
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_vm_tests_clean,
 		.pTests = vm_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = VM_TESTS_STR,
 			.pActive = suite_vm_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
+
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index f2ece3c3..960df046 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
  */
 extern CU_TestInfo vm_tests[];
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 4c1237c6..3ceec715 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c',
+      'vm_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..a70bd92d
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point;
+	int r;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, DRM_SYNCOBJ_CREATE_TYPE_TIMELINE,
+				       &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1,
+					    0x10000000000, //10s
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL | DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

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[PATCH libdrm 1/5] [libdrm] new syncobj extension

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/drm.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index 85c685a2..43d7420a 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -711,6 +711,7 @@ struct drm_prime_handle {
 struct drm_syncobj_create {
 	__u32 handle;
 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
+#define DRM_SYNCOBJ_CREATE_TYPE_TIMELINE (1 << 1)
 	__u32 flags;
 };
 
@@ -728,9 +729,20 @@ struct drm_syncobj_handle {
 	__s32 fd;
 	__u32 pad;
 };
+struct drm_syncobj_handle2 {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+
+	__s32 fd;
+	__u32 pad;
+};
+
 
 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_COMPLETED (1 << 2)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 3)
 struct drm_syncobj_wait {
 	__u64 handles;
 	/* absolute timeout */
@@ -741,12 +753,32 @@ struct drm_syncobj_wait {
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_wait {
+        __u64 handles;
+        /* wait on specific timeline point for every handles*/
+        __u64 points;
+        /* absolute timeout */
+        __s64 timeout_nsec;
+        __u32 count_handles;
+        __u32 flags;
+        __u32 first_signaled; /* only valid when not waiting all */
+        __u32 pad;
+};
+
 struct drm_syncobj_array {
 	__u64 handles;
 	__u32 count_handles;
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_query {
+        __u64 handles;
+        /* points are timeline syncobjs payloads returned by query ioctl */
+        __u64 points;
+        __u32 count_handles;
+        __u32 pad;
+};
+
 /* Query current scanout sequence number */
 struct drm_crtc_get_sequence {
 	__u32 crtc_id;		/* requested crtc_id */
@@ -903,6 +935,12 @@ extern "C" {
 #define DRM_IOCTL_MODE_GET_LEASE	DRM_IOWR(0xC8, struct drm_mode_get_lease)
 #define DRM_IOCTL_MODE_REVOKE_LEASE	DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
 
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERY         DRM_IOWR(0xCB, struct drm_syncobj_timeline_query)
+#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD2        DRM_IOWR(0xCC, struct drm_syncobj_handle2)
+#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE2        DRM_IOWR(0xCD, struct drm_syncobj_handle2)
+
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
-- 
2.17.1

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[PATCH libdrm 5/5] [libdrm] add syncobj timeline tests

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  12 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 263 +++++++++++++++++++++++++++++++++++
 5 files changed, 299 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 447ff217..d3fbe2bb 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -33,4 +33,5 @@ amdgpu_test_SOURCES = \
 	vcn_tests.c \
 	uve_ib.h \
 	deadlock_tests.c \
-	vm_tests.c
+	vm_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 96fcd687..cdcb93a5 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,6 +56,7 @@
 #define UVD_ENC_TESTS_STR "UVD ENC Tests"
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_vm_tests_clean,
 		.pTests = vm_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = VM_TESTS_STR,
 			.pActive = suite_vm_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
+
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 0609a74b..946e91c2 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
  */
 extern CU_TestInfo vm_tests[];
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 4c1237c6..3ceec715 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c',
+      'vm_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..2a345490
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t *p_payload;
+	uint64_t wait_point;
+	int r;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, DRM_SYNCOBJ_CREATE_TYPE_TIMELINE,
+				       &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	p_payload = &payload;
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, &p_payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1,
+					    0x10000000000, //10s
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_COMPLETED |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

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Re: [PATCH libdrm 5/5] [libdrm] add syncobj timeline tests

[Daniel Vetter]

On Fri, Nov 02, 2018 at 04:26:49PM +0800, Chunming Zhou wrote:
> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
> ---
>  tests/amdgpu/Makefile.am     |   3 +-
>  tests/amdgpu/amdgpu_test.c   |  12 ++
>  tests/amdgpu/amdgpu_test.h   |  21 +++
>  tests/amdgpu/meson.build     |   2 +-
>  tests/amdgpu/syncobj_tests.c | 263 +++++++++++++++++++++++++++++++++++
>  5 files changed, 299 insertions(+), 2 deletions(-)
>  create mode 100644 tests/amdgpu/syncobj_tests.c

This testcase seems very much a happy sunday scenario, no tests at all for
corner cases, invalid input, and generally trying to pull the kernel over
the table. I think we need a lot more, and preferrably in igt, where we
already have a good baseline of drm_syncobj tests.
-Daniel

> 
> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
> index 447ff217..d3fbe2bb 100644
> --- a/tests/amdgpu/Makefile.am
> +++ b/tests/amdgpu/Makefile.am
> @@ -33,4 +33,5 @@ amdgpu_test_SOURCES = \
>  	vcn_tests.c \
>  	uve_ib.h \
>  	deadlock_tests.c \
> -	vm_tests.c
> +	vm_tests.c \
> +	syncobj_tests.c
> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
> index 96fcd687..cdcb93a5 100644
> --- a/tests/amdgpu/amdgpu_test.c
> +++ b/tests/amdgpu/amdgpu_test.c
> @@ -56,6 +56,7 @@
>  #define UVD_ENC_TESTS_STR "UVD ENC Tests"
>  #define DEADLOCK_TESTS_STR "Deadlock Tests"
>  #define VM_TESTS_STR "VM Tests"
> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
>  
>  /**
>   *  Open handles for amdgpu devices
> @@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
>  		.pCleanupFunc = suite_vm_tests_clean,
>  		.pTests = vm_tests,
>  	},
> +	{
> +		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> +		.pInitFunc = suite_syncobj_timeline_tests_init,
> +		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
> +		.pTests = syncobj_timeline_tests,
> +	},
>  
>  	CU_SUITE_INFO_NULL,
>  };
> @@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
>  			.pName = VM_TESTS_STR,
>  			.pActive = suite_vm_tests_enable,
>  		},
> +		{
> +			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> +			.pActive = suite_syncobj_timeline_tests_enable,
> +		},
> +
>  };
>  
>  
> diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
> index 0609a74b..946e91c2 100644
> --- a/tests/amdgpu/amdgpu_test.h
> +++ b/tests/amdgpu/amdgpu_test.h
> @@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
>   */
>  extern CU_TestInfo vm_tests[];
>  
> +/**
> + * Initialize syncobj timeline test suite
> + */
> +int suite_syncobj_timeline_tests_init();
> +
> +/**
> + * Deinitialize syncobj timeline test suite
> + */
> +int suite_syncobj_timeline_tests_clean();
> +
> +/**
> + * Decide if the suite is enabled by default or not.
> + */
> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
> +
> +/**
> + * Tests in syncobj timeline test suite
> + */
> +extern CU_TestInfo syncobj_timeline_tests[];
> +
> +
>  /**
>   * Helper functions
>   */
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 4c1237c6..3ceec715 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -24,7 +24,7 @@ if dep_cunit.found()
>      files(
>        'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
>        'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
> -      'vm_tests.c',
> +      'vm_tests.c', 'syncobj_tests.c',
>      ),
>      dependencies : [dep_cunit, dep_threads],
>      include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
> diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
> new file mode 100644
> index 00000000..2a345490
> --- /dev/null
> +++ b/tests/amdgpu/syncobj_tests.c
> @@ -0,0 +1,263 @@
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +
> +#include "CUnit/Basic.h"
> +
> +#include "amdgpu_test.h"
> +#include "amdgpu_drm.h"
> +#include "amdgpu_internal.h"
> +#include <pthread.h>
> +
> +static  amdgpu_device_handle device_handle;
> +static  uint32_t  major_version;
> +static  uint32_t  minor_version;
> +
> +static void amdgpu_syncobj_timeline_test(void);
> +
> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
> +{
> +	return CU_TRUE;
> +}
> +
> +int suite_syncobj_timeline_tests_init(void)
> +{
> +	int r;
> +
> +	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
> +				   &minor_version, &device_handle);
> +
> +	if (r) {
> +		if ((r == -EACCES) && (errno == EACCES))
> +			printf("\n\nError:%s. "
> +				"Hint:Try to run this test program as root.",
> +				strerror(errno));
> +		return CUE_SINIT_FAILED;
> +	}
> +
> +	return CUE_SUCCESS;
> +}
> +
> +int suite_syncobj_timeline_tests_clean(void)
> +{
> +	int r = amdgpu_device_deinitialize(device_handle);
> +
> +	if (r == 0)
> +		return CUE_SUCCESS;
> +	else
> +		return CUE_SCLEAN_FAILED;
> +}
> +
> +
> +CU_TestInfo syncobj_timeline_tests[] = {
> +	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
> +	CU_TEST_INFO_NULL,
> +};
> +
> +#define GFX_COMPUTE_NOP  0xffff1000
> +#define SDMA_NOP  0x0
> +static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
> +					     wait_or_signal, uint64_t point)
> +{
> +	amdgpu_context_handle context_handle;
> +	amdgpu_bo_handle ib_result_handle;
> +	void *ib_result_cpu;
> +	uint64_t ib_result_mc_address;
> +	struct drm_amdgpu_cs_chunk chunks[2];
> +	struct drm_amdgpu_cs_chunk_data chunk_data;
> +	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> +	struct amdgpu_cs_fence fence_status;
> +	amdgpu_bo_list_handle bo_list;
> +	amdgpu_va_handle va_handle;
> +	uint32_t expired, flags;
> +	int i, r;
> +	uint64_t seq_no;
> +	static uint32_t *ptr;
> +
> +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> +				    AMDGPU_GEM_DOMAIN_GTT, 0,
> +				    &ib_result_handle, &ib_result_cpu,
> +				    &ib_result_mc_address, &va_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
> +			       &bo_list);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	ptr = ib_result_cpu;
> +
> +	for (i = 0; i < 16; ++i)
> +		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> +
> +	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> +	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> +	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> +	chunk_data.ib_data._pad = 0;
> +	chunk_data.ib_data.va_start = ib_result_mc_address;
> +	chunk_data.ib_data.ib_bytes = 16 * 4;
> +	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
> +		AMDGPU_HW_IP_DMA;
> +	chunk_data.ib_data.ip_instance = 0;
> +	chunk_data.ib_data.ring = 0;
> +	chunk_data.ib_data.flags = 0;
> +
> +	chunks[1].chunk_id = wait_or_signal ?
> +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> +	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> +	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> +	syncobj_data.handle = syncobj_handle;
> +	syncobj_data.point = point;
> +	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> +	r = amdgpu_cs_submit_raw(device_handle,
> +				 context_handle,
> +				 bo_list,
> +				 2,
> +				 chunks,
> +				 &seq_no);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +
> +	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> +	fence_status.context = context_handle;
> +	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
> +		AMDGPU_HW_IP_DMA;
> +	fence_status.ip_instance = 0;
> +	fence_status.ring = 0;
> +	fence_status.fence = seq_no;
> +
> +	r = amdgpu_cs_query_fence_status(&fence_status,
> +			AMDGPU_TIMEOUT_INFINITE,0, &expired);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_bo_list_destroy(bo_list);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> +				     ib_result_mc_address, 4096);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_cs_ctx_free(context_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	return r;
> +}
> +
> +struct syncobj_point {
> +	uint32_t syncobj_handle;
> +	uint64_t point;
> +};
> +
> +static void *syncobj_wait(void *data)
> +{
> +	struct syncobj_point *sp = (struct syncobj_point *)data;
> +	int r;
> +
> +	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
> +					      sp->point);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	return (void *)r;
> +}
> +
> +static void *syncobj_signal(void *data)
> +{
> +	struct syncobj_point *sp = (struct syncobj_point *)data;
> +	int r;
> +
> +	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
> +					      sp->point);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	return (void *)r;
> +}
> +
> +static void amdgpu_syncobj_timeline_test(void)
> +{
> +	static pthread_t wait_thread;
> +	static pthread_t signal_thread;
> +	static pthread_t c_thread;
> +	struct syncobj_point sp1, sp2, sp3;
> +	uint32_t syncobj_handle;
> +	uint64_t payload;
> +	uint64_t *p_payload;
> +	uint64_t wait_point;
> +	int r;
> +	void *tmp;
> +
> +	r =  amdgpu_cs_create_syncobj2(device_handle, DRM_SYNCOBJ_CREATE_TYPE_TIMELINE,
> +				       &syncobj_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	// wait on point 5
> +	sp1.syncobj_handle = syncobj_handle;
> +	sp1.point = 5;
> +	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	// signal on point 10
> +	sp2.syncobj_handle = syncobj_handle;
> +	sp2.point = 10;
> +	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = pthread_join(wait_thread, &tmp);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(tmp, 0);
> +
> +	r = pthread_join(signal_thread, &tmp);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(tmp, 0);
> +
> +	//query timeline payload
> +	p_payload = &payload;
> +	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, &p_payload, 1);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(payload, 10);
> +
> +	//signal on point 16
> +	sp3.syncobj_handle = syncobj_handle;
> +	sp3.point = 16;
> +	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> +	CU_ASSERT_EQUAL(r, 0);
> +	//CPU wait on point 16
> +	wait_point = 16;
> +	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> +					    &wait_point, 1,
> +					    0x10000000000, //10s
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_COMPLETED |
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> +					    NULL);
> +	CU_ASSERT_EQUAL(r, 0);
> +	r = pthread_join(c_thread, &tmp);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(tmp, 0);
> +
> +	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +}
> -- 
> 2.17.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH libdrm 5/5] [libdrm] add syncobj timeline tests

[Zhou, David(ChunMing)]

> -----Original Message-----
> From: Daniel Vetter <daniel.vetter@ffwll.ch> On Behalf Of Daniel Vetter
> Sent: Monday, November 05, 2018 5:39 PM
> To: Zhou, David(ChunMing) <David1.Zhou@amd.com>
> Cc: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH libdrm 5/5] [libdrm] add syncobj timeline tests
> 
> On Fri, Nov 02, 2018 at 04:26:49PM +0800, Chunming Zhou wrote:
> > Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
> > ---
> >  tests/amdgpu/Makefile.am     |   3 +-
> >  tests/amdgpu/amdgpu_test.c   |  12 ++
> >  tests/amdgpu/amdgpu_test.h   |  21 +++
> >  tests/amdgpu/meson.build     |   2 +-
> >  tests/amdgpu/syncobj_tests.c | 263
> > +++++++++++++++++++++++++++++++++++
> >  5 files changed, 299 insertions(+), 2 deletions(-)  create mode
> > 100644 tests/amdgpu/syncobj_tests.c
> 
> This testcase seems very much a happy sunday scenario, no tests at all for
> corner cases, invalid input, and generally trying to pull the kernel over the
> table. I think we need a lot more, and preferrably in igt, where we already
> have a good baseline of drm_syncobj tests.
Hi Daniel,

OK, if you insist on that, I would switch to implement a timeline test on IGT.
Btw,  timeline syncobj test needs based on command submission, Can I write it with amdgpu driver on IGT?
And after that, where should I send igt patch to review? 

Last, if you are free, Could you also take a look the u/k interface of timeline syncobj?


Thanks,
David Zhou
> -Daniel
> 
> >
> > diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index
> > 447ff217..d3fbe2bb 100644
> > --- a/tests/amdgpu/Makefile.am
> > +++ b/tests/amdgpu/Makefile.am
> > @@ -33,4 +33,5 @@ amdgpu_test_SOURCES = \
> >  	vcn_tests.c \
> >  	uve_ib.h \
> >  	deadlock_tests.c \
> > -	vm_tests.c
> > +	vm_tests.c \
> > +	syncobj_tests.c
> > diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
> > index 96fcd687..cdcb93a5 100644
> > --- a/tests/amdgpu/amdgpu_test.c
> > +++ b/tests/amdgpu/amdgpu_test.c
> > @@ -56,6 +56,7 @@
> >  #define UVD_ENC_TESTS_STR "UVD ENC Tests"
> >  #define DEADLOCK_TESTS_STR "Deadlock Tests"
> >  #define VM_TESTS_STR "VM Tests"
> > +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
> >
> >  /**
> >   *  Open handles for amdgpu devices
> > @@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
> >  		.pCleanupFunc = suite_vm_tests_clean,
> >  		.pTests = vm_tests,
> >  	},
> > +	{
> > +		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> > +		.pInitFunc = suite_syncobj_timeline_tests_init,
> > +		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
> > +		.pTests = syncobj_timeline_tests,
> > +	},
> >
> >  	CU_SUITE_INFO_NULL,
> >  };
> > @@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
> >  			.pName = VM_TESTS_STR,
> >  			.pActive = suite_vm_tests_enable,
> >  		},
> > +		{
> > +			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> > +			.pActive = suite_syncobj_timeline_tests_enable,
> > +		},
> > +
> >  };
> >
> >
> > diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
> > index 0609a74b..946e91c2 100644
> > --- a/tests/amdgpu/amdgpu_test.h
> > +++ b/tests/amdgpu/amdgpu_test.h
> > @@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
> >   */
> >  extern CU_TestInfo vm_tests[];
> >
> > +/**
> > + * Initialize syncobj timeline test suite  */ int
> > +suite_syncobj_timeline_tests_init();
> > +
> > +/**
> > + * Deinitialize syncobj timeline test suite  */ int
> > +suite_syncobj_timeline_tests_clean();
> > +
> > +/**
> > + * Decide if the suite is enabled by default or not.
> > + */
> > +CU_BOOL suite_syncobj_timeline_tests_enable(void);
> > +
> > +/**
> > + * Tests in syncobj timeline test suite  */ extern CU_TestInfo
> > +syncobj_timeline_tests[];
> > +
> > +
> >  /**
> >   * Helper functions
> >   */
> > diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build index
> > 4c1237c6..3ceec715 100644
> > --- a/tests/amdgpu/meson.build
> > +++ b/tests/amdgpu/meson.build
> > @@ -24,7 +24,7 @@ if dep_cunit.found()
> >      files(
> >        'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
> >        'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
> > -      'vm_tests.c',
> > +      'vm_tests.c', 'syncobj_tests.c',
> >      ),
> >      dependencies : [dep_cunit, dep_threads],
> >      include_directories : [inc_root, inc_drm,
> > include_directories('../../amdgpu')],
> > diff --git a/tests/amdgpu/syncobj_tests.c
> > b/tests/amdgpu/syncobj_tests.c new file mode 100644 index
> > 00000000..2a345490
> > --- /dev/null
> > +++ b/tests/amdgpu/syncobj_tests.c
> > @@ -0,0 +1,263 @@
> > +/*
> > + * Copyright 2017 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > +included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN
> NO EVENT
> > +SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> > +DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > +OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE
> > +OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > +*/
> > +
> > +#include "CUnit/Basic.h"
> > +
> > +#include "amdgpu_test.h"
> > +#include "amdgpu_drm.h"
> > +#include "amdgpu_internal.h"
> > +#include <pthread.h>
> > +
> > +static  amdgpu_device_handle device_handle; static  uint32_t
> > +major_version; static  uint32_t  minor_version;
> > +
> > +static void amdgpu_syncobj_timeline_test(void);
> > +
> > +CU_BOOL suite_syncobj_timeline_tests_enable(void)
> > +{
> > +	return CU_TRUE;
> > +}
> > +
> > +int suite_syncobj_timeline_tests_init(void)
> > +{
> > +	int r;
> > +
> > +	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
> > +				   &minor_version, &device_handle);
> > +
> > +	if (r) {
> > +		if ((r == -EACCES) && (errno == EACCES))
> > +			printf("\n\nError:%s. "
> > +				"Hint:Try to run this test program as root.",
> > +				strerror(errno));
> > +		return CUE_SINIT_FAILED;
> > +	}
> > +
> > +	return CUE_SUCCESS;
> > +}
> > +
> > +int suite_syncobj_timeline_tests_clean(void)
> > +{
> > +	int r = amdgpu_device_deinitialize(device_handle);
> > +
> > +	if (r == 0)
> > +		return CUE_SUCCESS;
> > +	else
> > +		return CUE_SCLEAN_FAILED;
> > +}
> > +
> > +
> > +CU_TestInfo syncobj_timeline_tests[] = {
> > +	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
> > +	CU_TEST_INFO_NULL,
> > +};
> > +
> > +#define GFX_COMPUTE_NOP  0xffff1000
> > +#define SDMA_NOP  0x0
> > +static int syncobj_command_submission_helper(uint32_t syncobj_handle,
> bool
> > +					     wait_or_signal, uint64_t point) {
> > +	amdgpu_context_handle context_handle;
> > +	amdgpu_bo_handle ib_result_handle;
> > +	void *ib_result_cpu;
> > +	uint64_t ib_result_mc_address;
> > +	struct drm_amdgpu_cs_chunk chunks[2];
> > +	struct drm_amdgpu_cs_chunk_data chunk_data;
> > +	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> > +	struct amdgpu_cs_fence fence_status;
> > +	amdgpu_bo_list_handle bo_list;
> > +	amdgpu_va_handle va_handle;
> > +	uint32_t expired, flags;
> > +	int i, r;
> > +	uint64_t seq_no;
> > +	static uint32_t *ptr;
> > +
> > +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> > +				    AMDGPU_GEM_DOMAIN_GTT, 0,
> > +				    &ib_result_handle, &ib_result_cpu,
> > +				    &ib_result_mc_address, &va_handle);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
> > +			       &bo_list);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	ptr = ib_result_cpu;
> > +
> > +	for (i = 0; i < 16; ++i)
> > +		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> > +
> > +	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> > +	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> > +	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> > +	chunk_data.ib_data._pad = 0;
> > +	chunk_data.ib_data.va_start = ib_result_mc_address;
> > +	chunk_data.ib_data.ib_bytes = 16 * 4;
> > +	chunk_data.ib_data.ip_type = wait_or_signal ?
> AMDGPU_HW_IP_GFX :
> > +		AMDGPU_HW_IP_DMA;
> > +	chunk_data.ib_data.ip_instance = 0;
> > +	chunk_data.ib_data.ring = 0;
> > +	chunk_data.ib_data.flags = 0;
> > +
> > +	chunks[1].chunk_id = wait_or_signal ?
> > +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> > +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> > +	chunks[1].length_dw = sizeof(struct
> drm_amdgpu_cs_chunk_syncobj) / 4;
> > +	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> > +	syncobj_data.handle = syncobj_handle;
> > +	syncobj_data.point = point;
> > +	syncobj_data.flags =
> DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> > +
> > +	r = amdgpu_cs_submit_raw(device_handle,
> > +				 context_handle,
> > +				 bo_list,
> > +				 2,
> > +				 chunks,
> > +				 &seq_no);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +
> > +	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> > +	fence_status.context = context_handle;
> > +	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
> > +		AMDGPU_HW_IP_DMA;
> > +	fence_status.ip_instance = 0;
> > +	fence_status.ring = 0;
> > +	fence_status.fence = seq_no;
> > +
> > +	r = amdgpu_cs_query_fence_status(&fence_status,
> > +			AMDGPU_TIMEOUT_INFINITE,0, &expired);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	r = amdgpu_bo_list_destroy(bo_list);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> > +				     ib_result_mc_address, 4096);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	r = amdgpu_cs_ctx_free(context_handle);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	return r;
> > +}
> > +
> > +struct syncobj_point {
> > +	uint32_t syncobj_handle;
> > +	uint64_t point;
> > +};
> > +
> > +static void *syncobj_wait(void *data) {
> > +	struct syncobj_point *sp = (struct syncobj_point *)data;
> > +	int r;
> > +
> > +	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
> > +					      sp->point);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	return (void *)r;
> > +}
> > +
> > +static void *syncobj_signal(void *data) {
> > +	struct syncobj_point *sp = (struct syncobj_point *)data;
> > +	int r;
> > +
> > +	r = syncobj_command_submission_helper(sp->syncobj_handle,
> false,
> > +					      sp->point);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	return (void *)r;
> > +}
> > +
> > +static void amdgpu_syncobj_timeline_test(void)
> > +{
> > +	static pthread_t wait_thread;
> > +	static pthread_t signal_thread;
> > +	static pthread_t c_thread;
> > +	struct syncobj_point sp1, sp2, sp3;
> > +	uint32_t syncobj_handle;
> > +	uint64_t payload;
> > +	uint64_t *p_payload;
> > +	uint64_t wait_point;
> > +	int r;
> > +	void *tmp;
> > +
> > +	r =  amdgpu_cs_create_syncobj2(device_handle,
> DRM_SYNCOBJ_CREATE_TYPE_TIMELINE,
> > +				       &syncobj_handle);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	// wait on point 5
> > +	sp1.syncobj_handle = syncobj_handle;
> > +	sp1.point = 5;
> > +	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	// signal on point 10
> > +	sp2.syncobj_handle = syncobj_handle;
> > +	sp2.point = 10;
> > +	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +	r = pthread_join(wait_thread, &tmp);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +	CU_ASSERT_EQUAL(tmp, 0);
> > +
> > +	r = pthread_join(signal_thread, &tmp);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +	CU_ASSERT_EQUAL(tmp, 0);
> > +
> > +	//query timeline payload
> > +	p_payload = &payload;
> > +	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> &p_payload, 1);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +	CU_ASSERT_EQUAL(payload, 10);
> > +
> > +	//signal on point 16
> > +	sp3.syncobj_handle = syncobj_handle;
> > +	sp3.point = 16;
> > +	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +	//CPU wait on point 16
> > +	wait_point = 16;
> > +	r = amdgpu_cs_syncobj_timeline_wait(device_handle,
> &syncobj_handle,
> > +					    &wait_point, 1,
> > +					    0x10000000000, //10s
> > +
> DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> > +
> DRM_SYNCOBJ_WAIT_FLAGS_WAIT_COMPLETED |
> > +
> DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> > +					    NULL);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +	r = pthread_join(c_thread, &tmp);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +	CU_ASSERT_EQUAL(tmp, 0);
> > +
> > +	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> > +	CU_ASSERT_EQUAL(r, 0);
> > +
> > +}
> > --
> > 2.17.1
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH libdrm 5/5] [libdrm] add syncobj timeline tests

[Daniel Vetter]

On Mon, Nov 05, 2018 at 10:07:24AM +0000, Zhou, David(ChunMing) wrote:
> 
> 
> > -----Original Message-----
> > From: Daniel Vetter <daniel.vetter@ffwll.ch> On Behalf Of Daniel Vetter
> > Sent: Monday, November 05, 2018 5:39 PM
> > To: Zhou, David(ChunMing) <David1.Zhou@amd.com>
> > Cc: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH libdrm 5/5] [libdrm] add syncobj timeline tests
> > 
> > On Fri, Nov 02, 2018 at 04:26:49PM +0800, Chunming Zhou wrote:
> > > Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
> > > ---
> > >  tests/amdgpu/Makefile.am     |   3 +-
> > >  tests/amdgpu/amdgpu_test.c   |  12 ++
> > >  tests/amdgpu/amdgpu_test.h   |  21 +++
> > >  tests/amdgpu/meson.build     |   2 +-
> > >  tests/amdgpu/syncobj_tests.c | 263
> > > +++++++++++++++++++++++++++++++++++
> > >  5 files changed, 299 insertions(+), 2 deletions(-)  create mode
> > > 100644 tests/amdgpu/syncobj_tests.c
> > 
> > This testcase seems very much a happy sunday scenario, no tests at all for
> > corner cases, invalid input, and generally trying to pull the kernel over the
> > table. I think we need a lot more, and preferrably in igt, where we already
> > have a good baseline of drm_syncobj tests.
> Hi Daniel,
> 
> OK, if you insist on that, I would switch to implement a timeline test on IGT.
> Btw,  timeline syncobj test needs based on command submission, Can I write it with amdgpu driver on IGT?
> And after that, where should I send igt patch to review? 

We have used vgem and sw_fence in the past to be able to have very
controlled timelines. This allows us to write generic testcases. The
current igt tests for syncobj are neither i915 nor amdgpu specific.

You might still want to have an amgpu test on top, we do have some i915
tests for the i915 execbuf integration of syncobj of course. But that's a
fairly minor part of the syncobj api.

For contributing to igt, see https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md

> Last, if you are free, Could you also take a look the u/k interface of timeline syncobj?

Looked reasonable, the detailed questions need userspace (and so probably
better answered by someone who has mesa/vk/gl clue). I can help review
corner cases of the uapi, but that's much easier to do once we have
test-cases to exercise them all. See existing igts for an idea of what
exhaustive testing of uapi corner cases looks like.
-Daniel


> 
> 
> Thanks,
> David Zhou
> > -Daniel
> > 
> > >
> > > diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am index
> > > 447ff217..d3fbe2bb 100644
> > > --- a/tests/amdgpu/Makefile.am
> > > +++ b/tests/amdgpu/Makefile.am
> > > @@ -33,4 +33,5 @@ amdgpu_test_SOURCES = \
> > >  	vcn_tests.c \
> > >  	uve_ib.h \
> > >  	deadlock_tests.c \
> > > -	vm_tests.c
> > > +	vm_tests.c \
> > > +	syncobj_tests.c
> > > diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
> > > index 96fcd687..cdcb93a5 100644
> > > --- a/tests/amdgpu/amdgpu_test.c
> > > +++ b/tests/amdgpu/amdgpu_test.c
> > > @@ -56,6 +56,7 @@
> > >  #define UVD_ENC_TESTS_STR "UVD ENC Tests"
> > >  #define DEADLOCK_TESTS_STR "Deadlock Tests"
> > >  #define VM_TESTS_STR "VM Tests"
> > > +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
> > >
> > >  /**
> > >   *  Open handles for amdgpu devices
> > > @@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
> > >  		.pCleanupFunc = suite_vm_tests_clean,
> > >  		.pTests = vm_tests,
> > >  	},
> > > +	{
> > > +		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> > > +		.pInitFunc = suite_syncobj_timeline_tests_init,
> > > +		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
> > > +		.pTests = syncobj_timeline_tests,
> > > +	},
> > >
> > >  	CU_SUITE_INFO_NULL,
> > >  };
> > > @@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
> > >  			.pName = VM_TESTS_STR,
> > >  			.pActive = suite_vm_tests_enable,
> > >  		},
> > > +		{
> > > +			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> > > +			.pActive = suite_syncobj_timeline_tests_enable,
> > > +		},
> > > +
> > >  };
> > >
> > >
> > > diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
> > > index 0609a74b..946e91c2 100644
> > > --- a/tests/amdgpu/amdgpu_test.h
> > > +++ b/tests/amdgpu/amdgpu_test.h
> > > @@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
> > >   */
> > >  extern CU_TestInfo vm_tests[];
> > >
> > > +/**
> > > + * Initialize syncobj timeline test suite  */ int
> > > +suite_syncobj_timeline_tests_init();
> > > +
> > > +/**
> > > + * Deinitialize syncobj timeline test suite  */ int
> > > +suite_syncobj_timeline_tests_clean();
> > > +
> > > +/**
> > > + * Decide if the suite is enabled by default or not.
> > > + */
> > > +CU_BOOL suite_syncobj_timeline_tests_enable(void);
> > > +
> > > +/**
> > > + * Tests in syncobj timeline test suite  */ extern CU_TestInfo
> > > +syncobj_timeline_tests[];
> > > +
> > > +
> > >  /**
> > >   * Helper functions
> > >   */
> > > diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build index
> > > 4c1237c6..3ceec715 100644
> > > --- a/tests/amdgpu/meson.build
> > > +++ b/tests/amdgpu/meson.build
> > > @@ -24,7 +24,7 @@ if dep_cunit.found()
> > >      files(
> > >        'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
> > >        'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
> > > -      'vm_tests.c',
> > > +      'vm_tests.c', 'syncobj_tests.c',
> > >      ),
> > >      dependencies : [dep_cunit, dep_threads],
> > >      include_directories : [inc_root, inc_drm,
> > > include_directories('../../amdgpu')],
> > > diff --git a/tests/amdgpu/syncobj_tests.c
> > > b/tests/amdgpu/syncobj_tests.c new file mode 100644 index
> > > 00000000..2a345490
> > > --- /dev/null
> > > +++ b/tests/amdgpu/syncobj_tests.c
> > > @@ -0,0 +1,263 @@
> > > +/*
> > > + * Copyright 2017 Advanced Micro Devices, Inc.
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person
> > > +obtaining a
> > > + * copy of this software and associated documentation files (the
> > > +"Software"),
> > > + * to deal in the Software without restriction, including without
> > > +limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > +sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom
> > > +the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice shall be
> > > +included in
> > > + * all copies or substantial portions of the Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > KIND,
> > > +EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > +MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN
> > NO EVENT
> > > +SHALL
> > > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> > > +DAMAGES OR
> > > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > > +OTHERWISE,
> > > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> > THE USE
> > > +OR
> > > + * OTHER DEALINGS IN THE SOFTWARE.
> > > + *
> > > +*/
> > > +
> > > +#include "CUnit/Basic.h"
> > > +
> > > +#include "amdgpu_test.h"
> > > +#include "amdgpu_drm.h"
> > > +#include "amdgpu_internal.h"
> > > +#include <pthread.h>
> > > +
> > > +static  amdgpu_device_handle device_handle; static  uint32_t
> > > +major_version; static  uint32_t  minor_version;
> > > +
> > > +static void amdgpu_syncobj_timeline_test(void);
> > > +
> > > +CU_BOOL suite_syncobj_timeline_tests_enable(void)
> > > +{
> > > +	return CU_TRUE;
> > > +}
> > > +
> > > +int suite_syncobj_timeline_tests_init(void)
> > > +{
> > > +	int r;
> > > +
> > > +	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
> > > +				   &minor_version, &device_handle);
> > > +
> > > +	if (r) {
> > > +		if ((r == -EACCES) && (errno == EACCES))
> > > +			printf("\n\nError:%s. "
> > > +				"Hint:Try to run this test program as root.",
> > > +				strerror(errno));
> > > +		return CUE_SINIT_FAILED;
> > > +	}
> > > +
> > > +	return CUE_SUCCESS;
> > > +}
> > > +
> > > +int suite_syncobj_timeline_tests_clean(void)
> > > +{
> > > +	int r = amdgpu_device_deinitialize(device_handle);
> > > +
> > > +	if (r == 0)
> > > +		return CUE_SUCCESS;
> > > +	else
> > > +		return CUE_SCLEAN_FAILED;
> > > +}
> > > +
> > > +
> > > +CU_TestInfo syncobj_timeline_tests[] = {
> > > +	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
> > > +	CU_TEST_INFO_NULL,
> > > +};
> > > +
> > > +#define GFX_COMPUTE_NOP  0xffff1000
> > > +#define SDMA_NOP  0x0
> > > +static int syncobj_command_submission_helper(uint32_t syncobj_handle,
> > bool
> > > +					     wait_or_signal, uint64_t point) {
> > > +	amdgpu_context_handle context_handle;
> > > +	amdgpu_bo_handle ib_result_handle;
> > > +	void *ib_result_cpu;
> > > +	uint64_t ib_result_mc_address;
> > > +	struct drm_amdgpu_cs_chunk chunks[2];
> > > +	struct drm_amdgpu_cs_chunk_data chunk_data;
> > > +	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> > > +	struct amdgpu_cs_fence fence_status;
> > > +	amdgpu_bo_list_handle bo_list;
> > > +	amdgpu_va_handle va_handle;
> > > +	uint32_t expired, flags;
> > > +	int i, r;
> > > +	uint64_t seq_no;
> > > +	static uint32_t *ptr;
> > > +
> > > +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> > > +				    AMDGPU_GEM_DOMAIN_GTT, 0,
> > > +				    &ib_result_handle, &ib_result_cpu,
> > > +				    &ib_result_mc_address, &va_handle);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
> > > +			       &bo_list);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	ptr = ib_result_cpu;
> > > +
> > > +	for (i = 0; i < 16; ++i)
> > > +		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> > > +
> > > +	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> > > +	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> > > +	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> > > +	chunk_data.ib_data._pad = 0;
> > > +	chunk_data.ib_data.va_start = ib_result_mc_address;
> > > +	chunk_data.ib_data.ib_bytes = 16 * 4;
> > > +	chunk_data.ib_data.ip_type = wait_or_signal ?
> > AMDGPU_HW_IP_GFX :
> > > +		AMDGPU_HW_IP_DMA;
> > > +	chunk_data.ib_data.ip_instance = 0;
> > > +	chunk_data.ib_data.ring = 0;
> > > +	chunk_data.ib_data.flags = 0;
> > > +
> > > +	chunks[1].chunk_id = wait_or_signal ?
> > > +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> > > +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> > > +	chunks[1].length_dw = sizeof(struct
> > drm_amdgpu_cs_chunk_syncobj) / 4;
> > > +	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> > > +	syncobj_data.handle = syncobj_handle;
> > > +	syncobj_data.point = point;
> > > +	syncobj_data.flags =
> > DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> > > +
> > > +	r = amdgpu_cs_submit_raw(device_handle,
> > > +				 context_handle,
> > > +				 bo_list,
> > > +				 2,
> > > +				 chunks,
> > > +				 &seq_no);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +
> > > +	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> > > +	fence_status.context = context_handle;
> > > +	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
> > > +		AMDGPU_HW_IP_DMA;
> > > +	fence_status.ip_instance = 0;
> > > +	fence_status.ring = 0;
> > > +	fence_status.fence = seq_no;
> > > +
> > > +	r = amdgpu_cs_query_fence_status(&fence_status,
> > > +			AMDGPU_TIMEOUT_INFINITE,0, &expired);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	r = amdgpu_bo_list_destroy(bo_list);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> > > +				     ib_result_mc_address, 4096);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	r = amdgpu_cs_ctx_free(context_handle);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	return r;
> > > +}
> > > +
> > > +struct syncobj_point {
> > > +	uint32_t syncobj_handle;
> > > +	uint64_t point;
> > > +};
> > > +
> > > +static void *syncobj_wait(void *data) {
> > > +	struct syncobj_point *sp = (struct syncobj_point *)data;
> > > +	int r;
> > > +
> > > +	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
> > > +					      sp->point);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	return (void *)r;
> > > +}
> > > +
> > > +static void *syncobj_signal(void *data) {
> > > +	struct syncobj_point *sp = (struct syncobj_point *)data;
> > > +	int r;
> > > +
> > > +	r = syncobj_command_submission_helper(sp->syncobj_handle,
> > false,
> > > +					      sp->point);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	return (void *)r;
> > > +}
> > > +
> > > +static void amdgpu_syncobj_timeline_test(void)
> > > +{
> > > +	static pthread_t wait_thread;
> > > +	static pthread_t signal_thread;
> > > +	static pthread_t c_thread;
> > > +	struct syncobj_point sp1, sp2, sp3;
> > > +	uint32_t syncobj_handle;
> > > +	uint64_t payload;
> > > +	uint64_t *p_payload;
> > > +	uint64_t wait_point;
> > > +	int r;
> > > +	void *tmp;
> > > +
> > > +	r =  amdgpu_cs_create_syncobj2(device_handle,
> > DRM_SYNCOBJ_CREATE_TYPE_TIMELINE,
> > > +				       &syncobj_handle);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	// wait on point 5
> > > +	sp1.syncobj_handle = syncobj_handle;
> > > +	sp1.point = 5;
> > > +	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	// signal on point 10
> > > +	sp2.syncobj_handle = syncobj_handle;
> > > +	sp2.point = 10;
> > > +	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +	r = pthread_join(wait_thread, &tmp);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +	CU_ASSERT_EQUAL(tmp, 0);
> > > +
> > > +	r = pthread_join(signal_thread, &tmp);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +	CU_ASSERT_EQUAL(tmp, 0);
> > > +
> > > +	//query timeline payload
> > > +	p_payload = &payload;
> > > +	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> > &p_payload, 1);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +	CU_ASSERT_EQUAL(payload, 10);
> > > +
> > > +	//signal on point 16
> > > +	sp3.syncobj_handle = syncobj_handle;
> > > +	sp3.point = 16;
> > > +	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +	//CPU wait on point 16
> > > +	wait_point = 16;
> > > +	r = amdgpu_cs_syncobj_timeline_wait(device_handle,
> > &syncobj_handle,
> > > +					    &wait_point, 1,
> > > +					    0x10000000000, //10s
> > > +
> > DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> > > +
> > DRM_SYNCOBJ_WAIT_FLAGS_WAIT_COMPLETED |
> > > +
> > DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> > > +					    NULL);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +	r = pthread_join(c_thread, &tmp);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +	CU_ASSERT_EQUAL(tmp, 0);
> > > +
> > > +	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> > > +	CU_ASSERT_EQUAL(r, 0);
> > > +
> > > +}
> > > --
> > > 2.17.1
> > >
> > > _______________________________________________
> > > dri-devel mailing list
> > > dri-devel@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> > 
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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