From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>,
Feifei Xu <Feifei.Xu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting
Date: Wed, 12 Sep 2018 14:29:26 -0500 [thread overview]
Message-ID: <20180912192933.28712-10-alexander.deucher@amd.com> (raw)
In-Reply-To: <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
From: Feifei Xu <Feifei.Xu@amd.com>
Golden register settings from the hw team.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 ++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7b9e1c274c59..4991ae00a4ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -187,6 +187,29 @@ static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
};
+static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
+{
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+};
+
static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
@@ -255,6 +278,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
#define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x24000042
+#define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -294,6 +318,17 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
ARRAY_SIZE(golden_settings_gc_9_0_vg20));
break;
case CHIP_RAVEN:
+ soc15_program_register_sequence(adev, golden_settings_gc_9_1,
+ ARRAY_SIZE(golden_settings_gc_9_1));
+ if (adev->rev_id >= 8)
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_9_1_rv2,
+ ARRAY_SIZE(golden_settings_gc_9_1_rv2));
+ else
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_9_1_rv1,
+ ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ break;
case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_gc_9_1,
@@ -1288,7 +1323,10 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
- gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
+ if (adev->rev_id >= 8)
+ gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
+ else
+ gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
break;
case CHIP_PICASSO:
adev->gfx.config.max_hw_contexts = 8;
--
2.13.6
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next prev parent reply other threads:[~2018-09-12 19:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-12 19:29 [PATCH 00/16] Add support for Raven2 Alex Deucher
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 19:29 ` [PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 02/16] drm/amdgpu: set external rev id for raven2 Alex Deucher
2018-09-12 19:29 ` [PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support Alex Deucher
2018-09-12 19:29 ` [PATCH 05/16] drm/amdgpu: add psp support for raven2 Alex Deucher
2018-09-12 19:29 ` [PATCH 06/16] drm/amdgpu/sdma4: specify raven2 firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting Alex Deucher
2018-09-12 19:29 ` [PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware Alex Deucher
2018-09-12 19:29 ` Alex Deucher [this message]
2018-09-12 19:29 ` [PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram Alex Deucher
2018-09-12 19:29 ` [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc Alex Deucher
[not found] ` <20180912192933.28712-12-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 20:10 ` Alex Deucher
[not found] ` <CADnq5_PsBONPZyirw5BVGNb=sf5_9njE6=jXBm0d7RjqC8=i+g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-12 20:43 ` Harry Wentland
[not found] ` <4a0826ff-d3a2-4f6f-2c74-d262e6ec70b3-5C7GfCeVMHo@public.gmane.org>
2018-09-12 20:56 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible Alex Deucher
2018-09-12 19:29 ` [PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2) Alex Deucher
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