From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>,
Bhawanpreet Lakha
<Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc
Date: Wed, 12 Sep 2018 14:29:28 -0500 [thread overview]
Message-ID: <20180912192933.28712-12-alexander.deucher@amd.com> (raw)
In-Reply-To: <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Add Raven2 definitions in the dc code
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../amd/display/dc/bios/command_table_helper2.c | 5 +++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 +++++
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 7 +++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 5 +++
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 5 +++
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +++
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +++++
drivers/gpu/drm/amd/display/include/dal_types.h | 3 ++
9 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index bbbcef566c55..65b006ad372e 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -61,6 +61,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+ return true;
+#endif
case DCE_VERSION_12_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d981755d1e4d..721dd13d2ed2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -88,6 +88,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case FAMILY_RV:
dc_version = DCN_VERSION_1_0;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
+ dc_version = DCN_VERSION_1_01;
+#endif
break;
#endif
default:
@@ -138,6 +142,9 @@ struct resource_pool *dc_create_resource_pool(
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
res_pool = dcn10_create_resource_pool(
num_virtual_links, dc);
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 5a9f3601ffb6..ae3c44aff1c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -601,6 +601,9 @@ static uint32_t dce110_get_pix_clk_dividers(
case DCN_VERSION_1_0:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
dce112_get_pix_clk_dividers_helper(clk_src,
pll_settings, pix_clk_params);
break;
@@ -907,6 +910,10 @@ static bool dce110_program_pix_clk(
case DCN_VERSION_1_0:
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+#endif
+
if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
pll_settings->use_external_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 1b519f8f044f..65a596ffa02a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -152,7 +152,10 @@ enum dcn10_clk_src_array_id {
DCN10_CLK_SRC_PLL1,
DCN10_CLK_SRC_PLL2,
DCN10_CLK_SRC_PLL3,
- DCN10_CLK_SRC_TOTAL
+ DCN10_CLK_SRC_TOTAL,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
+#endif
};
/* begin *********************
@@ -1163,6 +1166,10 @@ static bool construct(
/* max pipe num for ASIC before check pipe fuses */
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
+ pool->base.pipe_count = 3;
+#endif
dc->caps.max_video_width = 3840;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 100;
@@ -1194,13 +1201,28 @@ static bool construct(
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL2,
&clk_src_regs[2], false);
+
+#ifdef CONFIG_DRM_AMD_DC_DCN1_01
+ if (dc->ctx->dce_version == DCN_VERSION_1_0) {
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL3,
+ &clk_src_regs[3], false);
+ }
+#else
pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL3,
&clk_src_regs[3], false);
+#endif
pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01)
+ pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
+#endif
+
pool->base.dp_clock_source =
dcn10_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_ID_DP_DTO,
@@ -1246,6 +1268,18 @@ static bool construct(
memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ if (dc->ctx->dce_version == DCN_VERSION_1_01) {
+ struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
+ struct dcn_ip_params *dcn_ip = dc->dcn_ip;
+ struct display_mode_lib *dml = &dc->dml;
+
+ dml->ip.max_num_dpp = 3;
+ /* TODO how to handle 23.84? */
+ dcn_soc->dram_clock_change_latency = 23;
+ dcn_ip->max_num_dpp = 3;
+ }
+#endif
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc->dcn_soc->urgent_latency = 3;
dc->debug.disable_dmcu = true;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 0caee3523017..a683f4102e65 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -86,6 +86,11 @@ bool dal_hw_factory_init(
dal_hw_factory_dcn10_init(factory);
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ dal_hw_factory_dcn10_init(factory);
+ return true;
+#endif
default:
ASSERT_CRITICAL(false);
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 55c707488541..096f45628630 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -83,6 +83,11 @@ bool dal_hw_translate_init(
dal_hw_translate_dcn10_init(translate);
return true;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ dal_hw_translate_dcn10_init(translate);
+ return true;
+#endif
default:
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index 9b0bcc6b769b..e56093f26eed 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -96,6 +96,10 @@ struct i2caux *dal_i2caux_create(
return dal_i2caux_dcn10_create(ctx);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ case DCN_VERSION_1_01:
+ return dal_i2caux_dcn10_create(ctx);
+#endif
default:
BREAK_TO_DEBUGGER();
return NULL;
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 25029ed42d89..4f501ddcfb8d 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -131,8 +131,15 @@
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
#define RAVEN_A0 0x01
#define RAVEN_B0 0x21
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+/* DCN1_01 */
+#define RAVEN2_A0 0x81
+#endif
#define RAVEN_UNKNOWN 0xFF
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
+#endif /* DCN1_01 */
#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
#define RAVEN1_F0 0xF0
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 840142b65f8b..89627133e188 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -44,6 +44,9 @@ enum dce_version {
DCE_VERSION_12_0,
DCE_VERSION_MAX,
DCN_VERSION_1_0,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+ DCN_VERSION_1_01,
+#endif /* DCN1_01 */
DCN_VERSION_MAX
};
--
2.13.6
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2018-09-12 19:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-12 19:29 [PATCH 00/16] Add support for Raven2 Alex Deucher
[not found] ` <20180912192933.28712-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 19:29 ` [PATCH 01/16] drm/amdgpu: move get_rev_id at first before load gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 02/16] drm/amdgpu: set external rev id for raven2 Alex Deucher
2018-09-12 19:29 ` [PATCH 03/16] drm/amdgpu: add raven2 to gpu_info firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 04/16] drm/amdgpu: add raven2 vcn firmware support Alex Deucher
2018-09-12 19:29 ` [PATCH 05/16] drm/amdgpu: add psp support for raven2 Alex Deucher
2018-09-12 19:29 ` [PATCH 06/16] drm/amdgpu/sdma4: specify raven2 firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 07/16] drm/amdgpu/sdma4: Add raven2 golden setting Alex Deucher
2018-09-12 19:29 ` [PATCH 08/16] drm/amdgpu/gfx9: add support for raven2 gfx firmware Alex Deucher
2018-09-12 19:29 ` [PATCH 09/16] drm/amdgpu/gfx9: add raven2 golden setting Alex Deucher
2018-09-12 19:29 ` [PATCH 10/16] drm/amdgpu: fix the VM fault while write at the top of the invisible vram Alex Deucher
2018-09-12 19:29 ` Alex Deucher [this message]
[not found] ` <20180912192933.28712-12-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-09-12 20:10 ` [PATCH 11/16] drm/amd/display: Add Raven2 definitions in dc Alex Deucher
[not found] ` <CADnq5_PsBONPZyirw5BVGNb=sf5_9njE6=jXBm0d7RjqC8=i+g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-09-12 20:43 ` Harry Wentland
[not found] ` <4a0826ff-d3a2-4f6f-2c74-d262e6ec70b3-5C7GfCeVMHo@public.gmane.org>
2018-09-12 20:56 ` Alex Deucher
2018-09-12 19:29 ` [PATCH 12/16] drm/amd/display: Add DC config flag for Raven2 (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 13/16] drm/amd/powerplay: update smu10_verify_smc_interface() to be raven2 compatible Alex Deucher
2018-09-12 19:29 ` [PATCH 14/16] drm/amd/powerplay: round up the Mhz convertion (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 15/16] drm/amd/powerplay: disable raven2 force dpm level support (v2) Alex Deucher
2018-09-12 19:29 ` [PATCH 16/16] drm/amdgpu: set CG flags for raven2 (v2) Alex Deucher
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180912192933.28712-12-alexander.deucher@amd.com \
--to=alexdeucher-re5jqeeqqe8avxtiumwx3w@public.gmane.org \
--cc=Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org \
--cc=alexander.deucher-5C7GfCeVMHo@public.gmane.org \
--cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox