[PATCH 1/4] drm/amd/powerplay: fix Vega10 mclk/socclk voltage link setup

[PATCH 1/4] drm/amd/powerplay: fix Vega10 mclk/socclk voltage link setup

[Evan Quan]

This may affects the Vega10 MCLK OD functionality.

Change-Id: Icd685187501b4ec8867fb3c5077ea2664edbd114
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 35 +++++++++++++------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index d5d0db456021..138f9f9ea765 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5016,7 +5016,7 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
 	struct vega10_hwmgr *data = hwmgr->backend;
 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
-	struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.soc_table;
+	struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
 
 	struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
 							&data->odn_dpm_table.vdd_dep_on_socclk;
@@ -5040,7 +5040,8 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
 					break;
 			}
 			if (j == od_vddc_lookup_table->count) {
-				od_vddc_lookup_table->entries[j-1].us_vdd =
+				j = od_vddc_lookup_table->count - 1;
+				od_vddc_lookup_table->entries[j].us_vdd =
 					podn_vdd_dep->entries[i].vddc;
 				data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
 			}
@@ -5048,23 +5049,35 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
 		}
 		dpm_table = &data->dpm_table.soc_table;
 		for (i = 0; i < dep_table->count; i++) {
-			if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[dep_table->count-1].vddInd &&
-					dep_table->entries[i].clk < podn_vdd_dep->entries[dep_table->count-1].clk) {
+			if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
+					dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
 				data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
-				podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
-				dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
+				for (; (i < dep_table->count) &&
+				       (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
+					podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
+					dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
+				}
+				break;
+			} else {
+				dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
+				podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
+				podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
+				podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
 			}
 		}
 		if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
-					podn_vdd_dep->entries[dep_table->count-1].clk) {
+					podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
 			data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
-			podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = podn_vdd_dep->entries[dep_table->count-1].clk;
-			dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = podn_vdd_dep->entries[dep_table->count-1].clk;
+			podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
+				podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
+			dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
+				podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
 		}
 		if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
-					podn_vdd_dep->entries[dep_table->count-1].vddInd) {
+					podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
 			data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
-			podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = podn_vdd_dep->entries[dep_table->count-1].vddInd;
+			podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
+				podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
 		}
 	}
 }
-- 
2.21.0

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[PATCH 2/4] drm/amd/powerplay: valid Vega10 DPMTABLE_OD_UPDATE_VDDC settings

[Evan Quan]

With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS
will be disabled. However, the buggy code makes this actually not
working as expected.

Change-Id: Ifa83a6255bb3f6fa4bdb4de616521cb7bab6830a
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 138f9f9ea765..103f7e3f0783 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2466,11 +2466,6 @@ static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
 			return;
 		}
 	}
-
-	if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
-		data->need_update_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
-		data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
-	}
 }
 
 /**
@@ -3683,7 +3678,7 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
 
 	vega10_update_avfs(hwmgr);
 
-	data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
+	data->need_update_dpm_table = 0;
 
 	return 0;
 }
-- 
2.21.0

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RE: [PATCH 2/4] drm/amd/powerplay: valid Vega10 DPMTABLE_OD_UPDATE_VDDC settings

[Quan, Evan]

Just sent out a V2 version and drop this one.

> -----Original Message-----
> From: Evan Quan <evan.quan@amd.com>
> Sent: 2019年5月7日 14:09
> To: amd-gfx@lists.freedesktop.org
> Cc: yanik@yiannakis.de; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 2/4] drm/amd/powerplay: valid Vega10
> DPMTABLE_OD_UPDATE_VDDC settings
> 
> With user specified voltage(DPMTABLE_OD_UPDATE_VDDC), the AVFS will
> be disabled. However, the buggy code makes this actually not working as
> expected.
> 
> Change-Id: Ifa83a6255bb3f6fa4bdb4de616521cb7bab6830a
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 138f9f9ea765..103f7e3f0783 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2466,11 +2466,6 @@ static void
> vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
>  			return;
>  		}
>  	}
> -
> -	if (data->need_update_dpm_table &
> DPMTABLE_OD_UPDATE_VDDC) {
> -		data->need_update_dpm_table &=
> ~DPMTABLE_OD_UPDATE_VDDC;
> -		data->need_update_dpm_table |=
> DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
> -	}
>  }
> 
>  /**
> @@ -3683,7 +3678,7 @@ static int vega10_set_power_state_tasks(struct
> pp_hwmgr *hwmgr,
> 
>  	vega10_update_avfs(hwmgr);
> 
> -	data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
> +	data->need_update_dpm_table = 0;
> 
>  	return 0;
>  }
> --
> 2.21.0

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[PATCH 3/4] drm/amd/powerplay: avoid repeat AVFS enablement/disablement

[Evan Quan]

No need to enable or disable AVFS if it's already in wanted
state.

Change-Id: I862c0c3d642e6a0dc7bb34e04c5a59f17b6b8deb
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 103f7e3f0783..f4b81f50b185 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2364,6 +2364,10 @@ static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
 	struct vega10_hwmgr *data = hwmgr->backend;
 
 	if (data->smu_features[GNLD_AVFS].supported) {
+		/* Already enabled or disabled */
+		if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
+			return 0;
+
 		if (enable) {
 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
 					true,
-- 
2.21.0

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[PATCH 4/4] drm/amd/powerplay: update Vega10 power state on OD

[Evan Quan]

Update Vega10 top performance level power state accordingly
on OD.

Change-Id: Iaadeefb2904222bf5f4d54b39d7179ce53f92ac0
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f4b81f50b185..4878938ecf33 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5009,6 +5009,63 @@ static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
 	return true;
 }
 
+static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
+{
+	struct vega10_hwmgr *data = hwmgr->backend;
+	struct pp_power_state *ps = hwmgr->request_ps;
+	struct vega10_power_state *vega10_ps;
+	struct vega10_single_dpm_table *gfx_dpm_table =
+		&data->dpm_table.gfx_table;
+	struct vega10_single_dpm_table *soc_dpm_table =
+		&data->dpm_table.soc_table;
+	struct vega10_single_dpm_table *mem_dpm_table =
+		&data->dpm_table.mem_table;
+	int max_level;
+
+	if (!ps)
+		return;
+
+	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
+	max_level = vega10_ps->performance_level_count - 1;
+
+	if (vega10_ps->performance_levels[max_level].gfx_clock !=
+	    gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
+		vega10_ps->performance_levels[max_level].gfx_clock =
+			gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
+
+	if (vega10_ps->performance_levels[max_level].soc_clock !=
+	    soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
+		vega10_ps->performance_levels[max_level].soc_clock =
+			soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
+
+	if (vega10_ps->performance_levels[max_level].mem_clock !=
+	    mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
+		vega10_ps->performance_levels[max_level].mem_clock =
+			mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
+
+	if (!hwmgr->ps)
+		return;
+
+	ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
+	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
+	max_level = vega10_ps->performance_level_count - 1;
+
+	if (vega10_ps->performance_levels[max_level].gfx_clock !=
+	    gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
+		vega10_ps->performance_levels[max_level].gfx_clock =
+			gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
+
+	if (vega10_ps->performance_levels[max_level].soc_clock !=
+	    soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
+		vega10_ps->performance_levels[max_level].soc_clock =
+			soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
+
+	if (vega10_ps->performance_levels[max_level].mem_clock !=
+	    mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
+		vega10_ps->performance_levels[max_level].mem_clock =
+			mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
+}
+
 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
 						enum PP_OD_DPM_TABLE_COMMAND type)
 {
@@ -5079,6 +5136,7 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
 				podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
 		}
 	}
+	vega10_odn_update_power_state(hwmgr);
 }
 
 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
@@ -5113,6 +5171,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
 	} else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
 		memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
 		vega10_odn_initial_default_setting(hwmgr);
+		vega10_odn_update_power_state(hwmgr);
 		return 0;
 	} else if (PP_OD_COMMIT_DPM_TABLE == type) {
 		vega10_check_dpm_table_updated(hwmgr);
-- 
2.21.0

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Re: [PATCH 4/4] drm/amd/powerplay: update Vega10 power state on OD

[Alex Deucher]

On Tue, May 7, 2019 at 2:09 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Update Vega10 top performance level power state accordingly
> on OD.
>
> Change-Id: Iaadeefb2904222bf5f4d54b39d7179ce53f92ac0
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 59 +++++++++++++++++++
>  1 file changed, 59 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index f4b81f50b185..4878938ecf33 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -5009,6 +5009,63 @@ static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
>         return true;
>  }
>
> +static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
> +{
> +       struct vega10_hwmgr *data = hwmgr->backend;
> +       struct pp_power_state *ps = hwmgr->request_ps;
> +       struct vega10_power_state *vega10_ps;
> +       struct vega10_single_dpm_table *gfx_dpm_table =
> +               &data->dpm_table.gfx_table;
> +       struct vega10_single_dpm_table *soc_dpm_table =
> +               &data->dpm_table.soc_table;
> +       struct vega10_single_dpm_table *mem_dpm_table =
> +               &data->dpm_table.mem_table;
> +       int max_level;
> +
> +       if (!ps)
> +               return;
> +
> +       vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> +       max_level = vega10_ps->performance_level_count - 1;
> +
> +       if (vega10_ps->performance_levels[max_level].gfx_clock !=
> +           gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
> +               vega10_ps->performance_levels[max_level].gfx_clock =
> +                       gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
> +
> +       if (vega10_ps->performance_levels[max_level].soc_clock !=
> +           soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
> +               vega10_ps->performance_levels[max_level].soc_clock =
> +                       soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
> +
> +       if (vega10_ps->performance_levels[max_level].mem_clock !=
> +           mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
> +               vega10_ps->performance_levels[max_level].mem_clock =
> +                       mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
> +
> +       if (!hwmgr->ps)
> +               return;
> +
> +       ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
> +       vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
> +       max_level = vega10_ps->performance_level_count - 1;
> +
> +       if (vega10_ps->performance_levels[max_level].gfx_clock !=
> +           gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
> +               vega10_ps->performance_levels[max_level].gfx_clock =
> +                       gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
> +
> +       if (vega10_ps->performance_levels[max_level].soc_clock !=
> +           soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
> +               vega10_ps->performance_levels[max_level].soc_clock =
> +                       soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
> +
> +       if (vega10_ps->performance_levels[max_level].mem_clock !=
> +           mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
> +               vega10_ps->performance_levels[max_level].mem_clock =
> +                       mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
> +}
> +
>  static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
>                                                 enum PP_OD_DPM_TABLE_COMMAND type)
>  {
> @@ -5079,6 +5136,7 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
>                                 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
>                 }
>         }
> +       vega10_odn_update_power_state(hwmgr);
>  }
>
>  static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
> @@ -5113,6 +5171,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
>         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
>                 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
>                 vega10_odn_initial_default_setting(hwmgr);
> +               vega10_odn_update_power_state(hwmgr);
>                 return 0;
>         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
>                 vega10_check_dpm_table_updated(hwmgr);
> --
> 2.21.0
>
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