* [PATCH 1/2] drm/amdgpu: move the VCN DPG mode read and write to VCN
@ 2019-05-13 17:19 Liu, Leo
[not found] ` <20190513171745.7890-1-leo.liu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Liu, Leo @ 2019-05-13 17:19 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Liu, Leo
Since this is VCN specific and only used by VCN
Signed-off-by: Leo Liu <leo.liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 20 ++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 21 ---------------------
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a0ad19af9080..d29a5c9545bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -45,6 +45,26 @@
#define VCN_ENC_CMD_REG_WRITE 0x0000000b
#define VCN_ENC_CMD_REG_WAIT 0x0000000c
+#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
+ ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
+ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
+ UVD_DPG_LMA_CTL__MASK_EN_MASK | \
+ ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
+ << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
+ (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
+ RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })
+
+#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
+ do { \
+ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
+ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
+ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
+ UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
+ ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
+ << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
+ (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
+ } while (0)
+
enum engine_status_constants {
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index c634606e64bd..47f74dab365d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -69,27 +69,6 @@
} \
} while (0)
-#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
- ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
- UVD_DPG_LMA_CTL__MASK_EN_MASK | \
- ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
- << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
- (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
- RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })
-
-#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
- do { \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
- UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
- ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
- << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
- (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
- } while (0)
-
-
#define WREG32_RLC(reg, value) \
do { \
if (amdgpu_virt_support_rlc_prg_reg(adev)) { \
--
2.17.1
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* [PATCH 2/2] drm/amdgpu: make VCN DPG pause mode detached from general VCN [not found] ` <20190513171745.7890-1-leo.liu-5C7GfCeVMHo@public.gmane.org> @ 2019-05-13 17:19 ` Liu, Leo [not found] ` <20190513171745.7890-2-leo.liu-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 3+ messages in thread From: Liu, Leo @ 2019-05-13 17:19 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Liu, Leo It should be attached to VCN 1.0 Signed-off-by: Leo Liu <leo.liu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 130 +---------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 132 +++++++++++++++++++++++- 3 files changed, 135 insertions(+), 129 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index ecf6f96df2ad..01545ff87424 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -212,132 +212,6 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) return 0; } -static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, - struct dpg_pause_state *new_state) -{ - int ret_code; - uint32_t reg_data = 0; - uint32_t reg_data2 = 0; - struct amdgpu_ring *ring; - - /* pause/unpause if state is changed */ - if (adev->vcn.pause_state.fw_based != new_state->fw_based) { - DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", - adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, - new_state->fw_based, new_state->jpeg); - - reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & - (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); - - if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { - ret_code = 0; - - if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, - UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); - - if (!ret_code) { - /* pause DPG non-jpeg */ - reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, - UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, - UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); - - /* Restore */ - ring = &adev->vcn.ring_enc[0]; - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); - WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); - WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); - - ring = &adev->vcn.ring_enc[1]; - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); - WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); - WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); - - ring = &adev->vcn.ring_dec; - WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, - RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, - UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); - } - } else { - /* unpause dpg non-jpeg, no need to wait */ - reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); - } - adev->vcn.pause_state.fw_based = new_state->fw_based; - } - - /* pause/unpause if state is changed */ - if (adev->vcn.pause_state.jpeg != new_state->jpeg) { - DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", - adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, - new_state->fw_based, new_state->jpeg); - - reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & - (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); - - if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { - ret_code = 0; - - if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, - UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); - - if (!ret_code) { - /* Make sure JPRG Snoop is disabled before sending the pause */ - reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); - reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; - WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); - - /* pause DPG jpeg */ - reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, - UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, - UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); - - /* Restore */ - ring = &adev->vcn.ring_jpeg; - WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, - UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | - UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); - WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, - lower_32_bits(ring->gpu_addr)); - WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, - upper_32_bits(ring->gpu_addr)); - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, - UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); - - ring = &adev->vcn.ring_dec; - WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, - RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, - UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); - } - } else { - /* unpause dpg jpeg, no need to wait */ - reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); - } - adev->vcn.pause_state.jpeg = new_state->jpeg; - } - - return 0; -} - static void amdgpu_vcn_idle_work_handler(struct work_struct *work) { struct amdgpu_device *adev = @@ -362,7 +236,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) else new_state.jpeg = VCN_DPG_STATE__UNPAUSE; - amdgpu_vcn_pause_dpg_mode(adev, &new_state); + adev->vcn.vcn_pause_dpg_mode(adev, &new_state); } fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg); @@ -417,7 +291,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) new_state.jpeg = VCN_DPG_STATE__PAUSE; - amdgpu_vcn_pause_dpg_mode(adev, &new_state); + adev->vcn.vcn_pause_dpg_mode(adev, &new_state); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index d29a5c9545bd..cee0f263d159 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -101,6 +101,8 @@ struct amdgpu_vcn { unsigned num_enc_rings; enum amd_powergating_state cur_state; struct dpg_pause_state pause_state; + int (*vcn_pause_dpg_mode)(struct amdgpu_device *adev, + struct dpg_pause_state *new_state); }; int amdgpu_vcn_sw_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index ac2e5a1eb576..a5ab676cb4ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -49,6 +49,8 @@ static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); +static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, + struct dpg_pause_state *new_state); /** * vcn_v1_0_early_init - set function pointers @@ -140,7 +142,9 @@ static int vcn_v1_0_sw_init(void *handle) if (r) return r; - return r; + adev->vcn.vcn_pause_dpg_mode = vcn_v1_0_pause_dpg_mode; + + return 0; } /** @@ -1204,6 +1208,132 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) return r; } +static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, + struct dpg_pause_state *new_state) +{ + int ret_code; + uint32_t reg_data = 0; + uint32_t reg_data2 = 0; + struct amdgpu_ring *ring; + + /* pause/unpause if state is changed */ + if (adev->vcn.pause_state.fw_based != new_state->fw_based) { + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, + new_state->fw_based, new_state->jpeg); + + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { + ret_code = 0; + + if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + + if (!ret_code) { + /* pause DPG non-jpeg */ + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); + + /* Restore */ + ring = &adev->vcn.ring_enc[0]; + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); + + ring = &adev->vcn.ring_enc[1]; + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); + + ring = &adev->vcn.ring_dec; + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, + RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + } + } else { + /* unpause dpg non-jpeg, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + } + adev->vcn.pause_state.fw_based = new_state->fw_based; + } + + /* pause/unpause if state is changed */ + if (adev->vcn.pause_state.jpeg != new_state->jpeg) { + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, + new_state->fw_based, new_state->jpeg); + + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); + + if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { + ret_code = 0; + + if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + + if (!ret_code) { + /* Make sure JPRG Snoop is disabled before sending the pause */ + reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); + reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); + + /* pause DPG jpeg */ + reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); + + /* Restore */ + ring = &adev->vcn.ring_jpeg; + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, + UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); + + ring = &adev->vcn.ring_dec; + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, + RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + } + } else { + /* unpause dpg jpeg, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); + } + adev->vcn.pause_state.jpeg = new_state->jpeg; + } + + return 0; +} + static bool vcn_v1_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <20190513171745.7890-2-leo.liu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 2/2] drm/amdgpu: make VCN DPG pause mode detached from general VCN [not found] ` <20190513171745.7890-2-leo.liu-5C7GfCeVMHo@public.gmane.org> @ 2019-05-13 17:24 ` Alex Deucher 0 siblings, 0 replies; 3+ messages in thread From: Alex Deucher @ 2019-05-13 17:24 UTC (permalink / raw) To: Liu, Leo; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org On Mon, May 13, 2019 at 1:19 PM Liu, Leo <Leo.Liu@amd.com> wrote: > > It should be attached to VCN 1.0 > > Signed-off-by: Leo Liu <leo.liu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 130 +---------------------- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 + > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 132 +++++++++++++++++++++++- > 3 files changed, 135 insertions(+), 129 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index ecf6f96df2ad..01545ff87424 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -212,132 +212,6 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) > return 0; > } > > -static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, > - struct dpg_pause_state *new_state) > -{ > - int ret_code; > - uint32_t reg_data = 0; > - uint32_t reg_data2 = 0; > - struct amdgpu_ring *ring; > - > - /* pause/unpause if state is changed */ > - if (adev->vcn.pause_state.fw_based != new_state->fw_based) { > - DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", > - adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, > - new_state->fw_based, new_state->jpeg); > - > - reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & > - (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); > - > - if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { > - ret_code = 0; > - > - if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) > - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > - UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, > - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > - > - if (!ret_code) { > - /* pause DPG non-jpeg */ > - reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; > - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, > - UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, > - UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); > - > - /* Restore */ > - ring = &adev->vcn.ring_enc[0]; > - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > - WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > - WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > - WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > - > - ring = &adev->vcn.ring_enc[1]; > - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); > - WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); > - WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); > - WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); > - WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); > - > - ring = &adev->vcn.ring_dec; > - WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > - RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > - UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, > - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > - } > - } else { > - /* unpause dpg non-jpeg, no need to wait */ > - reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; > - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > - } > - adev->vcn.pause_state.fw_based = new_state->fw_based; > - } > - > - /* pause/unpause if state is changed */ > - if (adev->vcn.pause_state.jpeg != new_state->jpeg) { > - DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", > - adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, > - new_state->fw_based, new_state->jpeg); > - > - reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & > - (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); > - > - if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { > - ret_code = 0; > - > - if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) > - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > - UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, > - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > - > - if (!ret_code) { > - /* Make sure JPRG Snoop is disabled before sending the pause */ > - reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); > - reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; > - WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); > - > - /* pause DPG jpeg */ > - reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; > - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, > - UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, > - UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); > - > - /* Restore */ > - ring = &adev->vcn.ring_jpeg; > - WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); > - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > - UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | > - UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); > - WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, > - lower_32_bits(ring->gpu_addr)); > - WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, > - upper_32_bits(ring->gpu_addr)); > - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); > - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); > - WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > - UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); > - > - ring = &adev->vcn.ring_dec; > - WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > - RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > - SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > - UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, > - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > - } > - } else { > - /* unpause dpg jpeg, no need to wait */ > - reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; > - WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > - } > - adev->vcn.pause_state.jpeg = new_state->jpeg; > - } > - > - return 0; > -} > - > static void amdgpu_vcn_idle_work_handler(struct work_struct *work) > { > struct amdgpu_device *adev = > @@ -362,7 +236,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) > else > new_state.jpeg = VCN_DPG_STATE__UNPAUSE; > > - amdgpu_vcn_pause_dpg_mode(adev, &new_state); > + adev->vcn.vcn_pause_dpg_mode(adev, &new_state); > } > > fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg); > @@ -417,7 +291,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) > else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) > new_state.jpeg = VCN_DPG_STATE__PAUSE; > > - amdgpu_vcn_pause_dpg_mode(adev, &new_state); > + adev->vcn.vcn_pause_dpg_mode(adev, &new_state); > } > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h > index d29a5c9545bd..cee0f263d159 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h > @@ -101,6 +101,8 @@ struct amdgpu_vcn { > unsigned num_enc_rings; > enum amd_powergating_state cur_state; > struct dpg_pause_state pause_state; > + int (*vcn_pause_dpg_mode)(struct amdgpu_device *adev, > + struct dpg_pause_state *new_state); Can probably drop the vcn in the function pointer name since it's already part of the vcn struct. E.g., int (*pause_dpg_mode)(struct amdgpu_device *adev, struct dpg_pause_state *new_state); Either way, series is: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > }; > > int amdgpu_vcn_sw_init(struct amdgpu_device *adev); > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index ac2e5a1eb576..a5ab676cb4ac 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -49,6 +49,8 @@ static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); > static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); > static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr); > static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); > +static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, > + struct dpg_pause_state *new_state); > > /** > * vcn_v1_0_early_init - set function pointers > @@ -140,7 +142,9 @@ static int vcn_v1_0_sw_init(void *handle) > if (r) > return r; > > - return r; > + adev->vcn.vcn_pause_dpg_mode = vcn_v1_0_pause_dpg_mode; > + > + return 0; > } > > /** > @@ -1204,6 +1208,132 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) > return r; > } > > +static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, > + struct dpg_pause_state *new_state) > +{ > + int ret_code; > + uint32_t reg_data = 0; > + uint32_t reg_data2 = 0; > + struct amdgpu_ring *ring; > + > + /* pause/unpause if state is changed */ > + if (adev->vcn.pause_state.fw_based != new_state->fw_based) { > + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", > + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, > + new_state->fw_based, new_state->jpeg); > + > + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & > + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); > + > + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { > + ret_code = 0; > + > + if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + > + if (!ret_code) { > + /* pause DPG non-jpeg */ > + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, > + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, > + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); > + > + /* Restore */ > + ring = &adev->vcn.ring_enc[0]; > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); > + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); > + > + ring = &adev->vcn.ring_enc[1]; > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); > + WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); > + WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); > + WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); > + > + ring = &adev->vcn.ring_dec; > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > + RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + } > + } else { > + /* unpause dpg non-jpeg, no need to wait */ > + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + } > + adev->vcn.pause_state.fw_based = new_state->fw_based; > + } > + > + /* pause/unpause if state is changed */ > + if (adev->vcn.pause_state.jpeg != new_state->jpeg) { > + DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", > + adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, > + new_state->fw_based, new_state->jpeg); > + > + reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & > + (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); > + > + if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { > + ret_code = 0; > + > + if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + > + if (!ret_code) { > + /* Make sure JPRG Snoop is disabled before sending the pause */ > + reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); > + reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); > + > + /* pause DPG jpeg */ > + reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, > + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, > + UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); > + > + /* Restore */ > + ring = &adev->vcn.ring_jpeg; > + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > + UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | > + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); > + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, > + lower_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, > + upper_32_bits(ring->gpu_addr)); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); > + WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > + UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); > + > + ring = &adev->vcn.ring_dec; > + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > + RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > + SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, > + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, > + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); > + } > + } else { > + /* unpause dpg jpeg, no need to wait */ > + reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; > + WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); > + } > + adev->vcn.pause_state.jpeg = new_state->jpeg; > + } > + > + return 0; > +} > + > static bool vcn_v1_0_is_idle(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-05-13 17:19 [PATCH 1/2] drm/amdgpu: move the VCN DPG mode read and write to VCN Liu, Leo
[not found] ` <20190513171745.7890-1-leo.liu-5C7GfCeVMHo@public.gmane.org>
2019-05-13 17:19 ` [PATCH 2/2] drm/amdgpu: make VCN DPG pause mode detached from general VCN Liu, Leo
[not found] ` <20190513171745.7890-2-leo.liu-5C7GfCeVMHo@public.gmane.org>
2019-05-13 17:24 ` Alex Deucher
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