From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Dennis Li <dennis.li-5C7GfCeVMHo@public.gmane.org>,
Hawking Zhang <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 05/26] drm/amdgpu: add umc v6_1_1 IP headers
Date: Wed, 31 Jul 2019 12:57:57 -0500 [thread overview]
Message-ID: <20190731175818.20159-6-alexander.deucher@amd.com> (raw)
In-Reply-To: <20190731175818.20159-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
From: Hawking Zhang <Hawking.Zhang@amd.com>
the change introduces IP headers for unified memory controller (umc)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
---
.../include/asic_reg/umc/umc_6_1_1_offset.h | 31 +++++++
.../include/asic_reg/umc/umc_6_1_1_sh_mask.h | 91 +++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
new file mode 100644
index 000000000000..043aa695d63f
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _umc_6_1_1_OFFSET_HEADER
+#define _umc_6_1_1_OFFSET_HEADER
+
+#define mmUMCCH0_0_EccErrCntSel 0x0360
+#define mmUMCCH0_0_EccErrCntSel_BASE_IDX 0
+#define mmUMCCH0_0_EccErrCnt 0x0361
+#define mmUMCCH0_0_EccErrCnt_BASE_IDX 0
+#define mmMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
+#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
new file mode 100644
index 000000000000..45c888280af9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _umc_6_1_1_SH_MASK_HEADER
+#define _umc_6_1_1_SH_MASK_HEADER
+
+//UMCCH0_0_EccErrCntSel
+#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0
+#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT 0xc
+#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf
+#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL
+#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK 0x00003000L
+#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L
+//UMCCH0_0_EccErrCnt
+#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT 0x0
+#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL
+//MCA_UMC_UMC0_MCUMC_STATUST0
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0__SHIFT 0x16
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1__SHIFT 0x26
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2__SHIFT 0x29
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
+#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3__SHIFT 0x2f
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
+#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4__SHIFT 0x36
+#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
+#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
+#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
+#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0_MASK 0x00000000FFC00000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1_MASK 0x000000C000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2_MASK 0x0000060000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3_MASK 0x000F800000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4_MASK 0x0040000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
+#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
+//MCA_UMC_UMC0_MCUMC_ADDRT0
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT 0x38
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x3e
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK 0x3F00000000000000L
+#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xC000000000000000L
+
+#endif
--
2.20.1
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next prev parent reply other threads:[~2019-07-31 17:57 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 17:57 [PATCH 00/26] Further RAS enablement for vega20 Alex Deucher
[not found] ` <20190731175818.20159-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-07-31 17:57 ` [PATCH 01/26] drm/amdgpu: move some ras data structure to amdgpu_ras.h Alex Deucher
2019-07-31 17:57 ` [PATCH 02/26] drm/amdgpu: init RSMU and UMC ip base address for vega20 Alex Deucher
2019-07-31 17:57 ` [PATCH 03/26] drm/amdgpu: add amdgpu_umc_functions structure Alex Deucher
2019-07-31 17:57 ` [PATCH 04/26] drm/amdgpu: add rsmu v_0_0_2 ip headers Alex Deucher
2019-07-31 17:57 ` Alex Deucher [this message]
2019-07-31 17:57 ` [PATCH 06/26] drm/amdgpu: add umc v6_1 query error count support Alex Deucher
2019-07-31 17:57 ` [PATCH 07/26] drm/amdgpu: init umc v6_1 functions for vega20 Alex Deucher
2019-07-31 17:58 ` [PATCH 08/26] drm/amdgpu: querry umc error count Alex Deucher
2019-07-31 17:58 ` [PATCH 09/26] drm/amdgpu: add ras error count after each query (v2) Alex Deucher
2019-07-31 17:58 ` [PATCH 10/26] drm/amdgpu: add RREG64/WREG64(_PCIE) operations Alex Deucher
2019-07-31 17:58 ` [PATCH 11/26] drm/amdgpu: use 64bit operation macros for umc Alex Deucher
2019-07-31 17:58 ` [PATCH 12/26] drm/amdgpu: switch to amdgpu_umc structure Alex Deucher
2019-07-31 17:58 ` [PATCH 13/26] drm/amdgpu: update algorithm of umc uncorrectable error counting Alex Deucher
2019-07-31 17:58 ` [PATCH 14/26] drm/amdgpu: add support for recording ras error address Alex Deucher
2019-07-31 17:58 ` [PATCH 15/26] drm/amdgpu: add structures for umc error address translation Alex Deucher
2019-07-31 17:58 ` [PATCH 16/26] drm/amdgpu: query umc ras error address Alex Deucher
2019-07-31 17:58 ` [PATCH 17/26] drm/amdgpu: allow ras interrupt callback to return error data Alex Deucher
2019-07-31 17:58 ` [PATCH 18/26] drm/amdgpu: update interrupt callback for all ras clients Alex Deucher
2019-07-31 17:58 ` [PATCH 19/26] drm/amdgpu: add check for ras error type Alex Deucher
2019-07-31 17:58 ` [PATCH 20/26] drm/amdgpu: remove ras_reserve_vram in ras injection Alex Deucher
2019-07-31 17:58 ` [PATCH 21/26] drm/amd/include: add bitfield define for EDC registers Alex Deucher
2019-07-31 17:58 ` [PATCH 22/26] drm/amd/include: add define of TCP_EDC_CNT_NEW Alex Deucher
2019-07-31 17:58 ` [PATCH 23/26] drm/amdgpu: add define for gfx ras subblock Alex Deucher
2019-07-31 17:58 ` [PATCH 24/26] drm/amdgpu: add RAS callback for gfx Alex Deucher
[not found] ` <20190731175818.20159-25-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-08-01 5:40 ` Kevin Wang
2019-07-31 17:58 ` [PATCH 25/26] drm/amdgpu: support gfx ras error injection and err_cnt query Alex Deucher
2019-07-31 17:58 ` [PATCH 26/26] drm/amdgpu: disable inject for failed subblocks of gfx Alex Deucher
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