From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: David Francis <David.Francis@amd.com>,
Harry Wentland <harry.wentland@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Sasha Levin <sashal@kernel.org>,
amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [PATCH AUTOSEL 4.19 022/167] powerplay: Respect units on max dcfclk watermark
Date: Tue, 3 Sep 2019 12:22:54 -0400 [thread overview]
Message-ID: <20190903162519.7136-22-sashal@kernel.org> (raw)
In-Reply-To: <20190903162519.7136-1-sashal@kernel.org>
From: David Francis <David.Francis@amd.com>
[ Upstream commit f191415b24a3ad3fa22088af7cd7fc328a2f469f ]
In a refactor, the watermark clock inputs to
powerplay from DC were changed from units of 10kHz to
kHz clocks.
One division by 100 was not converted into a division
by 1000.
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 2aab1b4759459..a321c465b7dce 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -674,7 +674,7 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
- 100);
+ 1000);
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
--
2.20.1
next prev parent reply other threads:[~2019-09-03 16:22 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190903162519.7136-1-sashal@kernel.org>
2019-09-03 16:22 ` [PATCH AUTOSEL 4.19 009/167] drm/amdgpu/gfx9: Update gfx9 golden settings Sasha Levin
2019-09-03 16:22 ` [PATCH AUTOSEL 4.19 010/167] drm/amdgpu: Update gc_9_0 " Sasha Levin
2019-09-03 16:22 ` Sasha Levin [this message]
2019-09-03 16:23 ` [PATCH AUTOSEL 4.19 044/167] drm/amdgpu: validate user pitch alignment Sasha Levin
2019-09-03 16:40 ` Michel Dänzer
2019-09-03 17:03 ` Greg KH
2019-09-03 20:01 ` Sasha Levin
2019-09-03 20:16 ` Daniel Vetter
2019-09-04 8:55 ` Michel Dänzer
2019-09-04 12:08 ` Sasha Levin
2019-09-04 15:05 ` Michel Dänzer
2019-09-07 15:50 ` Joe Perches
2019-09-07 14:58 ` Alex Deucher
[not found] ` <CADnq5_Mfee4xmzMJ-Hmw251QCMfabWPKd8PX+o70D97qdCDJ8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-09-09 15:25 ` Michel Dänzer
2019-09-03 16:23 ` [PATCH AUTOSEL 4.19 045/167] drm/amdgpu: validate user GEM object size Sasha Levin
[not found] ` <20190903162519.7136-1-sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
2019-09-03 16:22 ` [PATCH AUTOSEL 4.19 023/167] drm/amd/pp: Fix truncated clock value when set watermark Sasha Levin
2019-09-03 16:22 ` [PATCH AUTOSEL 4.19 024/167] drm/amd/dm: Understand why attaching path/tile properties are needed Sasha Levin
2019-09-03 16:24 ` [PATCH AUTOSEL 4.19 114/167] drm/amdkfd: Add missing Polaris10 ID Sasha Levin
2019-09-03 16:24 ` [PATCH AUTOSEL 4.19 116/167] drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2) Sasha Levin
2019-09-03 16:24 ` [PATCH AUTOSEL 4.19 117/167] drm/amdgpu/{uvd, vcn}: fetch ring's read_ptr after alloc Sasha Levin
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