* [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK @ 2020-01-25 18:48 Alex Deucher 2020-01-25 18:48 ` [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking Alex Deucher 2020-01-25 18:48 ` [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table Alex Deucher 0 siblings, 2 replies; 12+ messages in thread From: Alex Deucher @ 2020-01-25 18:48 UTC (permalink / raw) To: amd-gfx; +Cc: Alex Deucher You can only adjust the max mclk, not the min. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index f1b27fc20c19..c8f09874c2ec 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -843,7 +843,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) break; size += sprintf(buf + size, "OD_MCLK:\n"); - size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax); + size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax); break; case SMU_OD_VDDC_CURVE: if (!smu->od_enabled || !od_table || !od_settings) -- 2.24.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking 2020-01-25 18:48 [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK Alex Deucher @ 2020-01-25 18:48 ` Alex Deucher 2020-01-25 18:48 ` [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table Alex Deucher 1 sibling, 0 replies; 12+ messages in thread From: Alex Deucher @ 2020-01-25 18:48 UTC (permalink / raw) To: amd-gfx; +Cc: Alex Deucher So users can see the range of valid values. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c8f09874c2ec..d2d45181ae23 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -737,6 +737,15 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl return od_table->cap[feature]; } +static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, + enum SMU_11_0_ODSETTING_ID setting, + uint32_t *min, uint32_t *max) +{ + if (min) + *min = od_table->min[setting]; + if (max) + *max = od_table->max[setting]; +} static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) @@ -755,6 +764,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; struct smu_11_0_overdrive_table *od_settings = smu->od_settings; + uint32_t min_value, max_value; switch (clk_type) { case SMU_GFXCLK: @@ -867,6 +877,55 @@ static int navi10_print_clk_levels(struct smu_context *smu, } size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE); } + break; + case SMU_OD_RANGE: + if (!smu->od_enabled || !od_table || !od_settings) + break; + size = sprintf(buf, "%s:\n", "OD_RANGE"); + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, + &min_value, NULL); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, + NULL, &max_value); + size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", + min_value, max_value); + } + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, + &min_value, &max_value); + size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", + min_value, max_value); + } + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", + min_value, max_value); + } + break; default: break; -- 2.24.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table 2020-01-25 18:48 [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK Alex Deucher 2020-01-25 18:48 ` [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking Alex Deucher @ 2020-01-25 18:48 ` Alex Deucher 2020-01-28 16:44 ` Matt Coffin 1 sibling, 1 reply; 12+ messages in thread From: Alex Deucher @ 2020-01-25 18:48 UTC (permalink / raw) To: amd-gfx; +Cc: Alex Deucher Was missing before. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index d2d45181ae23..f60762f9b143 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -2062,6 +2062,14 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL if (ret) return ret; od_table->UclkFmax = input[1]; + break; + case PP_OD_RESTORE_DEFAULT_TABLE: + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); + if (ret) { + pr_err("Failed to export over drive table!\n"); + return ret; + } + break; case PP_OD_COMMIT_DPM_TABLE: navi10_dump_od_table(od_table); -- 2.24.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table 2020-01-25 18:48 ` [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table Alex Deucher @ 2020-01-28 16:44 ` Matt Coffin 2020-01-28 17:26 ` Alex Deucher 0 siblings, 1 reply; 12+ messages in thread From: Matt Coffin @ 2020-01-28 16:44 UTC (permalink / raw) To: Alex Deucher, amd-gfx; +Cc: Alex Deucher For this, I believe we're updating `table_context->overdrive_table` with the values set by the user, wouldn't the intended behavior here be to restore the settings that were there on boot? If so, I think we'd have to cache the overdrive table that was there on boot, and use that in the response for `PP_OD_RESTORE_DEFAULT_TABLE`, no? I'm doing some testing on this patchset, but on initial lookover that's the only thing I saw. I could be mistaken, but I think this just writes the overdrive table that we are currently using over again instead of writing the default one. On 1/25/20 11:48 AM, Alex Deucher wrote: > Was missing before. > > Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 > Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > index d2d45181ae23..f60762f9b143 100644 > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > @@ -2062,6 +2062,14 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL > if (ret) > return ret; > od_table->UclkFmax = input[1]; > + break; > + case PP_OD_RESTORE_DEFAULT_TABLE: > + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); > + if (ret) { > + pr_err("Failed to export over drive table!\n"); > + return ret; > + } > + > break; > case PP_OD_COMMIT_DPM_TABLE: > navi10_dump_od_table(od_table); > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table 2020-01-28 16:44 ` Matt Coffin @ 2020-01-28 17:26 ` Alex Deucher 2020-01-28 18:48 ` Matt Coffin 0 siblings, 1 reply; 12+ messages in thread From: Alex Deucher @ 2020-01-28 17:26 UTC (permalink / raw) To: Matt Coffin; +Cc: Alex Deucher, amd-gfx list On Tue, Jan 28, 2020 at 11:44 AM Matt Coffin <mcoffin13@gmail.com> wrote: > > For this, I believe we're updating `table_context->overdrive_table` with > the values set by the user, wouldn't the intended behavior here be to > restore the settings that were there on boot? > Correct. > > > If so, I think we'd have to cache the overdrive table that was there on > boot, and use that in the response for `PP_OD_RESTORE_DEFAULT_TABLE`, no? > > > > I'm doing some testing on this patchset, but on initial lookover that's > the only thing I saw. I could be mistaken, but I think this just writes > the overdrive table that we are currently using over again instead of > writing the default one. I just copied that vega20 did. You may be right. I haven't paged the recent SMU interface stuff into my head in a while. If so, we should also fix the vega20_ppt.c code. Thanks! Alex > > On 1/25/20 11:48 AM, Alex Deucher wrote: > > Was missing before. > > > > Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > > --- > > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > > index d2d45181ae23..f60762f9b143 100644 > > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > > @@ -2062,6 +2062,14 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL > > if (ret) > > return ret; > > od_table->UclkFmax = input[1]; > > + break; > > + case PP_OD_RESTORE_DEFAULT_TABLE: > > + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); > > + if (ret) { > > + pr_err("Failed to export over drive table!\n"); > > + return ret; > > + } > > + > > break; > > case PP_OD_COMMIT_DPM_TABLE: > > navi10_dump_od_table(od_table); > > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table 2020-01-28 17:26 ` Alex Deucher @ 2020-01-28 18:48 ` Matt Coffin 2020-01-28 20:06 ` Alex Deucher 2020-01-28 20:10 ` [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables Matt Coffin 0 siblings, 2 replies; 12+ messages in thread From: Matt Coffin @ 2020-01-28 18:48 UTC (permalink / raw) To: Alex Deucher; +Cc: Alex Deucher, amd-gfx list On 1/28/20 10:26 AM, Alex Deucher wrote: > On Tue, Jan 28, 2020 at 11:44 AM Matt Coffin <mcoffin13@gmail.com> wrote: > I just copied that vega20 did. You may be right. I haven't paged the > recent SMU interface stuff into my head in a while. If so, we should > also fix the vega20_ppt.c code. The vega20_ppt code was correct, until we implemented the ability for the user to write to that overdrive table, which will land in 5.5. Not entirely sure about the canonical way to distribute changes to someone else's series, but I can take a crack at fixing this. >> >> On 1/25/20 11:48 AM, Alex Deucher wrote: >>> Was missing before. >>> >>> Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 >>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> >>> --- >>> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c >>> index d2d45181ae23..f60762f9b143 100644 >>> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c >>> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c >>> @@ -2062,6 +2062,14 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL >>> if (ret) >>> return ret; >>> od_table->UclkFmax = input[1]; >>> + break; >>> + case PP_OD_RESTORE_DEFAULT_TABLE: >>> + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); >>> + if (ret) { >>> + pr_err("Failed to export over drive table!\n"); >>> + return ret; >>> + } >>> + >>> break; >>> case PP_OD_COMMIT_DPM_TABLE: >>> navi10_dump_od_table(od_table); >>> _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table 2020-01-28 18:48 ` Matt Coffin @ 2020-01-28 20:06 ` Alex Deucher 2020-01-28 20:10 ` [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables Matt Coffin 1 sibling, 0 replies; 12+ messages in thread From: Alex Deucher @ 2020-01-28 20:06 UTC (permalink / raw) To: Matt Coffin; +Cc: Alex Deucher, amd-gfx list On Tue, Jan 28, 2020 at 1:49 PM Matt Coffin <mcoffin13@gmail.com> wrote: > > > > On 1/28/20 10:26 AM, Alex Deucher wrote: > > On Tue, Jan 28, 2020 at 11:44 AM Matt Coffin <mcoffin13@gmail.com> wrote: > > > I just copied that vega20 did. You may be right. I haven't paged the > > recent SMU interface stuff into my head in a while. If so, we should > > also fix the vega20_ppt.c code. > > The vega20_ppt code was correct, until we implemented the ability for > the user to write to that overdrive table, which will land in 5.5. > > Not entirely sure about the canonical way to distribute changes to > someone else's series, but I can take a crack at fixing this. > Thanks. Just go ahead and send patches. Alex > >> > >> On 1/25/20 11:48 AM, Alex Deucher wrote: > >>> Was missing before. > >>> > >>> Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 > >>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > >>> --- > >>> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 ++++++++ > >>> 1 file changed, 8 insertions(+) > >>> > >>> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > >>> index d2d45181ae23..f60762f9b143 100644 > >>> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > >>> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > >>> @@ -2062,6 +2062,14 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL > >>> if (ret) > >>> return ret; > >>> od_table->UclkFmax = input[1]; > >>> + break; > >>> + case PP_OD_RESTORE_DEFAULT_TABLE: > >>> + ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); > >>> + if (ret) { > >>> + pr_err("Failed to export over drive table!\n"); > >>> + return ret; > >>> + } > >>> + > >>> break; > >>> case PP_OD_COMMIT_DPM_TABLE: > >>> navi10_dump_od_table(od_table); > >>> _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables 2020-01-28 18:48 ` Matt Coffin 2020-01-28 20:06 ` Alex Deucher @ 2020-01-28 20:10 ` Matt Coffin 2020-01-28 22:26 ` Alex Deucher 1 sibling, 1 reply; 12+ messages in thread From: Matt Coffin @ 2020-01-28 20:10 UTC (permalink / raw) To: Alex Deucher; +Cc: Alex Deucher, Matt Coffin, amd-gfx Previously, the syfs functionality for restoring the default powerplay table was sourcing it's information from the currently-staged powerplay table. This patch adds a step to cache the first overdrive table that we see on boot, so that it can be used later to "restore" the powerplay table --- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 9 +++--- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++++ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 28 ++++++------------- 4 files changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index b0591a8dda41..1e33c3e9b98d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -273,6 +273,7 @@ struct smu_table_context uint8_t thermal_controller_type; void *overdrive_table; + void *boot_overdrive_table; }; struct smu_dpm_context { diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index f60762f9b143..26cfccc57331 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -2064,12 +2064,11 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL od_table->UclkFmax = input[1]; break; case PP_OD_RESTORE_DEFAULT_TABLE: - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); - if (ret) { - pr_err("Failed to export over drive table!\n"); - return ret; + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { + pr_err("Overdrive table was not initialized!\n"); + return -EINVAL; } - + memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); break; case PP_OD_COMMIT_DPM_TABLE: navi10_dump_od_table(od_table); diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 02f8c9cb89d9..0dc49479a7eb 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1882,6 +1882,12 @@ int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, pr_err("Failed to export overdrive table!\n"); return ret; } + if (!table_context->boot_overdrive_table) { + table_context->boot_overdrive_table = kmemdup(table_context->overdrive_table, overdrive_table_size, GFP_KERNEL); + if (!table_context->boot_overdrive_table) { + return -ENOMEM; + } + } } ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); if (ret) { diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 38febd5ca4da..4ad8d6c14ee5 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -1706,22 +1706,11 @@ static int vega20_set_default_od_settings(struct smu_context *smu, struct smu_table_context *table_context = &smu->smu_table; int ret; - if (initialize) { - if (table_context->overdrive_table) - return -EINVAL; - - table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL); - - if (!table_context->overdrive_table) - return -ENOMEM; - - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, - table_context->overdrive_table, false); - if (ret) { - pr_err("Failed to export over drive table!\n"); - return ret; - } + ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t)); + if (ret) + return ret; + if (initialize) { ret = vega20_set_default_od8_setttings(smu); if (ret) return ret; @@ -2778,12 +2767,11 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu, break; case PP_OD_RESTORE_DEFAULT_TABLE: - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); - if (ret) { - pr_err("Failed to export over drive table!\n"); - return ret; + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { + pr_err("Overdrive table was not initialized!\n"); + return -EINVAL; } - + memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); break; case PP_OD_COMMIT_DPM_TABLE: -- 2.25.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables 2020-01-28 20:10 ` [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables Matt Coffin @ 2020-01-28 22:26 ` Alex Deucher 2020-01-28 22:37 ` Matt Coffin 0 siblings, 1 reply; 12+ messages in thread From: Alex Deucher @ 2020-01-28 22:26 UTC (permalink / raw) To: Matt Coffin; +Cc: Alex Deucher, amd-gfx list On Tue, Jan 28, 2020 at 3:10 PM Matt Coffin <mcoffin13@gmail.com> wrote: > > Previously, the syfs functionality for restoring the default powerplay > table was sourcing it's information from the currently-staged powerplay > table. > > This patch adds a step to cache the first overdrive table that we see on > boot, so that it can be used later to "restore" the powerplay table Missing your signed-off by. With that fixed, patch is: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 9 +++--- > drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++++ > drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 28 ++++++------------- > 4 files changed, 19 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > index b0591a8dda41..1e33c3e9b98d 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > @@ -273,6 +273,7 @@ struct smu_table_context > uint8_t thermal_controller_type; > > void *overdrive_table; > + void *boot_overdrive_table; > }; > > struct smu_dpm_context { > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > index f60762f9b143..26cfccc57331 100644 > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > @@ -2064,12 +2064,11 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL > od_table->UclkFmax = input[1]; > break; > case PP_OD_RESTORE_DEFAULT_TABLE: > - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); > - if (ret) { > - pr_err("Failed to export over drive table!\n"); > - return ret; > + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { > + pr_err("Overdrive table was not initialized!\n"); > + return -EINVAL; > } > - > + memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); > break; > case PP_OD_COMMIT_DPM_TABLE: > navi10_dump_od_table(od_table); > diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > index 02f8c9cb89d9..0dc49479a7eb 100644 > --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > @@ -1882,6 +1882,12 @@ int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, > pr_err("Failed to export overdrive table!\n"); > return ret; > } > + if (!table_context->boot_overdrive_table) { > + table_context->boot_overdrive_table = kmemdup(table_context->overdrive_table, overdrive_table_size, GFP_KERNEL); > + if (!table_context->boot_overdrive_table) { > + return -ENOMEM; > + } > + } > } > ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); > if (ret) { > diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c > index 38febd5ca4da..4ad8d6c14ee5 100644 > --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c > @@ -1706,22 +1706,11 @@ static int vega20_set_default_od_settings(struct smu_context *smu, > struct smu_table_context *table_context = &smu->smu_table; > int ret; > > - if (initialize) { > - if (table_context->overdrive_table) > - return -EINVAL; > - > - table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL); > - > - if (!table_context->overdrive_table) > - return -ENOMEM; > - > - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, > - table_context->overdrive_table, false); > - if (ret) { > - pr_err("Failed to export over drive table!\n"); > - return ret; > - } > + ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t)); > + if (ret) > + return ret; > > + if (initialize) { > ret = vega20_set_default_od8_setttings(smu); > if (ret) > return ret; > @@ -2778,12 +2767,11 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu, > break; > > case PP_OD_RESTORE_DEFAULT_TABLE: > - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); > - if (ret) { > - pr_err("Failed to export over drive table!\n"); > - return ret; > + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { > + pr_err("Overdrive table was not initialized!\n"); > + return -EINVAL; > } > - > + memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); > break; > > case PP_OD_COMMIT_DPM_TABLE: > -- > 2.25.0 > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables 2020-01-28 22:26 ` Alex Deucher @ 2020-01-28 22:37 ` Matt Coffin 0 siblings, 0 replies; 12+ messages in thread From: Matt Coffin @ 2020-01-28 22:37 UTC (permalink / raw) To: Alex Deucher; +Cc: Alex Deucher, Matt Coffin, amd-gfx Previously, the syfs functionality for restoring the default powerplay table was sourcing it's information from the currently-staged powerplay table. This patch adds a step to cache the first overdrive table that we see on boot, so that it can be used later to "restore" the powerplay table Signed-off-by: Matt Coffin <mcoffin13@gmail.com> --- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 9 +++--- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++++ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 28 ++++++------------- 4 files changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index b0591a8dda41..1e33c3e9b98d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -273,6 +273,7 @@ struct smu_table_context uint8_t thermal_controller_type; void *overdrive_table; + void *boot_overdrive_table; }; struct smu_dpm_context { diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index f60762f9b143..26cfccc57331 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -2064,12 +2064,11 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL od_table->UclkFmax = input[1]; break; case PP_OD_RESTORE_DEFAULT_TABLE: - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); - if (ret) { - pr_err("Failed to export over drive table!\n"); - return ret; + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { + pr_err("Overdrive table was not initialized!\n"); + return -EINVAL; } - + memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); break; case PP_OD_COMMIT_DPM_TABLE: navi10_dump_od_table(od_table); diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 02f8c9cb89d9..0dc49479a7eb 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1882,6 +1882,12 @@ int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, pr_err("Failed to export overdrive table!\n"); return ret; } + if (!table_context->boot_overdrive_table) { + table_context->boot_overdrive_table = kmemdup(table_context->overdrive_table, overdrive_table_size, GFP_KERNEL); + if (!table_context->boot_overdrive_table) { + return -ENOMEM; + } + } } ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true); if (ret) { diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 38febd5ca4da..4ad8d6c14ee5 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -1706,22 +1706,11 @@ static int vega20_set_default_od_settings(struct smu_context *smu, struct smu_table_context *table_context = &smu->smu_table; int ret; - if (initialize) { - if (table_context->overdrive_table) - return -EINVAL; - - table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL); - - if (!table_context->overdrive_table) - return -ENOMEM; - - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, - table_context->overdrive_table, false); - if (ret) { - pr_err("Failed to export over drive table!\n"); - return ret; - } + ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t)); + if (ret) + return ret; + if (initialize) { ret = vega20_set_default_od8_setttings(smu); if (ret) return ret; @@ -2778,12 +2767,11 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu, break; case PP_OD_RESTORE_DEFAULT_TABLE: - ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false); - if (ret) { - pr_err("Failed to export over drive table!\n"); - return ret; + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { + pr_err("Overdrive table was not initialized!\n"); + return -EINVAL; } - + memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); break; case PP_OD_COMMIT_DPM_TABLE: -- 2.25.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK @ 2020-01-29 18:17 Alex Deucher 2020-01-29 18:17 ` [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking Alex Deucher 0 siblings, 1 reply; 12+ messages in thread From: Alex Deucher @ 2020-01-29 18:17 UTC (permalink / raw) To: amd-gfx; +Cc: Alex Deucher You can only adjust the max mclk, not the min. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index f1b27fc20c19..c8f09874c2ec 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -843,7 +843,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) break; size += sprintf(buf + size, "OD_MCLK:\n"); - size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax); + size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax); break; case SMU_OD_VDDC_CURVE: if (!smu->od_enabled || !od_table || !od_settings) -- 2.24.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking 2020-01-29 18:17 [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK Alex Deucher @ 2020-01-29 18:17 ` Alex Deucher 2020-02-03 3:18 ` Quan, Evan 0 siblings, 1 reply; 12+ messages in thread From: Alex Deucher @ 2020-01-29 18:17 UTC (permalink / raw) To: amd-gfx; +Cc: Alex Deucher So users can see the range of valid values. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c8f09874c2ec..d2d45181ae23 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -737,6 +737,15 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl return od_table->cap[feature]; } +static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, + enum SMU_11_0_ODSETTING_ID setting, + uint32_t *min, uint32_t *max) +{ + if (min) + *min = od_table->min[setting]; + if (max) + *max = od_table->max[setting]; +} static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) @@ -755,6 +764,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; struct smu_11_0_overdrive_table *od_settings = smu->od_settings; + uint32_t min_value, max_value; switch (clk_type) { case SMU_GFXCLK: @@ -867,6 +877,55 @@ static int navi10_print_clk_levels(struct smu_context *smu, } size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE); } + break; + case SMU_OD_RANGE: + if (!smu->od_enabled || !od_table || !od_settings) + break; + size = sprintf(buf, "%s:\n", "OD_RANGE"); + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, + &min_value, NULL); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, + NULL, &max_value); + size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", + min_value, max_value); + } + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, + &min_value, &max_value); + size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", + min_value, max_value); + } + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", + min_value, max_value); + } + break; default: break; -- 2.24.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking 2020-01-29 18:17 ` [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking Alex Deucher @ 2020-02-03 3:18 ` Quan, Evan 0 siblings, 0 replies; 12+ messages in thread From: Quan, Evan @ 2020-02-03 3:18 UTC (permalink / raw) To: Alex Deucher, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander Reviewed-by: Evan Quan <evan.quan@amd.com> -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher Sent: Thursday, January 30, 2020 2:18 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander <Alexander.Deucher@amd.com> Subject: [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking So users can see the range of valid values. Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2Fissues%2F1020&data=02%7C01%7Cevan.quan%40amd.com%7C0e007c1c61d74ee6f6fb08d7a4e79680%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637159186942374776&sdata=5NRVbhuOdaAqKBZorF5%2F33np%2F8aoNa5LZsmMCyrazJY%3D&reserved=0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c8f09874c2ec..d2d45181ae23 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -737,6 +737,15 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl return od_table->cap[feature]; } +static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, + enum SMU_11_0_ODSETTING_ID setting, + uint32_t *min, uint32_t *max) +{ + if (min) + *min = od_table->min[setting]; + if (max) + *max = od_table->max[setting]; +} static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) @@ -755,6 +764,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; struct smu_11_0_overdrive_table *od_settings = smu->od_settings; + uint32_t min_value, max_value; switch (clk_type) { case SMU_GFXCLK: @@ -867,6 +877,55 @@ static int navi10_print_clk_levels(struct smu_context *smu, } size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE); } + break; + case SMU_OD_RANGE: + if (!smu->od_enabled || !od_table || !od_settings) + break; + size = sprintf(buf, "%s:\n", "OD_RANGE"); + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, + &min_value, NULL); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, + NULL, &max_value); + size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", + min_value, max_value); + } + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, + &min_value, &max_value); + size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", + min_value, max_value); + } + + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) { + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", + min_value, max_value); + navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, + &min_value, &max_value); + size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", + min_value, max_value); + } + break; default: break; -- 2.24.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cevan.quan%40amd.com%7C0e007c1c61d74ee6f6fb08d7a4e79680%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637159186942374776&sdata=pkI2xsrGq0EJNMaWU5r53%2Fv2CJ4p1ngxeaqHulbeoFo%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-02-03 3:18 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-01-25 18:48 [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK Alex Deucher 2020-01-25 18:48 ` [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking Alex Deucher 2020-01-25 18:48 ` [PATCH 3/3] drm/amdgpu/navi10: add OD support for restoring default table Alex Deucher 2020-01-28 16:44 ` Matt Coffin 2020-01-28 17:26 ` Alex Deucher 2020-01-28 18:48 ` Matt Coffin 2020-01-28 20:06 ` Alex Deucher 2020-01-28 20:10 ` [PATCH] drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables Matt Coffin 2020-01-28 22:26 ` Alex Deucher 2020-01-28 22:37 ` Matt Coffin -- strict thread matches above, loose matches on Subject: below -- 2020-01-29 18:17 [PATCH 1/3] drm/amdgpu/navi: fix index for OD MCLK Alex Deucher 2020-01-29 18:17 ` [PATCH 2/3] drm/amdgpu/navi10: add OD_RANGE for navi overclocking Alex Deucher 2020-02-03 3:18 ` Quan, Evan
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