From: Alex Deucher <alexdeucher@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>,
Likun Gao <Likun.Gao@amd.com>,
Hawking Zhang <Hawking.Zhang@amd.com>
Subject: [PATCH 013/207] drm/amdgpu: initialize IP offset for sienna_cichlid (v2)
Date: Mon, 1 Jun 2020 13:59:25 -0400 [thread overview]
Message-ID: <20200601180239.1267430-10-alexander.deucher@amd.com> (raw)
In-Reply-To: <20200601180239.1267430-1-alexander.deucher@amd.com>
From: Likun Gao <Likun.Gao@amd.com>
Add IP offset headers and state.
V2: squash in updates (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 3 +
drivers/gpu/drm/amd/amdgpu/nv.h | 1 +
.../drm/amd/amdgpu/sienna_cichlid_reg_init.c | 54 +
.../amd/include/sienna_cichlid_ip_offset.h | 1168 +++++++++++++++++
5 files changed, 1227 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
create mode 100644 drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 210d57a4afc8..0fdcb71a4feb 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -68,7 +68,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 642d18e70860..9466dc52df53 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -407,6 +407,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
case CHIP_NAVI12:
navi12_reg_base_init(adev);
break;
+ case CHIP_SIENNA_CICHLID:
+ sienna_cichlid_reg_base_init(adev);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index 82e6cb432f3d..b6a95f0122fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -32,4 +32,5 @@ int nv_set_ip_blocks(struct amdgpu_device *adev);
int navi10_reg_base_init(struct amdgpu_device *adev);
int navi14_reg_base_init(struct amdgpu_device *adev);
int navi12_reg_base_init(struct amdgpu_device *adev);
+int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
new file mode 100644
index 000000000000..5ee69f70c49b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "sienna_cichlid_ip_offset.h"
+
+int sienna_cichlid_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke needed by driver */
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h b/drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
new file mode 100644
index 000000000000..06800c6fa049
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
@@ -0,0 +1,1168 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _sienna_cichlid_ip_offset_HEADER
+#define _sienna_cichlid_ip_offset_HEADER
+
+#define MAX_INSTANCE 7
+#define MAX_SEGMENT 5
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
+ { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
+ { { 0x00017000, 0x02402000, 0, 0, 0 } },
+ { { 0x00017200, 0x02402400, 0, 0, 0 } },
+ { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
+ { { 0x0001B200, 0x0242DC00, 0, 0, 0 } },
+ { { 0x0001B400, 0x0242E000, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } },
+ { { 0x00054000, 0x02425C00, 0, 0, 0 } },
+ { { 0x00094000, 0x02426000, 0, 0, 0 } },
+ { { 0x000D4000, 0x02426400, 0, 0, 0 } },
+ { { 0x00114000, 0x02426800, 0, 0, 0 } },
+ { { 0x00154000, 0x02426C00, 0, 0, 0 } },
+ { { 0x00194000, 0x02427000, 0, 0, 0 } } } };
+static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
+ { { 0x00007B00, 0x00012000, 0x02445000, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C00
+#define ATHUB_BASE__INST0_SEG1 0x02408C00
+#define ATHUB_BASE__INST0_SEG2 0
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+
+#define ATHUB_BASE__INST5_SEG0 0
+#define ATHUB_BASE__INST5_SEG1 0
+#define ATHUB_BASE__INST5_SEG2 0
+#define ATHUB_BASE__INST5_SEG3 0
+#define ATHUB_BASE__INST5_SEG4 0
+
+#define ATHUB_BASE__INST6_SEG0 0
+#define ATHUB_BASE__INST6_SEG1 0
+#define ATHUB_BASE__INST6_SEG2 0
+#define ATHUB_BASE__INST6_SEG3 0
+#define ATHUB_BASE__INST6_SEG4 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0x02401800
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0x02401C00
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0x02402000
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0x02402400
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+
+#define CLK_BASE__INST4_SEG0 0x0001B000
+#define CLK_BASE__INST4_SEG1 0x0242D800
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+
+#define CLK_BASE__INST5_SEG0 0x0001B200
+#define CLK_BASE__INST5_SEG1 0x0242DC00
+#define CLK_BASE__INST5_SEG2 0
+#define CLK_BASE__INST5_SEG3 0
+#define CLK_BASE__INST5_SEG4 0
+
+#define CLK_BASE__INST6_SEG0 0x0001B400
+#define CLK_BASE__INST6_SEG1 0x0242E000
+#define CLK_BASE__INST6_SEG2 0
+#define CLK_BASE__INST6_SEG3 0
+#define CLK_BASE__INST6_SEG4 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0x0240B800
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+
+#define DF_BASE__INST5_SEG0 0
+#define DF_BASE__INST5_SEG1 0
+#define DF_BASE__INST5_SEG2 0
+#define DF_BASE__INST5_SEG3 0
+#define DF_BASE__INST5_SEG4 0
+
+#define DF_BASE__INST6_SEG0 0
+#define DF_BASE__INST6_SEG1 0
+#define DF_BASE__INST6_SEG2 0
+#define DF_BASE__INST6_SEG3 0
+#define DF_BASE__INST6_SEG4 0
+
+#define DIO_BASE__INST0_SEG0 0x02404000
+#define DIO_BASE__INST0_SEG1 0
+#define DIO_BASE__INST0_SEG2 0
+#define DIO_BASE__INST0_SEG3 0
+#define DIO_BASE__INST0_SEG4 0
+
+#define DIO_BASE__INST1_SEG0 0
+#define DIO_BASE__INST1_SEG1 0
+#define DIO_BASE__INST1_SEG2 0
+#define DIO_BASE__INST1_SEG3 0
+#define DIO_BASE__INST1_SEG4 0
+
+#define DIO_BASE__INST2_SEG0 0
+#define DIO_BASE__INST2_SEG1 0
+#define DIO_BASE__INST2_SEG2 0
+#define DIO_BASE__INST2_SEG3 0
+#define DIO_BASE__INST2_SEG4 0
+
+#define DIO_BASE__INST3_SEG0 0
+#define DIO_BASE__INST3_SEG1 0
+#define DIO_BASE__INST3_SEG2 0
+#define DIO_BASE__INST3_SEG3 0
+#define DIO_BASE__INST3_SEG4 0
+
+#define DIO_BASE__INST4_SEG0 0
+#define DIO_BASE__INST4_SEG1 0
+#define DIO_BASE__INST4_SEG2 0
+#define DIO_BASE__INST4_SEG3 0
+#define DIO_BASE__INST4_SEG4 0
+
+#define DIO_BASE__INST5_SEG0 0
+#define DIO_BASE__INST5_SEG1 0
+#define DIO_BASE__INST5_SEG2 0
+#define DIO_BASE__INST5_SEG3 0
+#define DIO_BASE__INST5_SEG4 0
+
+#define DIO_BASE__INST6_SEG0 0
+#define DIO_BASE__INST6_SEG1 0
+#define DIO_BASE__INST6_SEG2 0
+#define DIO_BASE__INST6_SEG3 0
+#define DIO_BASE__INST6_SEG4 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0x00009000
+#define DCN_BASE__INST0_SEG4 0x02403C00
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+
+#define DCN_BASE__INST5_SEG0 0
+#define DCN_BASE__INST5_SEG1 0
+#define DCN_BASE__INST5_SEG2 0
+#define DCN_BASE__INST5_SEG3 0
+#define DCN_BASE__INST5_SEG4 0
+
+#define DCN_BASE__INST6_SEG0 0
+#define DCN_BASE__INST6_SEG1 0
+#define DCN_BASE__INST6_SEG2 0
+#define DCN_BASE__INST6_SEG3 0
+#define DCN_BASE__INST6_SEG4 0
+
+#define DPCS_BASE__INST0_SEG0 0x00000012
+#define DPCS_BASE__INST0_SEG1 0x000000C0
+#define DPCS_BASE__INST0_SEG2 0x000034C0
+#define DPCS_BASE__INST0_SEG3 0x00009000
+#define DPCS_BASE__INST0_SEG4 0x02403C00
+
+#define DPCS_BASE__INST1_SEG0 0
+#define DPCS_BASE__INST1_SEG1 0
+#define DPCS_BASE__INST1_SEG2 0
+#define DPCS_BASE__INST1_SEG3 0
+#define DPCS_BASE__INST1_SEG4 0
+
+#define DPCS_BASE__INST2_SEG0 0
+#define DPCS_BASE__INST2_SEG1 0
+#define DPCS_BASE__INST2_SEG2 0
+#define DPCS_BASE__INST2_SEG3 0
+#define DPCS_BASE__INST2_SEG4 0
+
+#define DPCS_BASE__INST3_SEG0 0
+#define DPCS_BASE__INST3_SEG1 0
+#define DPCS_BASE__INST3_SEG2 0
+#define DPCS_BASE__INST3_SEG3 0
+#define DPCS_BASE__INST3_SEG4 0
+
+#define DPCS_BASE__INST4_SEG0 0
+#define DPCS_BASE__INST4_SEG1 0
+#define DPCS_BASE__INST4_SEG2 0
+#define DPCS_BASE__INST4_SEG3 0
+#define DPCS_BASE__INST4_SEG4 0
+
+#define DPCS_BASE__INST5_SEG0 0
+#define DPCS_BASE__INST5_SEG1 0
+#define DPCS_BASE__INST5_SEG2 0
+#define DPCS_BASE__INST5_SEG3 0
+#define DPCS_BASE__INST5_SEG4 0
+
+#define DPCS_BASE__INST6_SEG0 0
+#define DPCS_BASE__INST6_SEG1 0
+#define DPCS_BASE__INST6_SEG2 0
+#define DPCS_BASE__INST6_SEG3 0
+#define DPCS_BASE__INST6_SEG4 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0x02401400
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+
+#define FUSE_BASE__INST5_SEG0 0
+#define FUSE_BASE__INST5_SEG1 0
+#define FUSE_BASE__INST5_SEG2 0
+#define FUSE_BASE__INST5_SEG3 0
+#define FUSE_BASE__INST5_SEG4 0
+
+#define FUSE_BASE__INST6_SEG0 0
+#define FUSE_BASE__INST6_SEG1 0
+#define FUSE_BASE__INST6_SEG2 0
+#define FUSE_BASE__INST6_SEG3 0
+#define FUSE_BASE__INST6_SEG4 0
+
+#define GC_BASE__INST0_SEG0 0x00001260
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0x0001C000
+#define GC_BASE__INST0_SEG3 0x02402C00
+#define GC_BASE__INST0_SEG4 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+
+#define GC_BASE__INST5_SEG0 0
+#define GC_BASE__INST5_SEG1 0
+#define GC_BASE__INST5_SEG2 0
+#define GC_BASE__INST5_SEG3 0
+#define GC_BASE__INST5_SEG4 0
+
+#define GC_BASE__INST6_SEG0 0
+#define GC_BASE__INST6_SEG1 0
+#define GC_BASE__INST6_SEG2 0
+#define GC_BASE__INST6_SEG3 0
+#define GC_BASE__INST6_SEG4 0
+
+#define HDA_BASE__INST0_SEG0 0x004C0000
+#define HDA_BASE__INST0_SEG1 0x02404800
+#define HDA_BASE__INST0_SEG2 0
+#define HDA_BASE__INST0_SEG3 0
+#define HDA_BASE__INST0_SEG4 0
+
+#define HDA_BASE__INST1_SEG0 0
+#define HDA_BASE__INST1_SEG1 0
+#define HDA_BASE__INST1_SEG2 0
+#define HDA_BASE__INST1_SEG3 0
+#define HDA_BASE__INST1_SEG4 0
+
+#define HDA_BASE__INST2_SEG0 0
+#define HDA_BASE__INST2_SEG1 0
+#define HDA_BASE__INST2_SEG2 0
+#define HDA_BASE__INST2_SEG3 0
+#define HDA_BASE__INST2_SEG4 0
+
+#define HDA_BASE__INST3_SEG0 0
+#define HDA_BASE__INST3_SEG1 0
+#define HDA_BASE__INST3_SEG2 0
+#define HDA_BASE__INST3_SEG3 0
+#define HDA_BASE__INST3_SEG4 0
+
+#define HDA_BASE__INST4_SEG0 0
+#define HDA_BASE__INST4_SEG1 0
+#define HDA_BASE__INST4_SEG2 0
+#define HDA_BASE__INST4_SEG3 0
+#define HDA_BASE__INST4_SEG4 0
+
+#define HDA_BASE__INST5_SEG0 0
+#define HDA_BASE__INST5_SEG1 0
+#define HDA_BASE__INST5_SEG2 0
+#define HDA_BASE__INST5_SEG3 0
+#define HDA_BASE__INST5_SEG4 0
+
+#define HDA_BASE__INST6_SEG0 0
+#define HDA_BASE__INST6_SEG1 0
+#define HDA_BASE__INST6_SEG2 0
+#define HDA_BASE__INST6_SEG3 0
+#define HDA_BASE__INST6_SEG4 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0x0240A400
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+
+#define HDP_BASE__INST5_SEG0 0
+#define HDP_BASE__INST5_SEG1 0
+#define HDP_BASE__INST5_SEG2 0
+#define HDP_BASE__INST5_SEG3 0
+#define HDP_BASE__INST5_SEG4 0
+
+#define HDP_BASE__INST6_SEG0 0
+#define HDP_BASE__INST6_SEG1 0
+#define HDP_BASE__INST6_SEG2 0
+#define HDP_BASE__INST6_SEG3 0
+#define HDP_BASE__INST6_SEG4 0
+
+#define MMHUB_BASE__INST0_SEG0 0x0001A000
+#define MMHUB_BASE__INST0_SEG1 0x02408800
+#define MMHUB_BASE__INST0_SEG2 0
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+
+#define MMHUB_BASE__INST5_SEG0 0
+#define MMHUB_BASE__INST5_SEG1 0
+#define MMHUB_BASE__INST5_SEG2 0
+#define MMHUB_BASE__INST5_SEG3 0
+#define MMHUB_BASE__INST5_SEG4 0
+
+#define MMHUB_BASE__INST6_SEG0 0
+#define MMHUB_BASE__INST6_SEG1 0
+#define MMHUB_BASE__INST6_SEG2 0
+#define MMHUB_BASE__INST6_SEG3 0
+#define MMHUB_BASE__INST6_SEG4 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0x00DC0000
+#define MP0_BASE__INST0_SEG2 0x00E00000
+#define MP0_BASE__INST0_SEG3 0x00E40000
+#define MP0_BASE__INST0_SEG4 0x0243FC00
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+
+#define MP0_BASE__INST5_SEG0 0
+#define MP0_BASE__INST5_SEG1 0
+#define MP0_BASE__INST5_SEG2 0
+#define MP0_BASE__INST5_SEG3 0
+#define MP0_BASE__INST5_SEG4 0
+
+#define MP0_BASE__INST6_SEG0 0
+#define MP0_BASE__INST6_SEG1 0
+#define MP0_BASE__INST6_SEG2 0
+#define MP0_BASE__INST6_SEG3 0
+#define MP0_BASE__INST6_SEG4 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0x00DC0000
+#define MP1_BASE__INST0_SEG2 0x00E00000
+#define MP1_BASE__INST0_SEG3 0x00E40000
+#define MP1_BASE__INST0_SEG4 0x0243FC00
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+
+#define MP1_BASE__INST5_SEG0 0
+#define MP1_BASE__INST5_SEG1 0
+#define MP1_BASE__INST5_SEG2 0
+#define MP1_BASE__INST5_SEG3 0
+#define MP1_BASE__INST5_SEG4 0
+
+#define MP1_BASE__INST6_SEG0 0
+#define MP1_BASE__INST6_SEG1 0
+#define MP1_BASE__INST6_SEG2 0
+#define MP1_BASE__INST6_SEG3 0
+#define MP1_BASE__INST6_SEG4 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0x0241B000
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+
+#define NBIO_BASE__INST5_SEG0 0
+#define NBIO_BASE__INST5_SEG1 0
+#define NBIO_BASE__INST5_SEG2 0
+#define NBIO_BASE__INST5_SEG3 0
+#define NBIO_BASE__INST5_SEG4 0
+
+#define NBIO_BASE__INST6_SEG0 0
+#define NBIO_BASE__INST6_SEG1 0
+#define NBIO_BASE__INST6_SEG2 0
+#define NBIO_BASE__INST6_SEG3 0
+#define NBIO_BASE__INST6_SEG4 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0x0240A000
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+
+#define OSSSYS_BASE__INST5_SEG0 0
+#define OSSSYS_BASE__INST5_SEG1 0
+#define OSSSYS_BASE__INST5_SEG2 0
+#define OSSSYS_BASE__INST5_SEG3 0
+#define OSSSYS_BASE__INST5_SEG4 0
+
+#define OSSSYS_BASE__INST6_SEG0 0
+#define OSSSYS_BASE__INST6_SEG1 0
+#define OSSSYS_BASE__INST6_SEG2 0
+#define OSSSYS_BASE__INST6_SEG3 0
+#define OSSSYS_BASE__INST6_SEG4 0
+
+#define PCIE0_BASE__INST0_SEG0 0x00000000
+#define PCIE0_BASE__INST0_SEG1 0x00000014
+#define PCIE0_BASE__INST0_SEG2 0x00000D20
+#define PCIE0_BASE__INST0_SEG3 0x00010400
+#define PCIE0_BASE__INST0_SEG4 0x0241B000
+
+#define PCIE0_BASE__INST1_SEG0 0
+#define PCIE0_BASE__INST1_SEG1 0
+#define PCIE0_BASE__INST1_SEG2 0
+#define PCIE0_BASE__INST1_SEG3 0
+#define PCIE0_BASE__INST1_SEG4 0
+
+#define PCIE0_BASE__INST2_SEG0 0
+#define PCIE0_BASE__INST2_SEG1 0
+#define PCIE0_BASE__INST2_SEG2 0
+#define PCIE0_BASE__INST2_SEG3 0
+#define PCIE0_BASE__INST2_SEG4 0
+
+#define PCIE0_BASE__INST3_SEG0 0
+#define PCIE0_BASE__INST3_SEG1 0
+#define PCIE0_BASE__INST3_SEG2 0
+#define PCIE0_BASE__INST3_SEG3 0
+#define PCIE0_BASE__INST3_SEG4 0
+
+#define PCIE0_BASE__INST4_SEG0 0
+#define PCIE0_BASE__INST4_SEG1 0
+#define PCIE0_BASE__INST4_SEG2 0
+#define PCIE0_BASE__INST4_SEG3 0
+#define PCIE0_BASE__INST4_SEG4 0
+
+#define PCIE0_BASE__INST5_SEG0 0
+#define PCIE0_BASE__INST5_SEG1 0
+#define PCIE0_BASE__INST5_SEG2 0
+#define PCIE0_BASE__INST5_SEG3 0
+#define PCIE0_BASE__INST5_SEG4 0
+
+#define PCIE0_BASE__INST6_SEG0 0
+#define PCIE0_BASE__INST6_SEG1 0
+#define PCIE0_BASE__INST6_SEG2 0
+#define PCIE0_BASE__INST6_SEG3 0
+#define PCIE0_BASE__INST6_SEG4 0
+
+#define SDMA0_BASE__INST0_SEG0 0x00001260
+#define SDMA0_BASE__INST0_SEG1 0x0000A000
+#define SDMA0_BASE__INST0_SEG2 0x0001C000
+#define SDMA0_BASE__INST0_SEG3 0x02402C00
+#define SDMA0_BASE__INST0_SEG4 0
+
+#define SDMA0_BASE__INST1_SEG0 0
+#define SDMA0_BASE__INST1_SEG1 0
+#define SDMA0_BASE__INST1_SEG2 0
+#define SDMA0_BASE__INST1_SEG3 0
+#define SDMA0_BASE__INST1_SEG4 0
+
+#define SDMA0_BASE__INST2_SEG0 0
+#define SDMA0_BASE__INST2_SEG1 0
+#define SDMA0_BASE__INST2_SEG2 0
+#define SDMA0_BASE__INST2_SEG3 0
+#define SDMA0_BASE__INST2_SEG4 0
+
+#define SDMA0_BASE__INST3_SEG0 0
+#define SDMA0_BASE__INST3_SEG1 0
+#define SDMA0_BASE__INST3_SEG2 0
+#define SDMA0_BASE__INST3_SEG3 0
+#define SDMA0_BASE__INST3_SEG4 0
+
+#define SDMA0_BASE__INST4_SEG0 0
+#define SDMA0_BASE__INST4_SEG1 0
+#define SDMA0_BASE__INST4_SEG2 0
+#define SDMA0_BASE__INST4_SEG3 0
+#define SDMA0_BASE__INST4_SEG4 0
+
+#define SDMA0_BASE__INST5_SEG0 0
+#define SDMA0_BASE__INST5_SEG1 0
+#define SDMA0_BASE__INST5_SEG2 0
+#define SDMA0_BASE__INST5_SEG3 0
+#define SDMA0_BASE__INST5_SEG4 0
+
+#define SDMA0_BASE__INST6_SEG0 0
+#define SDMA0_BASE__INST6_SEG1 0
+#define SDMA0_BASE__INST6_SEG2 0
+#define SDMA0_BASE__INST6_SEG3 0
+#define SDMA0_BASE__INST6_SEG4 0
+
+#define SDMA1_BASE__INST0_SEG0 0x00001260
+#define SDMA1_BASE__INST0_SEG1 0x0000A000
+#define SDMA1_BASE__INST0_SEG2 0x0001C000
+#define SDMA1_BASE__INST0_SEG3 0x02402C00
+#define SDMA1_BASE__INST0_SEG4 0
+
+#define SDMA1_BASE__INST1_SEG0 0
+#define SDMA1_BASE__INST1_SEG1 0
+#define SDMA1_BASE__INST1_SEG2 0
+#define SDMA1_BASE__INST1_SEG3 0
+#define SDMA1_BASE__INST1_SEG4 0
+
+#define SDMA1_BASE__INST2_SEG0 0
+#define SDMA1_BASE__INST2_SEG1 0
+#define SDMA1_BASE__INST2_SEG2 0
+#define SDMA1_BASE__INST2_SEG3 0
+#define SDMA1_BASE__INST2_SEG4 0
+
+#define SDMA1_BASE__INST3_SEG0 0
+#define SDMA1_BASE__INST3_SEG1 0
+#define SDMA1_BASE__INST3_SEG2 0
+#define SDMA1_BASE__INST3_SEG3 0
+#define SDMA1_BASE__INST3_SEG4 0
+
+#define SDMA1_BASE__INST4_SEG0 0
+#define SDMA1_BASE__INST4_SEG1 0
+#define SDMA1_BASE__INST4_SEG2 0
+#define SDMA1_BASE__INST4_SEG3 0
+#define SDMA1_BASE__INST4_SEG4 0
+
+#define SDMA1_BASE__INST5_SEG0 0
+#define SDMA1_BASE__INST5_SEG1 0
+#define SDMA1_BASE__INST5_SEG2 0
+#define SDMA1_BASE__INST5_SEG3 0
+#define SDMA1_BASE__INST5_SEG4 0
+
+#define SDMA1_BASE__INST6_SEG0 0
+#define SDMA1_BASE__INST6_SEG1 0
+#define SDMA1_BASE__INST6_SEG2 0
+#define SDMA1_BASE__INST6_SEG3 0
+#define SDMA1_BASE__INST6_SEG4 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0x00016A00
+#define SMUIO_BASE__INST0_SEG2 0x00440000
+#define SMUIO_BASE__INST0_SEG3 0x02401000
+#define SMUIO_BASE__INST0_SEG4 0
+
+#define SMUIO_BASE__INST1_SEG0 0
+#define SMUIO_BASE__INST1_SEG1 0
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+
+#define SMUIO_BASE__INST5_SEG0 0
+#define SMUIO_BASE__INST5_SEG1 0
+#define SMUIO_BASE__INST5_SEG2 0
+#define SMUIO_BASE__INST5_SEG3 0
+#define SMUIO_BASE__INST5_SEG4 0
+
+#define SMUIO_BASE__INST6_SEG0 0
+#define SMUIO_BASE__INST6_SEG1 0
+#define SMUIO_BASE__INST6_SEG2 0
+#define SMUIO_BASE__INST6_SEG3 0
+#define SMUIO_BASE__INST6_SEG4 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0x02400C00
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+
+#define THM_BASE__INST5_SEG0 0
+#define THM_BASE__INST5_SEG1 0
+#define THM_BASE__INST5_SEG2 0
+#define THM_BASE__INST5_SEG3 0
+#define THM_BASE__INST5_SEG4 0
+
+#define THM_BASE__INST6_SEG0 0
+#define THM_BASE__INST6_SEG1 0
+#define THM_BASE__INST6_SEG2 0
+#define THM_BASE__INST6_SEG3 0
+#define THM_BASE__INST6_SEG4 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0x02425800
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+
+#define UMC_BASE__INST1_SEG0 0x00054000
+#define UMC_BASE__INST1_SEG1 0x02425C00
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+
+#define UMC_BASE__INST2_SEG0 0x00094000
+#define UMC_BASE__INST2_SEG1 0x02426000
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+
+#define UMC_BASE__INST3_SEG0 0x000D4000
+#define UMC_BASE__INST3_SEG1 0x02426400
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+
+#define UMC_BASE__INST4_SEG0 0x00114000
+#define UMC_BASE__INST4_SEG1 0x02426800
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+
+#define UMC_BASE__INST5_SEG0 0x00154000
+#define UMC_BASE__INST5_SEG1 0x02426C00
+#define UMC_BASE__INST5_SEG2 0
+#define UMC_BASE__INST5_SEG3 0
+#define UMC_BASE__INST5_SEG4 0
+
+#define UMC_BASE__INST6_SEG0 0x00194000
+#define UMC_BASE__INST6_SEG1 0x02427000
+#define UMC_BASE__INST6_SEG2 0
+#define UMC_BASE__INST6_SEG3 0
+#define UMC_BASE__INST6_SEG4 0
+
+#define USB0_BASE__INST0_SEG0 0x0242A800
+#define USB0_BASE__INST0_SEG1 0x05B00000
+#define USB0_BASE__INST0_SEG2 0
+#define USB0_BASE__INST0_SEG3 0
+#define USB0_BASE__INST0_SEG4 0
+
+#define USB0_BASE__INST1_SEG0 0
+#define USB0_BASE__INST1_SEG1 0
+#define USB0_BASE__INST1_SEG2 0
+#define USB0_BASE__INST1_SEG3 0
+#define USB0_BASE__INST1_SEG4 0
+
+#define USB0_BASE__INST2_SEG0 0
+#define USB0_BASE__INST2_SEG1 0
+#define USB0_BASE__INST2_SEG2 0
+#define USB0_BASE__INST2_SEG3 0
+#define USB0_BASE__INST2_SEG4 0
+
+#define USB0_BASE__INST3_SEG0 0
+#define USB0_BASE__INST3_SEG1 0
+#define USB0_BASE__INST3_SEG2 0
+#define USB0_BASE__INST3_SEG3 0
+#define USB0_BASE__INST3_SEG4 0
+
+#define USB0_BASE__INST4_SEG0 0
+#define USB0_BASE__INST4_SEG1 0
+#define USB0_BASE__INST4_SEG2 0
+#define USB0_BASE__INST4_SEG3 0
+#define USB0_BASE__INST4_SEG4 0
+
+#define USB0_BASE__INST5_SEG0 0
+#define USB0_BASE__INST5_SEG1 0
+#define USB0_BASE__INST5_SEG2 0
+#define USB0_BASE__INST5_SEG3 0
+#define USB0_BASE__INST5_SEG4 0
+
+#define USB0_BASE__INST6_SEG0 0
+#define USB0_BASE__INST6_SEG1 0
+#define USB0_BASE__INST6_SEG2 0
+#define USB0_BASE__INST6_SEG3 0
+#define USB0_BASE__INST6_SEG4 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0x02403000
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+
+#define VCN_BASE__INST1_SEG0 0x00007B00
+#define VCN_BASE__INST1_SEG1 0x00012000
+#define VCN_BASE__INST1_SEG2 0x02445000
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+
+#define VCN_BASE__INST5_SEG0 0
+#define VCN_BASE__INST5_SEG1 0
+#define VCN_BASE__INST5_SEG2 0
+#define VCN_BASE__INST5_SEG3 0
+#define VCN_BASE__INST5_SEG4 0
+
+#define VCN_BASE__INST6_SEG0 0
+#define VCN_BASE__INST6_SEG1 0
+#define VCN_BASE__INST6_SEG2 0
+#define VCN_BASE__INST6_SEG3 0
+#define VCN_BASE__INST6_SEG4 0
+
+#endif
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2020-06-01 18:03 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type Alex Deucher
2020-06-01 17:59 ` [PATCH 006/207] drm/amdgpu: add sienna_cichlid gpu info firmware v2 Alex Deucher
2020-06-01 17:59 ` [PATCH 007/207] drm/amdgpu: set fw load type for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 008/207] drm/amdgpu: set asic family and ip blocks " Alex Deucher
2020-06-01 17:59 ` [PATCH 009/207] drm/amdgpu/gfx10: add support for sienna_cichlid firmware Alex Deucher
2020-06-01 17:59 ` [PATCH 010/207] drm/amdgpu/gmc10: add sienna_cichlid support Alex Deucher
2020-06-01 17:59 ` [PATCH 011/207] drm/amdgpu/gfx10: add clockgating support for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 012/207] drm/amdgpu/soc15: add " Alex Deucher
2020-06-01 17:59 ` Alex Deucher [this message]
2020-06-01 17:59 ` [PATCH 014/207] drm/amdgpu/soc15: add common ip block " Alex Deucher
2020-06-01 17:59 ` [PATCH 015/207] drm/amdgpu: add support on mmhub " Alex Deucher
2020-06-01 17:59 ` [PATCH 016/207] drm/amdgpu: add support gfxhub for sienna_cichlid (v3) Alex Deucher
2020-06-01 17:59 ` [PATCH 017/207] drm/amdgpu: add gmc ip block for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 018/207] drm/amdgpu: add ih " Alex Deucher
2020-06-01 17:59 ` [PATCH 019/207] drm/amdgpu: add gfx ip block for sienna_cichlid (v3) Alex Deucher
2020-06-01 17:59 ` [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 021/207] drm/amdgpu: add sdma ip block for sienna_cichlid (v5) Alex Deucher
2020-06-01 17:59 ` [PATCH 022/207] drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 023/207] drm/amdgpu/gfx10: change register configure " Alex Deucher
2020-06-01 17:59 ` [PATCH 024/207] drm/amdgpu: add virtual display support " Alex Deucher
2020-06-01 17:59 ` [PATCH 025/207] drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 026/207] drm/amd/powerplay: add support to set performance level for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 027/207] drm/amd/powerplay: set SOCCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 028/207] drm/amd/powerplay: set FCLK " Alex Deucher
2020-06-01 17:59 ` [PATCH 029/207] drm/amd/powerplay: enable Ultra Low Voltage " Alex Deucher
2020-06-01 17:59 ` [PATCH 030/207] drm/amd/powerplay: enable Graphics Clock Deep Sleep " Alex Deucher
2020-06-01 17:59 ` [PATCH 031/207] drm/amd/powerplay: enable SOC " Alex Deucher
2020-06-01 17:59 ` [PATCH 032/207] drm/amdgpu/powerplay: set Thermal control " Alex Deucher
2020-06-01 17:59 ` [PATCH 033/207] drm/amdgpu/powerplay: set UCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 034/207] drm/amd/powerplay: make gfx ds can be configure " Alex Deucher
2020-06-01 17:59 ` [PATCH 035/207] drm/amd/powerplay: Enable SOCCLK ULV " Alex Deucher
2020-06-01 17:59 ` [PATCH 036/207] drm/amd/powerplay: enable DCEFCLK DPM and DS " Alex Deucher
2020-06-01 17:59 ` [PATCH 037/207] drm/amd/powerplay: support pcie value set and update " Alex Deucher
2020-06-01 17:59 ` [PATCH 038/207] drm/amd/powerplay: support to print pcie levels " Alex Deucher
2020-06-01 17:59 ` [PATCH 039/207] drm/amd/powerplay: enable LCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 040/207] drm/amd/powerplay: enable GFX SS " Alex Deucher
2020-06-01 17:59 ` [PATCH 041/207] drm/amd/powerplay: enable Fan control " Alex Deucher
2020-06-01 17:59 ` [PATCH 042/207] drm/amd/powerplay: support to get power index " Alex Deucher
2020-06-01 17:59 ` [PATCH 043/207] drm/amd/powerplay: enable PPT and TDC " Alex Deucher
2020-06-01 17:59 ` [PATCH 044/207] drm/amdgpu/powerplay: add smu block " Alex Deucher
2020-06-01 17:59 ` [PATCH 045/207] drm/amdgpu: skip ASD fw load " Alex Deucher
2020-06-01 17:59 ` [PATCH 046/207] drm/amdgpu/psp: add psp support " Alex Deucher
2020-06-01 17:59 ` [PATCH 047/207] drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently Alex Deucher
2020-06-01 18:00 ` [PATCH 048/207] drm/amdgpu: enable psp ip block for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 049/207] drm/amdgpu: update SDMA 5.2 microcode init Alex Deucher
2020-06-01 18:00 ` [PATCH 050/207] drm/amdgpu: Use variable instead of constant for sdma doorbell range Alex Deucher
2020-06-01 18:00 ` [PATCH 051/207] drm/amdgpu: add support for athub v2.1 Alex Deucher
2020-06-01 18:00 ` [PATCH 052/207] drm/amdgpu: add gmc cg support for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 053/207] drm/amdgpu: add psp block load condition " Alex Deucher
2020-06-01 18:00 ` [PATCH 054/207] drm/amdgpu: add 2rd VCN instance doorbell support Alex Deucher
2020-06-01 18:00 ` [PATCH 055/207] drm/amdgpu: assign the doorbell index to mes ring Alex Deucher
2020-06-01 18:00 ` [PATCH 056/207] drm/amdgpu: add the ring type definition of MES Alex Deucher
2020-06-01 18:00 ` [PATCH 057/207] drm/amdgpu: avoid dereferencing a NULL pointer Alex Deucher
2020-06-01 18:00 ` [PATCH 058/207] drm/amdgpu/mes: update some mes definitions Alex Deucher
2020-06-01 18:00 ` [PATCH 059/207] drm/amdgpu/mes10.1: allocate the eop buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 060/207] drm/amdgpu/mes10.1: initialize the software part of mes ring Alex Deucher
2020-06-01 18:00 ` [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific Alex Deucher
2020-06-02 10:00 ` Christian König
2020-06-02 18:59 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 062/207] drm/amdgpu/mes10.1: allocate mqd buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 063/207] drm/amdgpu/mes10.1: initialize the mqd Alex Deucher
2020-06-01 18:00 ` [PATCH 064/207] drm/amdgpu/mes10.1: install mes queue by register programming Alex Deucher
2020-06-01 18:00 ` [PATCH 065/207] drm/amdgpu/mes10.1: install mes queue via kiq Alex Deucher
2020-06-01 18:00 ` [PATCH 066/207] drm/amdgpu/mes10.1: enable the mes ring during initialization Alex Deucher
2020-06-01 18:00 ` [PATCH 067/207] drm/amdgpu/mes10.1: add the mes fw api Alex Deucher
2020-06-01 18:00 ` [PATCH 068/207] drm/amdgpu/mes10.1: add the helper function for mes command submission Alex Deucher
2020-06-01 18:00 ` [PATCH 069/207] drm/amdgpu/mes10.1: implement adding hardware queue Alex Deucher
2020-06-01 18:00 ` [PATCH 070/207] drm/amdgpu/mes10.1: implement removing " Alex Deucher
2020-06-01 18:00 ` [PATCH 071/207] drm/amdgpu/mes10.1: implement querying the scheduler status Alex Deucher
2020-06-01 18:00 ` [PATCH 072/207] drm/amdgpu/mes10.1: implement setting hardware resources Alex Deucher
2020-06-01 18:00 ` [PATCH 073/207] drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support Alex Deucher
2020-06-01 18:00 ` [PATCH 074/207] drm/amdgpu/mes10.1: copy mes fw info into global fw array Alex Deucher
2020-06-01 18:00 ` [PATCH 075/207] drm/amdgpu: upload mes firmware to gpu buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 076/207] drm/amdgpu/psp: convert amdgpu mes ucode type Alex Deucher
2020-06-01 18:00 ` [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring Alex Deucher
2020-06-02 9:30 ` Christian König
2020-06-02 18:51 ` Alex Deucher
2020-06-01 18:00 ` [PATCH 078/207] drm/amdgpu/mes10.1: update mes initialization Alex Deucher
2020-06-01 18:00 ` [PATCH 079/207] drm/amdgpu: add mes block to sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 080/207] drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 081/207] drm/amdgpu/mes: correct register offset for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 082/207] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 083/207] drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) Alex Deucher
2020-06-01 18:00 ` [PATCH 084/207] drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 085/207] drm/amdgpu: add Sienna_Cichlid VCN to the VCN family Alex Deucher
2020-06-01 18:00 ` [PATCH 086/207] drm/amdgpu: enable VCN3.0 for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 087/207] drm/amdgpu: add JPEG3.0 support " Alex Deucher
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200601180239.1267430-10-alexander.deucher@amd.com \
--to=alexdeucher@gmail.com \
--cc=Hawking.Zhang@amd.com \
--cc=Likun.Gao@amd.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox