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From: Alex Deucher <alexdeucher@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>,
	Likun Gao <Likun.Gao@amd.com>,
	Hawking Zhang <Hawking.Zhang@amd.com>
Subject: [PATCH 051/207] drm/amdgpu: add support for athub v2.1
Date: Mon,  1 Jun 2020 14:00:03 -0400	[thread overview]
Message-ID: <20200601180239.1267430-48-alexander.deucher@amd.com> (raw)
In-Reply-To: <20200601180239.1267430-1-alexander.deucher@amd.com>

From: Likun Gao <Likun.Gao@amd.com>

Add athub v2.1 function and support to compile it.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/Makefile     |   3 +-
 drivers/gpu/drm/amd/amdgpu/athub_v2_1.c | 100 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/athub_v2_1.h |  30 +++++++
 3 files changed, 132 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v2_1.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index e78674121dfe..38b6ec10751f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -163,7 +163,8 @@ amdgpu-y += \
 # add ATHUB block
 amdgpu-y += \
 	athub_v1_0.o \
-	athub_v2_0.o
+	athub_v2_0.o \
+	athub_v2_1.o
 
 # add amdkfd interfaces
 amdgpu-y += amdgpu_amdkfd.o
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
new file mode 100644
index 000000000000..0219bd6ce1b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "athub_v2_1.h"
+
+#include "athub/athub_2_1_0_offset.h"
+#include "athub/athub_2_1_0_sh_mask.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+static void
+athub_v2_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+					    bool enable)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+	else
+		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+
+	if (def != data)
+		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+static void
+athub_v2_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+					   bool enable)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
+	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+	else
+		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+
+	if(def != data)
+		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
+			       enum amd_clockgating_state state)
+{
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	switch (adev->asic_type) {
+	case CHIP_SIENNA_CICHLID:
+		athub_v2_1_update_medium_grain_clock_gating(adev,
+				state == AMD_CG_STATE_GATE ? true : false);
+		athub_v2_1_update_medium_grain_light_sleep(adev,
+				state == AMD_CG_STATE_GATE ? true : false);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+	int data;
+
+	/* AMD_CG_SUPPORT_ATHUB_MGCG */
+	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
+
+	/* AMD_CG_SUPPORT_ATHUB_LS */
+	if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_ATHUB_LS;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.h b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.h
new file mode 100644
index 000000000000..5e6824c0f591
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __ATHUB_V2_1_H__
+#define __ATHUB_V2_1_H__
+
+int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
+			       enum amd_clockgating_state state);
+void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+
+#endif
-- 
2.25.4

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  parent reply	other threads:[~2020-06-01 18:04 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-01 17:59 [PATCH 000/207] Add Support for Sienna Cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 005/207] drm/amdgpu: add sienna_cichlid asic type Alex Deucher
2020-06-01 17:59 ` [PATCH 006/207] drm/amdgpu: add sienna_cichlid gpu info firmware v2 Alex Deucher
2020-06-01 17:59 ` [PATCH 007/207] drm/amdgpu: set fw load type for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 008/207] drm/amdgpu: set asic family and ip blocks " Alex Deucher
2020-06-01 17:59 ` [PATCH 009/207] drm/amdgpu/gfx10: add support for sienna_cichlid firmware Alex Deucher
2020-06-01 17:59 ` [PATCH 010/207] drm/amdgpu/gmc10: add sienna_cichlid support Alex Deucher
2020-06-01 17:59 ` [PATCH 011/207] drm/amdgpu/gfx10: add clockgating support for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 012/207] drm/amdgpu/soc15: add " Alex Deucher
2020-06-01 17:59 ` [PATCH 013/207] drm/amdgpu: initialize IP offset for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 014/207] drm/amdgpu/soc15: add common ip block for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 015/207] drm/amdgpu: add support on mmhub " Alex Deucher
2020-06-01 17:59 ` [PATCH 016/207] drm/amdgpu: add support gfxhub for sienna_cichlid (v3) Alex Deucher
2020-06-01 17:59 ` [PATCH 017/207] drm/amdgpu: add gmc ip block for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 018/207] drm/amdgpu: add ih " Alex Deucher
2020-06-01 17:59 ` [PATCH 019/207] drm/amdgpu: add gfx ip block for sienna_cichlid (v3) Alex Deucher
2020-06-01 17:59 ` [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 021/207] drm/amdgpu: add sdma ip block for sienna_cichlid (v5) Alex Deucher
2020-06-01 17:59 ` [PATCH 022/207] drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 023/207] drm/amdgpu/gfx10: change register configure " Alex Deucher
2020-06-01 17:59 ` [PATCH 024/207] drm/amdgpu: add virtual display support " Alex Deucher
2020-06-01 17:59 ` [PATCH 025/207] drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2) Alex Deucher
2020-06-01 17:59 ` [PATCH 026/207] drm/amd/powerplay: add support to set performance level for sienna_cichlid Alex Deucher
2020-06-01 17:59 ` [PATCH 027/207] drm/amd/powerplay: set SOCCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 028/207] drm/amd/powerplay: set FCLK " Alex Deucher
2020-06-01 17:59 ` [PATCH 029/207] drm/amd/powerplay: enable Ultra Low Voltage " Alex Deucher
2020-06-01 17:59 ` [PATCH 030/207] drm/amd/powerplay: enable Graphics Clock Deep Sleep " Alex Deucher
2020-06-01 17:59 ` [PATCH 031/207] drm/amd/powerplay: enable SOC " Alex Deucher
2020-06-01 17:59 ` [PATCH 032/207] drm/amdgpu/powerplay: set Thermal control " Alex Deucher
2020-06-01 17:59 ` [PATCH 033/207] drm/amdgpu/powerplay: set UCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 034/207] drm/amd/powerplay: make gfx ds can be configure " Alex Deucher
2020-06-01 17:59 ` [PATCH 035/207] drm/amd/powerplay: Enable SOCCLK ULV " Alex Deucher
2020-06-01 17:59 ` [PATCH 036/207] drm/amd/powerplay: enable DCEFCLK DPM and DS " Alex Deucher
2020-06-01 17:59 ` [PATCH 037/207] drm/amd/powerplay: support pcie value set and update " Alex Deucher
2020-06-01 17:59 ` [PATCH 038/207] drm/amd/powerplay: support to print pcie levels " Alex Deucher
2020-06-01 17:59 ` [PATCH 039/207] drm/amd/powerplay: enable LCLK DPM " Alex Deucher
2020-06-01 17:59 ` [PATCH 040/207] drm/amd/powerplay: enable GFX SS " Alex Deucher
2020-06-01 17:59 ` [PATCH 041/207] drm/amd/powerplay: enable Fan control " Alex Deucher
2020-06-01 17:59 ` [PATCH 042/207] drm/amd/powerplay: support to get power index " Alex Deucher
2020-06-01 17:59 ` [PATCH 043/207] drm/amd/powerplay: enable PPT and TDC " Alex Deucher
2020-06-01 17:59 ` [PATCH 044/207] drm/amdgpu/powerplay: add smu block " Alex Deucher
2020-06-01 17:59 ` [PATCH 045/207] drm/amdgpu: skip ASD fw load " Alex Deucher
2020-06-01 17:59 ` [PATCH 046/207] drm/amdgpu/psp: add psp support " Alex Deucher
2020-06-01 17:59 ` [PATCH 047/207] drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently Alex Deucher
2020-06-01 18:00 ` [PATCH 048/207] drm/amdgpu: enable psp ip block for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 049/207] drm/amdgpu: update SDMA 5.2 microcode init Alex Deucher
2020-06-01 18:00 ` [PATCH 050/207] drm/amdgpu: Use variable instead of constant for sdma doorbell range Alex Deucher
2020-06-01 18:00 ` Alex Deucher [this message]
2020-06-01 18:00 ` [PATCH 052/207] drm/amdgpu: add gmc cg support for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 053/207] drm/amdgpu: add psp block load condition " Alex Deucher
2020-06-01 18:00 ` [PATCH 054/207] drm/amdgpu: add 2rd VCN instance doorbell support Alex Deucher
2020-06-01 18:00 ` [PATCH 055/207] drm/amdgpu: assign the doorbell index to mes ring Alex Deucher
2020-06-01 18:00 ` [PATCH 056/207] drm/amdgpu: add the ring type definition of MES Alex Deucher
2020-06-01 18:00 ` [PATCH 057/207] drm/amdgpu: avoid dereferencing a NULL pointer Alex Deucher
2020-06-01 18:00 ` [PATCH 058/207] drm/amdgpu/mes: update some mes definitions Alex Deucher
2020-06-01 18:00 ` [PATCH 059/207] drm/amdgpu/mes10.1: allocate the eop buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 060/207] drm/amdgpu/mes10.1: initialize the software part of mes ring Alex Deucher
2020-06-01 18:00 ` [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific Alex Deucher
2020-06-02 10:00   ` Christian König
2020-06-02 18:59     ` Alex Deucher
2020-06-01 18:00 ` [PATCH 062/207] drm/amdgpu/mes10.1: allocate mqd buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 063/207] drm/amdgpu/mes10.1: initialize the mqd Alex Deucher
2020-06-01 18:00 ` [PATCH 064/207] drm/amdgpu/mes10.1: install mes queue by register programming Alex Deucher
2020-06-01 18:00 ` [PATCH 065/207] drm/amdgpu/mes10.1: install mes queue via kiq Alex Deucher
2020-06-01 18:00 ` [PATCH 066/207] drm/amdgpu/mes10.1: enable the mes ring during initialization Alex Deucher
2020-06-01 18:00 ` [PATCH 067/207] drm/amdgpu/mes10.1: add the mes fw api Alex Deucher
2020-06-01 18:00 ` [PATCH 068/207] drm/amdgpu/mes10.1: add the helper function for mes command submission Alex Deucher
2020-06-01 18:00 ` [PATCH 069/207] drm/amdgpu/mes10.1: implement adding hardware queue Alex Deucher
2020-06-01 18:00 ` [PATCH 070/207] drm/amdgpu/mes10.1: implement removing " Alex Deucher
2020-06-01 18:00 ` [PATCH 071/207] drm/amdgpu/mes10.1: implement querying the scheduler status Alex Deucher
2020-06-01 18:00 ` [PATCH 072/207] drm/amdgpu/mes10.1: implement setting hardware resources Alex Deucher
2020-06-01 18:00 ` [PATCH 073/207] drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support Alex Deucher
2020-06-01 18:00 ` [PATCH 074/207] drm/amdgpu/mes10.1: copy mes fw info into global fw array Alex Deucher
2020-06-01 18:00 ` [PATCH 075/207] drm/amdgpu: upload mes firmware to gpu buffer Alex Deucher
2020-06-01 18:00 ` [PATCH 076/207] drm/amdgpu/psp: convert amdgpu mes ucode type Alex Deucher
2020-06-01 18:00 ` [PATCH 077/207] drm/amdgpu: no need to set up GPU scheduler for mes ring Alex Deucher
2020-06-02  9:30   ` Christian König
2020-06-02 18:51     ` Alex Deucher
2020-06-01 18:00 ` [PATCH 078/207] drm/amdgpu/mes10.1: update mes initialization Alex Deucher
2020-06-01 18:00 ` [PATCH 079/207] drm/amdgpu: add mes block to sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 080/207] drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 081/207] drm/amdgpu/mes: correct register offset for sienna_cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 082/207] drm/amdgpu: add VCN3.0 support for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 083/207] drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) Alex Deucher
2020-06-01 18:00 ` [PATCH 084/207] drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 085/207] drm/amdgpu: add Sienna_Cichlid VCN to the VCN family Alex Deucher
2020-06-01 18:00 ` [PATCH 086/207] drm/amdgpu: enable VCN3.0 for Sienna_Cichlid Alex Deucher
2020-06-01 18:00 ` [PATCH 087/207] drm/amdgpu: add JPEG3.0 support " Alex Deucher

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