* [PATCH 1/9] drm/amd/display: Adjust static-ness of resource functions
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Qingqing Zhuo
` (7 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Joshua Aberback, Eryk.Brol, Sunpeng.Li, Harry.Wentland,
Qingqing.Zhuo, Rodrigo.Siqueira, Bhawanpreet.Lakha
From: Joshua Aberback <joshua.aberback@amd.com>
[Why]
Register definitions are asic-specific, so functions that use registers of
a particular asic should be static, to be exposed in asic-specific function
pointer structures.
[How]
- make register-definition-using functions static
- make some functions non-static, for future use
- remove duplicate function definition
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 -
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 27 ++++++++++---------
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 3 +++
3 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 2c1959845c29..cdd39ee9761d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -95,7 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create(
struct dc_context *ctx, uint32_t inst);
void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
-void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
void dcn20_cap_soc_clocks(
struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 653a571e366d..de53d26f61d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -871,7 +871,7 @@ void dcn30_dpp_destroy(struct dpp **dpp)
*dpp = NULL;
}
-struct dpp *dcn30_dpp_create(
+static struct dpp *dcn30_dpp_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -889,7 +889,8 @@ struct dpp *dcn30_dpp_create(
kfree(dpp);
return NULL;
}
-struct output_pixel_processor *dcn30_opp_create(
+
+static struct output_pixel_processor *dcn30_opp_create(
struct dc_context *ctx, uint32_t inst)
{
struct dcn20_opp *opp =
@@ -905,7 +906,7 @@ struct output_pixel_processor *dcn30_opp_create(
return &opp->base;
}
-struct dce_aux *dcn30_aux_engine_create(
+static struct dce_aux *dcn30_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -924,6 +925,7 @@ struct dce_aux *dcn30_aux_engine_create(
return &aux_engine->base;
}
+
#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
static const struct dce_i2c_registers i2c_hw_regs[] = {
@@ -943,7 +945,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
};
-struct dce_i2c_hw *dcn30_i2c_hw_create(
+static struct dce_i2c_hw *dcn30_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -958,6 +960,7 @@ struct dce_i2c_hw *dcn30_i2c_hw_create(
return dce_i2c_hw;
}
+
static struct mpc *dcn30_mpc_create(
struct dc_context *ctx,
int num_mpcc,
@@ -1008,7 +1011,7 @@ struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
return &hubbub3->base;
}
-struct timing_generator *dcn30_timing_generator_create(
+static struct timing_generator *dcn30_timing_generator_create(
struct dc_context *ctx,
uint32_t instance)
{
@@ -1042,7 +1045,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_TPS4_CAPABLE = true
};
-struct link_encoder *dcn30_link_encoder_create(
+static struct link_encoder *dcn30_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dcn20_link_encoder *enc20 =
@@ -1063,7 +1066,7 @@ struct link_encoder *dcn30_link_encoder_create(
return &enc20->enc10.base;
}
-struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{
struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
@@ -1311,7 +1314,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
dcn_dccg_destroy(&pool->base.dccg);
}
-struct hubp *dcn30_hubp_create(
+static struct hubp *dcn30_hubp_create(
struct dc_context *ctx,
uint32_t inst)
{
@@ -1330,7 +1333,7 @@ struct hubp *dcn30_hubp_create(
return NULL;
}
-bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{
int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
@@ -1355,7 +1358,7 @@ bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
return true;
}
-bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{
int i;
uint32_t pipe_count = pool->res_cap->num_dwb;
@@ -2292,7 +2295,7 @@ static void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
(dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
}
-static void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
unsigned int i, j;
unsigned int num_states = 0;
@@ -2683,7 +2686,7 @@ static bool dcn30_resource_construct(
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
- goto create_fail;
+ goto create_fail;
/* HW Sequencer and Plane caps */
dcn30_hw_sequencer_construct(dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
index 4b4a4d81c1e3..c9d5f94092a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -79,4 +79,7 @@ enum dc_status dcn30_add_stream_to_ctx(
struct dc *dc,
struct dc_state *new_ctx,
struct dc_stream_state *dc_stream);
+
+void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
+
#endif /* _DCN30_RESOURCE_H_ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 1/9] drm/amd/display: Adjust static-ness of resource functions Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
` (3 more replies)
2020-08-05 17:40 ` [PATCH 3/9] drm/amd/display: Revert regression Qingqing Zhuo
` (6 subsequent siblings)
8 siblings, 4 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Aric Cyr, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, stable, Bhawanpreet.Lakha
From: Aric Cyr <aric.cyr@amd.com>
[Why]
Typo in backlight refactor inctroduced wrong register offset.
[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV
Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
index 70ec691e14d2..99c68ca9c7e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
@@ -49,7 +49,7 @@
#define DCN_PANEL_CNTL_REG_LIST()\
DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
- DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
+ DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
SR(BL_PWM_CNTL), \
SR(BL_PWM_CNTL2), \
SR(BL_PWM_PERIOD_CNTL), \
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN
2020-08-05 17:40 ` [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Qingqing Zhuo
@ 2020-08-09 15:53 ` Sasha Levin
2020-08-13 16:25 ` Sasha Levin
` (2 subsequent siblings)
3 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-09 15:53 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Aric Cyr, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8, v5.7.13, v5.4.56, v4.19.137, v4.14.192, v4.9.232, v4.4.232.
v5.8: Build OK!
v5.7.13: Failed to apply! Possible dependencies:
16012806e697 ("drm/amd/display: Add ABM driver implementation")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9ec420d83341 ("drm/amd/display: code cleanup of dc_link file on func dc_link_construct")
d1ebfdd8d0fc ("drm/amd/display: Unify psr feature flags")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
efc3ec87a937 ("drm/amd/display: Remove unused defines")
fe8db3bcf2e5 ("drm/amd/display: query hdcp capability during link detect")
v5.4.56: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.137: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
a94d5569b232 ("drm/amd: Add DM DMCU support")
b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")
v4.14.192: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
v4.9.232: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN
2020-08-05 17:40 ` [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
@ 2020-08-13 16:25 ` Sasha Levin
2020-08-19 23:57 ` Sasha Levin
2020-08-26 13:54 ` Sasha Levin
3 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-13 16:25 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Aric Cyr, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8, v5.7.14, v5.4.57, v4.19.138, v4.14.193, v4.9.232, v4.4.232.
v5.8: Build OK!
v5.7.14: Failed to apply! Possible dependencies:
16012806e697 ("drm/amd/display: Add ABM driver implementation")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9ec420d83341 ("drm/amd/display: code cleanup of dc_link file on func dc_link_construct")
d1ebfdd8d0fc ("drm/amd/display: Unify psr feature flags")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
efc3ec87a937 ("drm/amd/display: Remove unused defines")
fe8db3bcf2e5 ("drm/amd/display: query hdcp capability during link detect")
v5.4.57: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.138: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
a94d5569b232 ("drm/amd: Add DM DMCU support")
b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")
v4.14.193: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
v4.9.232: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN
2020-08-05 17:40 ` [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
2020-08-13 16:25 ` Sasha Levin
@ 2020-08-19 23:57 ` Sasha Levin
2020-08-26 13:54 ` Sasha Levin
3 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-19 23:57 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Aric Cyr, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.1, v5.7.15, v5.4.58, v4.19.139, v4.14.193, v4.9.232, v4.4.232.
v5.8.1: Build OK!
v5.7.15: Failed to apply! Possible dependencies:
16012806e697 ("drm/amd/display: Add ABM driver implementation")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9ec420d83341 ("drm/amd/display: code cleanup of dc_link file on func dc_link_construct")
d1ebfdd8d0fc ("drm/amd/display: Unify psr feature flags")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
efc3ec87a937 ("drm/amd/display: Remove unused defines")
fe8db3bcf2e5 ("drm/amd/display: query hdcp capability during link detect")
v5.4.58: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.139: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
a94d5569b232 ("drm/amd: Add DM DMCU support")
b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")
v4.14.193: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
v4.9.232: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN
2020-08-05 17:40 ` [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Qingqing Zhuo
` (2 preceding siblings ...)
2020-08-19 23:57 ` Sasha Levin
@ 2020-08-26 13:54 ` Sasha Levin
3 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-26 13:54 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Aric Cyr, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.2, v5.7.16, v5.4.59, v4.19.140, v4.14.193, v4.9.232, v4.4.232.
v5.8.2: Build OK!
v5.7.16: Failed to apply! Possible dependencies:
16012806e697 ("drm/amd/display: Add ABM driver implementation")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9ec420d83341 ("drm/amd/display: code cleanup of dc_link file on func dc_link_construct")
d1ebfdd8d0fc ("drm/amd/display: Unify psr feature flags")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
efc3ec87a937 ("drm/amd/display: Remove unused defines")
fe8db3bcf2e5 ("drm/amd/display: query hdcp capability during link detect")
v5.4.59: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on DMCUB")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.140: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
a87fa9938749 ("drm/amd/display: Build stream update and plane updates in dm")
a94d5569b232 ("drm/amd: Add DM DMCU support")
b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
eb3dc8978596 ("drm/amd/display: Use private obj helpers for dm_atomic_state")
v4.14.193: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
v4.9.232: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4caa72e275c ("drm/amd/display: change from panel to panel cntl")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/9] drm/amd/display: Revert regression
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 1/9] drm/amd/display: Adjust static-ness of resource functions Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 4/9] drm/amd/display: mpcc black color should not be impacted by pixel encoding format Qingqing Zhuo
` (5 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Alvin Lee, Bhawanpreet.Lakha
From: Alvin Lee <alvin.lee2@amd.com>
[Why]
Caused pipe split regression
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 --
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 114 ------------------
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 7 --
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 2 -
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 2 -
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 -
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 -
7 files changed, 141 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ebbb8182228d..5aa3b89471c3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2300,7 +2300,6 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
- bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2331,15 +2330,6 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
- if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
- dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
- dc->hwss.interdependent_update_lock(dc, context, true);
- mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
- dc->hwss.interdependent_update_lock(dc, context, false);
- if (mpcc_disconnected)
- dc->hwss.wait_for_pending_cleared(dc, context);
- }
-
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 73eb4e76a0b1..66180b4332f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1624,120 +1624,6 @@ static void dcn20_program_pipe(
}
}
-bool dcn20_disconnect_pipes(
- struct dc *dc,
- struct dc_state *context)
-{
- int i;
- struct dce_hwseq *hws = dc->hwseq;
- bool mpcc_disconnected = false;
- DC_LOGGER_INIT(dc->ctx->logger);
-
- /* Set pipe update flags and lock pipes */
- for (i = 0; i < dc->res_pool->pipe_count; i++)
- dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
- &context->res_ctx.pipe_ctx[i]);
-
- if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
- /* OTG blank before disabling all front ends */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
- && !context->res_ctx.pipe_ctx[i].top_pipe
- && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
- && context->res_ctx.pipe_ctx[i].stream) {
- hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
- }
- }
-
- /* Disconnect mpcc */
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {
- hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
- DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
- mpcc_disconnected = true;
- }
- }
- }
-
- if (mpcc_disconnected) {
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
- struct dc_plane_state *plane_state = pipe_ctx->plane_state;
- struct hubp *hubp = pipe_ctx->plane_res.hubp;
-
- if (!pipe_ctx || !plane_state || !pipe_ctx->stream)
- continue;
-
- // Only update scaler and viewport here if we lose a pipe split.
- // This is to prevent half the screen from being black when we
- // unlock after disconnecting MPCC.
- if (!(old_pipe && !pipe_ctx->top_pipe &&
- !pipe_ctx->bottom_pipe && old_pipe->bottom_pipe))
- continue;
-
- if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) {
- if (pipe_ctx->update_flags.bits.scaler ||
- plane_state->update_flags.bits.scaling_change ||
- plane_state->update_flags.bits.position_change ||
- plane_state->update_flags.bits.per_pixel_alpha_change ||
- pipe_ctx->stream->update_flags.bits.scaling) {
-
- pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
- ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
- /* scaler configuration */
- pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
- pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
- }
-
- if (pipe_ctx->update_flags.bits.viewport ||
- (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
- (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
- (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
-
- hubp->funcs->mem_program_viewport(
- hubp,
- &pipe_ctx->plane_res.scl_data.viewport,
- &pipe_ctx->plane_res.scl_data.viewport_c);
- }
- }
- }
- }
- return mpcc_disconnected;
-}
-
-void dcn20_wait_for_pending_cleared(struct dc *dc,
- struct dc_state *context)
-{
- struct pipe_ctx *pipe_ctx;
- struct timing_generator *tg;
- int i;
-
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- pipe_ctx = &context->res_ctx.pipe_ctx[i];
- tg = pipe_ctx->stream_res.tg;
-
- /*
- * Only wait for top pipe's tg penindg bit
- * Also skip if pipe is disabled.
- */
- if (pipe_ctx->top_pipe ||
- !pipe_ctx->stream || !pipe_ctx->plane_state ||
- !tg->funcs->is_tg_enabled(tg))
- continue;
-
- /*
- * Wait for VBLANK then VACTIVE to ensure we get VUPDATE.
- * For some reason waiting for OTG_UPDATE_PENDING cleared
- * seems to not trigger the update right away, and if we
- * lock again before VUPDATE then we don't get a separated
- * operation.
- */
- pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
- pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
- }
-}
-
void dcn20_program_front_end_for_ctx(
struct dc *dc,
struct dc_state *context)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 7befd35a2359..83220e34c1a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -131,13 +131,6 @@ void dcn20_dccg_init(struct dce_hwseq *hws);
int dcn20_init_sys_ctx(struct dce_hwseq *hws,
struct dc *dc,
struct dc_phy_addr_space_config *pa_config);
-bool dcn20_disconnect_pipes(
- struct dc *dc,
- struct dc_state *context);
-
-void dcn20_wait_for_pending_cleared(struct dc *dc,
- struct dc_state *context);
-
#ifndef TRIM_FSFT
bool dcn20_optimize_timing_for_fsft(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 55afb70d33e5..3dde6f26de47 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -34,8 +34,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
- .disconnect_pipes = dcn20_disconnect_pipes,
- .wait_for_pending_cleared = dcn20_wait_for_pending_cleared,
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
.update_plane_addr = dcn20_update_plane_addr,
.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 264302b27d4f..b187f71afa65 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -35,8 +35,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
- .disconnect_pipes = dcn20_disconnect_pipes,
- .wait_for_pending_cleared = dcn20_wait_for_pending_cleared,
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
.update_plane_addr = dcn20_update_plane_addr,
.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 845aaf1c816c..9afee7160490 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -35,8 +35,6 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
- .disconnect_pipes = dcn20_disconnect_pipes,
- .wait_for_pending_cleared = dcn20_wait_for_pending_cleared,
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
.update_plane_addr = dcn20_update_plane_addr,
.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..3c986717dcd5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,10 +67,6 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
- bool (*disconnect_pipes)(struct dc *dc,
- struct dc_state *context);
- void (*wait_for_pending_cleared)(struct dc *dc,
- struct dc_state *context);
void (*post_unlock_program_front_end)(struct dc *dc,
struct dc_state *context);
void (*update_plane_addr)(const struct dc *dc,
--
2.17.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 4/9] drm/amd/display: mpcc black color should not be impacted by pixel encoding format
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
` (2 preceding siblings ...)
2020-08-05 17:40 ` [PATCH 3/9] drm/amd/display: Revert regression Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 5/9] drm/amd/display: Fix LFC multiplier changing erratically Qingqing Zhuo
` (4 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Xiaodong Yan, Bhawanpreet.Lakha
From: Xiaodong Yan <Xiaodong.Yan@amd.com>
[Why]
The format in MPCC should be 444
[How]
do not modify the mpcc black color according to pixel encoding format
Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a643927e272b..57cd52789606 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2368,14 +2368,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
&blnd_cfg.black_color);
}
- /*
- * The way 420 is packed, 2 channels carry Y component, 1 channel
- * alternate between Cb and Cr, so both channels need the pixel
- * value for Y
- */
- if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
- blnd_cfg.black_color.color_r_cr = blnd_cfg.black_color.color_g_y;
-
if (per_pixel_alpha)
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
else
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 5/9] drm/amd/display: Fix LFC multiplier changing erratically
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
` (3 preceding siblings ...)
2020-08-05 17:40 ` [PATCH 4/9] drm/amd/display: mpcc black color should not be impacted by pixel encoding format Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 6/9] drm/amd/display: Switch to immediate mode for updating infopackets Qingqing Zhuo
` (3 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Bhawanpreet.Lakha, Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.
2. We do not handle unsigned integer subtraction correctly and it underflows
to a really large value, which causes some logic errors.
[How]
1. Fix logic to calculate 'within range' using last_render_time_in_us
2. Split out delta_from_mid_point_delta_in_us calculation to ensure
we don't underflow and wrap around
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
.../amd/display/modules/freesync/freesync.c | 36 +++++++++++++++----
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 81820f3d6b3b..d988533d4af5 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -324,22 +324,44 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
/* Choose number of frames to insert based on how close it
* can get to the mid point of the variable range.
+ * - Delta for CEIL: delta_from_mid_point_in_us_1
+ * - Delta for FLOOR: delta_from_mid_point_in_us_2
*/
- if ((frame_time_in_us / mid_point_frames_ceil) > in_out_vrr->min_duration_in_us &&
- (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2 ||
- mid_point_frames_floor < 2)) {
+ if ((last_render_time_in_us / mid_point_frames_ceil) < in_out_vrr->min_duration_in_us) {
+ /* Check for out of range.
+ * If using CEIL produces a value that is out of range,
+ * then we are forced to use FLOOR.
+ */
+ frames_to_insert = mid_point_frames_floor;
+ } else if (mid_point_frames_floor < 2) {
+ /* Check if FLOOR would result in non-LFC. In this case
+ * choose to use CEIL
+ */
+ frames_to_insert = mid_point_frames_ceil;
+ } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
+ /* If choosing CEIL results in a frame duration that is
+ * closer to the mid point of the range.
+ * Choose CEIL
+ */
frames_to_insert = mid_point_frames_ceil;
- delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
- delta_from_mid_point_in_us_1;
} else {
+ /* If choosing FLOOR results in a frame duration that is
+ * closer to the mid point of the range.
+ * Choose FLOOR
+ */
frames_to_insert = mid_point_frames_floor;
- delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
- delta_from_mid_point_in_us_2;
}
/* Prefer current frame multiplier when BTR is enabled unless it drifts
* too far from the midpoint
*/
+ if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
+ delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
+ delta_from_mid_point_in_us_1;
+ } else {
+ delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
+ delta_from_mid_point_in_us_2;
+ }
if (in_out_vrr->btr.frames_to_insert != 0 &&
delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 6/9] drm/amd/display: Switch to immediate mode for updating infopackets
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
` (4 preceding siblings ...)
2020-08-05 17:40 ` [PATCH 5/9] drm/amd/display: Fix LFC multiplier changing erratically Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 7/9] drm/amd/display: Disconnect pipe separetely when disable pipe split Qingqing Zhuo
` (2 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Bhawanpreet.Lakha, Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
[Why]
Using FRAME_UPDATE will result in infopacket to be potentially updated
one frame late.
In commit stream scenarios for previously active stream, some stale
infopacket data from previous config might be erroneously sent out on
initial frame after stream is re-enabled.
[How]
Switch to using IMMEDIATE_UPDATE mode
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
.../amd/display/dc/dcn10/dcn10_stream_encoder.c | 16 ++++++++--------
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 14 ++++++++++++++
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 07b2f9399671..842abb4c475b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -121,35 +121,35 @@ void enc1_update_generic_info_packet(
switch (packet_index) {
case 0:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC0_FRAME_UPDATE, 1);
+ AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
break;
case 1:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC1_FRAME_UPDATE, 1);
+ AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
break;
case 2:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC2_FRAME_UPDATE, 1);
+ AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
break;
case 3:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC3_FRAME_UPDATE, 1);
+ AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
break;
case 4:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC4_FRAME_UPDATE, 1);
+ AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
break;
case 5:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC5_FRAME_UPDATE, 1);
+ AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
break;
case 6:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC6_FRAME_UPDATE, 1);
+ AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
break;
case 7:
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
- AFMT_GENERIC7_FRAME_UPDATE, 1);
+ AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index ed385b1477be..30eae7459d50 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -281,7 +281,14 @@ struct dcn10_stream_enc_registers {
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
@@ -345,7 +352,14 @@ struct dcn10_stream_enc_registers {
type AFMT_GENERIC2_FRAME_UPDATE;\
type AFMT_GENERIC3_FRAME_UPDATE;\
type AFMT_GENERIC4_FRAME_UPDATE;\
+ type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
+ type AFMT_GENERIC7_IMMEDIATE_UPDATE;\
type AFMT_GENERIC5_FRAME_UPDATE;\
type AFMT_GENERIC6_FRAME_UPDATE;\
type AFMT_GENERIC7_FRAME_UPDATE;\
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 7/9] drm/amd/display: Disconnect pipe separetely when disable pipe split
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
` (5 preceding siblings ...)
2020-08-05 17:40 ` [PATCH 6/9] drm/amd/display: Switch to immediate mode for updating infopackets Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend Qingqing Zhuo
2020-08-05 17:40 ` [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session Qingqing Zhuo
8 siblings, 0 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, Alvin Lee, Bhawanpreet.Lakha
From: Alvin Lee <alvin.lee2@amd.com>
[Why]
When changing pixel formats for HDR (e.g. ARGB -> FP16)
there are configurations that change from 2 pipes to 1 pipe.
In these cases, it seems that disconnecting MPCC and doing
a surface update at the same time(after unlocking) causes
some registers to be updated slightly faster than others
after unlocking (e.g. if the pixel format is updated to FP16
before the new surface address is programmed, we get
corruption on the screen because the pixel formats aren't
matching). We separate disconnecting MPCC from the rest
of the pipe programming sequence to prevent this.
[How]
Move MPCC disconnect into separate operation than the
rest of the pipe programming.
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 146 ++++++++++++++++++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 6 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 2 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 2 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 2 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +
8 files changed, 174 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5aa3b89471c3..ebbb8182228d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2300,6 +2300,7 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
+ bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2330,6 +2331,15 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
+ if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
+ dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
+ dc->hwss.interdependent_update_lock(dc, context, true);
+ mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
+ dc->hwss.interdependent_update_lock(dc, context, false);
+ if (mpcc_disconnected)
+ dc->hwss.wait_for_pending_cleared(dc, context);
+ }
+
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 57cd52789606..95e9d05f884b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2752,6 +2752,152 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
+bool dcn10_disconnect_pipes(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ bool found_stream = false;
+ int i, j;
+ struct dce_hwseq *hws = dc->hwseq;
+ struct dc_state *old_ctx = dc->current_state;
+ bool mpcc_disconnected = false;
+ struct pipe_ctx *old_pipe;
+ struct pipe_ctx *new_pipe;
+ DC_LOGGER_INIT(dc->ctx->logger);
+
+ /* Set pipe update flags and lock pipes */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ new_pipe = &context->res_ctx.pipe_ctx[i];
+ new_pipe->update_flags.raw = 0;
+
+ if (!old_pipe->plane_state && !new_pipe->plane_state)
+ continue;
+
+ if (old_pipe->plane_state && !new_pipe->plane_state)
+ new_pipe->update_flags.bits.disable = 1;
+
+ /* Check for scl update */
+ if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
+ new_pipe->update_flags.bits.scaler = 1;
+
+ /* Check for vp update */
+ if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
+ || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
+ &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
+ new_pipe->update_flags.bits.viewport = 1;
+
+ }
+
+ if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ /* Disconnect mpcc here only if losing pipe split*/
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable &&
+ old_ctx->res_ctx.pipe_ctx[i].top_pipe) {
+
+ /* Find the top pipe in the new ctx for the bottom pipe that we
+ * want to remove by comparing the streams. If both pipes are being
+ * disabled then do it in the regular pipe programming sequence
+ */
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ if (old_ctx->res_ctx.pipe_ctx[i].top_pipe->stream == context->res_ctx.pipe_ctx[j].stream &&
+ !context->res_ctx.pipe_ctx[j].top_pipe &&
+ !context->res_ctx.pipe_ctx[j].update_flags.bits.disable) {
+ found_stream = true;
+ break;
+ }
+ }
+
+ // Disconnect if the top pipe lost it's pipe split
+ if (found_stream && !context->res_ctx.pipe_ctx[j].bottom_pipe) {
+ hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
+ mpcc_disconnected = true;
+ }
+ }
+ found_stream = false;
+ }
+ }
+
+ if (mpcc_disconnected) {
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+ struct hubp *hubp = pipe_ctx->plane_res.hubp;
+
+ if (!pipe_ctx || !plane_state || !pipe_ctx->stream)
+ continue;
+
+ // Only update scaler and viewport here if we lose a pipe split.
+ // This is to prevent half the screen from being black when we
+ // unlock after disconnecting MPCC.
+ if (!(old_pipe && !pipe_ctx->top_pipe &&
+ !pipe_ctx->bottom_pipe && old_pipe->bottom_pipe))
+ continue;
+
+ if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) {
+ if (pipe_ctx->update_flags.bits.scaler ||
+ plane_state->update_flags.bits.scaling_change ||
+ plane_state->update_flags.bits.position_change ||
+ plane_state->update_flags.bits.per_pixel_alpha_change ||
+ pipe_ctx->stream->update_flags.bits.scaling) {
+
+ pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
+ ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
+ /* scaler configuration */
+ pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
+ pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
+ }
+
+ if (pipe_ctx->update_flags.bits.viewport ||
+ (context == dc->current_state && plane_state->update_flags.bits.position_change) ||
+ (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
+ (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
+
+ hubp->funcs->mem_program_viewport(
+ hubp,
+ &pipe_ctx->plane_res.scl_data.viewport,
+ &pipe_ctx->plane_res.scl_data.viewport_c);
+ }
+ }
+ }
+ }
+ return mpcc_disconnected;
+}
+
+void dcn10_wait_for_pending_cleared(struct dc *dc,
+ struct dc_state *context)
+{
+ struct pipe_ctx *pipe_ctx;
+ struct timing_generator *tg;
+ int i;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ tg = pipe_ctx->stream_res.tg;
+
+ /*
+ * Only wait for top pipe's tg penindg bit
+ * Also skip if pipe is disabled.
+ */
+ if (pipe_ctx->top_pipe ||
+ !pipe_ctx->stream || !pipe_ctx->plane_state ||
+ !tg->funcs->is_tg_enabled(tg))
+ continue;
+
+ /*
+ * Wait for VBLANK then VACTIVE to ensure we get VUPDATE.
+ * For some reason waiting for OTG_UPDATE_PENDING cleared
+ * seems to not trigger the update right away, and if we
+ * lock again before VUPDATE then we don't get a separated
+ * operation.
+ */
+ pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
+ pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+ }
+}
+
void dcn10_apply_ctx_for_surface(
struct dc *dc,
const struct dc_stream_state *stream,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 6d891166da8a..e5691e499023 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -194,6 +194,12 @@ void dcn10_get_surface_visual_confirm_color(
void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
+bool dcn10_disconnect_pipes(
+ struct dc *dc,
+ struct dc_state *context);
+
+void dcn10_wait_for_pending_cleared(struct dc *dc,
+ struct dc_state *context);
void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
void dcn10_verify_allow_pstate_change_high(struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index 5c98b71c1d47..a1d1559bb5d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -34,6 +34,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
+ .disconnect_pipes = dcn10_disconnect_pipes,
+ .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
.update_plane_addr = dcn10_update_plane_addr,
.update_dchub = dcn10_update_dchub,
.update_pending_status = dcn10_update_pending_status,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 3dde6f26de47..966e1790b9bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -34,6 +34,8 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ .disconnect_pipes = dcn10_disconnect_pipes,
+ .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
.update_plane_addr = dcn20_update_plane_addr,
.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index b187f71afa65..2ba880c3943c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -35,6 +35,8 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ .disconnect_pipes = dcn10_disconnect_pipes,
+ .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
.update_plane_addr = dcn20_update_plane_addr,
.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 9afee7160490..19daa456e3bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -35,6 +35,8 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = NULL,
.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ .disconnect_pipes = dcn10_disconnect_pipes,
+ .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
.update_plane_addr = dcn20_update_plane_addr,
.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 3c986717dcd5..64c1be818b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,6 +67,10 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
+ bool (*disconnect_pipes)(struct dc *dc,
+ struct dc_state *context);
+ void (*wait_for_pending_cleared)(struct dc *dc,
+ struct dc_state *context);
void (*post_unlock_program_front_end)(struct dc *dc,
struct dc_state *context);
void (*update_plane_addr)(const struct dc *dc,
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
` (6 preceding siblings ...)
2020-08-05 17:40 ` [PATCH 7/9] drm/amd/display: Disconnect pipe separetely when disable pipe split Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
` (2 more replies)
2020-08-05 17:40 ` [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session Qingqing Zhuo
8 siblings, 3 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Stylon Wang, Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, stable, Bhawanpreet.Lakha
From: Stylon Wang <stylon.wang@amd.com>
[Why]
Resuming from suspend, CEA blocks from EDID are not parsed and no video
modes can support YUV420. When this happens, output bpc cannot go over
8-bit with 4K modes on HDMI.
[How]
In amdgpu_dm_update_connector_after_detect(), drm_add_edid_modes() is
called after drm_connector_update_edid_property() to fully parse EDID
and update display info.
Cc: stable@vger.kernel.org
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 53bf8f60d30c..bfb06c168fba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2202,6 +2202,7 @@ void amdgpu_dm_update_connector_after_detect(
drm_connector_update_edid_property(connector,
aconnector->edid);
+ drm_add_edid_modes(connector, aconnector->edid);
if (aconnector->dc_link->aux_mode)
drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend
2020-08-05 17:40 ` [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend Qingqing Zhuo
@ 2020-08-09 15:53 ` Sasha Levin
2020-08-19 23:56 ` Sasha Levin
2020-08-26 13:54 ` Sasha Levin
2 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-09 15:53 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Stylon Wang, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8, v5.7.13, v5.4.56, v4.19.137, v4.14.192, v4.9.232, v4.4.232.
v5.8: Build OK!
v5.7.13: Build OK!
v5.4.56: Build OK!
v4.19.137: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
dcd5fb82ffb4 ("drm/amd/display: Fix reference counting for struct dc_sink.")
e6142dd51142 ("drm/amd/display: Prevent dpcd reads with passive dongles")
v4.14.192: Failed to apply! Possible dependencies:
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c80 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
v4.9.232: Failed to apply! Possible dependencies:
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend
2020-08-05 17:40 ` [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
@ 2020-08-19 23:56 ` Sasha Levin
2020-08-26 13:54 ` Sasha Levin
2 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-19 23:56 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Stylon Wang, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.1, v5.7.15, v5.4.58, v4.19.139, v4.14.193, v4.9.232, v4.4.232.
v5.8.1: Build OK!
v5.7.15: Build OK!
v5.4.58: Build OK!
v4.19.139: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
dcd5fb82ffb4 ("drm/amd/display: Fix reference counting for struct dc_sink.")
e6142dd51142 ("drm/amd/display: Prevent dpcd reads with passive dongles")
v4.14.193: Failed to apply! Possible dependencies:
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c80 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
v4.9.232: Failed to apply! Possible dependencies:
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend
2020-08-05 17:40 ` [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
2020-08-19 23:56 ` Sasha Levin
@ 2020-08-26 13:54 ` Sasha Levin
2 siblings, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-26 13:54 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Stylon Wang, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.2, v5.7.16, v5.4.59, v4.19.140, v4.14.193, v4.9.232, v4.4.232.
v5.8.2: Build OK!
v5.7.16: Build OK!
v5.4.59: Build OK!
v4.19.140: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting of amdgpu_dm.c comments")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
dcd5fb82ffb4 ("drm/amd/display: Fix reference counting for struct dc_sink.")
e6142dd51142 ("drm/amd/display: Prevent dpcd reads with passive dongles")
v4.14.193: Failed to apply! Possible dependencies:
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
1ed3d2567c80 ("drm/amdgpu: keep the MMU lock until the update ends v4")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
v4.9.232: Failed to apply! Possible dependencies:
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session
2020-08-05 17:40 [PATCH 0/9] DC Patches August 10th, 2020 Qingqing Zhuo
` (7 preceding siblings ...)
2020-08-05 17:40 ` [PATCH 8/9] drm/amd/display: Fix EDID parsing after resume from suspend Qingqing Zhuo
@ 2020-08-05 17:40 ` Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
2020-08-19 23:56 ` Sasha Levin
8 siblings, 2 replies; 19+ messages in thread
From: Qingqing Zhuo @ 2020-08-05 17:40 UTC (permalink / raw)
To: amd-gfx
Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, Qingqing.Zhuo,
Rodrigo.Siqueira, stable, Jaehyun Chung, Bhawanpreet.Lakha
From: Jaehyun Chung <jaehyun.chung@amd.com>
[Why]
Stream disable sequence incorretly destroys HDCP session while stream is
not blanked and while audio is not muted. This sequence causes a flash
of corruption during mode change and an audio click.
[How]
Change sequence to blank stream before destroying HDCP session. Audio will
also be muted by blanking the stream.
Cc: stable@vger.kernel.org
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 4bd6e03a7ef3..117d8aaf2a9b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3286,12 +3286,11 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
core_link_set_avmute(pipe_ctx, true);
}
+ dc->hwss.blank_stream(pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_HDCP)
update_psp_stream_config(pipe_ctx, true);
#endif
- dc->hwss.blank_stream(pipe_ctx);
-
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
deallocate_mst_payload(pipe_ctx);
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session
2020-08-05 17:40 ` [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session Qingqing Zhuo
@ 2020-08-09 15:53 ` Sasha Levin
2020-08-19 23:56 ` Sasha Levin
1 sibling, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-09 15:53 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Jaehyun Chung, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8, v5.7.13, v5.4.56, v4.19.137, v4.14.192, v4.9.232, v4.4.232.
v5.8: Build OK!
v5.7.13: Failed to apply! Possible dependencies:
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
v5.4.56: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
8cc426d79be1 ("drm/amd/display: Program DSC during timing programming")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.137: Failed to apply! Possible dependencies:
11c3ee48bd7c ("drm/amdgpu/display: add support for LVDS (v5)")
1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end")
1e7e86c43f38 ("drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
aa9c4abe466a ("drm/amd/display: Refactor FPGA-specific link setup")
v4.14.192: Failed to apply! Possible dependencies:
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
71021265a6f0 ("drm/amd/display: Clear test pattern when enabling stream")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
v4.9.232: Failed to apply! Possible dependencies:
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
71021265a6f0 ("drm/amd/display: Clear test pattern when enabling stream")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
71021265a6f0 ("drm/amd/display: Clear test pattern when enabling stream")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session
2020-08-05 17:40 ` [PATCH 9/9] drm/amd/display: Blank stream before destroying HDCP session Qingqing Zhuo
2020-08-09 15:53 ` Sasha Levin
@ 2020-08-19 23:56 ` Sasha Levin
1 sibling, 0 replies; 19+ messages in thread
From: Sasha Levin @ 2020-08-19 23:56 UTC (permalink / raw)
To: Sasha Levin, Qingqing Zhuo, Jaehyun Chung, amd-gfx
Cc: Sunpeng.Li, Harry.Wentland, stable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.1, v5.7.15, v5.4.58, v4.19.139, v4.14.193, v4.9.232, v4.4.232.
v5.8.1: Build OK!
v5.7.15: Failed to apply! Possible dependencies:
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
v5.4.58: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
8cc426d79be1 ("drm/amd/display: Program DSC during timing programming")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.139: Failed to apply! Possible dependencies:
11c3ee48bd7c ("drm/amdgpu/display: add support for LVDS (v5)")
1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end")
1e7e86c43f38 ("drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
8c3db1284a01 ("drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
aa9c4abe466a ("drm/amd/display: Refactor FPGA-specific link setup")
v4.14.193: Failed to apply! Possible dependencies:
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
71021265a6f0 ("drm/amd/display: Clear test pattern when enabling stream")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
v4.9.232: Failed to apply! Possible dependencies:
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
71021265a6f0 ("drm/amd/display: Clear test pattern when enabling stream")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after writes")
v4.4.232: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
2f752e914d94 ("drm/amd/display: Remove connect DIG FE to its BE during timing programming")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
4cf7c42739cc ("drm/amd/display: Set/Reset avmute when disable/enable stream")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
71021265a6f0 ("drm/amd/display: Clear test pattern when enabling stream")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread