* [PATCH AUTOSEL 5.4 14/38] drm/amd/powerplay: correct Vega20 cached smu feature state [not found] <20200824163751.606577-1-sashal@kernel.org> @ 2020-08-24 16:37 ` Sasha Levin 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 15/38] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading Sasha Levin ` (3 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Sasha Levin @ 2020-08-24 16:37 UTC (permalink / raw) To: linux-kernel, stable Cc: Alex Deucher, Sasha Levin, Evan Quan, dri-devel, amd-gfx From: Evan Quan <evan.quan@amd.com> [ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ] Correct the cached smu feature state on pp_features sysfs setting. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c index f5915308e643a..08b91c31532ba 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c @@ -981,27 +981,15 @@ static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) { struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - uint64_t features_enabled; - int i; - bool enabled; - int ret = 0; + int i, ret = 0; PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures)) == 0, "[DisableAllSMUFeatures] Failed to disable all smu features!", return ret); - ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); - PP_ASSERT_WITH_CODE(!ret, - "[DisableAllSMUFeatures] Failed to get enabled smc features!", - return ret); - - for (i = 0; i < GNLD_FEATURES_MAX; i++) { - enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? - true : false; - data->smu_features[i].enabled = enabled; - data->smu_features[i].supported = enabled; - } + for (i = 0; i < GNLD_FEATURES_MAX; i++) + data->smu_features[i].enabled = 0; return 0; } @@ -3211,10 +3199,11 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) { - uint64_t features_enabled; - uint64_t features_to_enable; - uint64_t features_to_disable; - int ret = 0; + struct vega20_hwmgr *data = + (struct vega20_hwmgr *)(hwmgr->backend); + uint64_t features_enabled, features_to_enable, features_to_disable; + int i, ret = 0; + bool enabled; if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) return -EINVAL; @@ -3243,6 +3232,17 @@ static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfe return ret; } + /* Update the cached feature enablement state */ + ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); + if (ret) + return ret; + + for (i = 0; i < GNLD_FEATURES_MAX; i++) { + enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? + true : false; + data->smu_features[i].enabled = enabled; + } + return 0; } -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH AUTOSEL 5.4 15/38] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading [not found] <20200824163751.606577-1-sashal@kernel.org> 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 14/38] drm/amd/powerplay: correct Vega20 cached smu feature state Sasha Levin @ 2020-08-24 16:37 ` Sasha Levin 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 16/38] drm/amd/display: Switch to immediate mode for updating infopackets Sasha Levin ` (2 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Sasha Levin @ 2020-08-24 16:37 UTC (permalink / raw) To: linux-kernel, stable Cc: Alex Deucher, Sasha Levin, Evan Quan, dri-devel, amd-gfx From: Evan Quan <evan.quan@amd.com> [ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ] The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to assume the bootup state in SMU based on the dpm status. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c index 08b91c31532ba..947e4fa3c5e68 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c @@ -1640,12 +1640,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) data->uvd_power_gated = true; data->vce_power_gated = true; - - if (data->smu_features[GNLD_DPM_UVD].enabled) - data->uvd_power_gated = false; - - if (data->smu_features[GNLD_DPM_VCE].enabled) - data->vce_power_gated = false; } static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH AUTOSEL 5.4 16/38] drm/amd/display: Switch to immediate mode for updating infopackets [not found] <20200824163751.606577-1-sashal@kernel.org> 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 14/38] drm/amd/powerplay: correct Vega20 cached smu feature state Sasha Levin 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 15/38] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading Sasha Levin @ 2020-08-24 16:37 ` Sasha Levin 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 34/38] drm/amdgpu: disable gfxoff for navy_flounder Sasha Levin 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 35/38] Revert "drm/amdgpu: disable gfxoff for navy_flounder" Sasha Levin 4 siblings, 0 replies; 7+ messages in thread From: Sasha Levin @ 2020-08-24 16:37 UTC (permalink / raw) To: linux-kernel, stable Cc: Sasha Levin, Ashley Thomas, Qingqing Zhuo, amd-gfx, dri-devel, Alex Deucher, Anthony Koo From: Anthony Koo <Anthony.Koo@amd.com> [ Upstream commit abba907c7a20032c2d504fd5afe3af7d440a09d0 ] [Why] Using FRAME_UPDATE will result in infopacket to be potentially updated one frame late. In commit stream scenarios for previously active stream, some stale infopacket data from previous config might be erroneously sent out on initial frame after stream is re-enabled. [How] Switch to using IMMEDIATE_UPDATE mode Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- .../amd/display/dc/dcn10/dcn10_stream_encoder.c | 16 ++++++++-------- .../amd/display/dc/dcn10/dcn10_stream_encoder.h | 14 ++++++++++++++ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 9aa258f3550b6..ddf66046616d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -121,35 +121,35 @@ void enc1_update_generic_info_packet( switch (packet_index) { case 0: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC0_FRAME_UPDATE, 1); + AFMT_GENERIC0_IMMEDIATE_UPDATE, 1); break; case 1: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC1_FRAME_UPDATE, 1); + AFMT_GENERIC1_IMMEDIATE_UPDATE, 1); break; case 2: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC2_FRAME_UPDATE, 1); + AFMT_GENERIC2_IMMEDIATE_UPDATE, 1); break; case 3: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC3_FRAME_UPDATE, 1); + AFMT_GENERIC3_IMMEDIATE_UPDATE, 1); break; case 4: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC4_FRAME_UPDATE, 1); + AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); break; case 5: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC5_FRAME_UPDATE, 1); + AFMT_GENERIC5_IMMEDIATE_UPDATE, 1); break; case 6: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC6_FRAME_UPDATE, 1); + AFMT_GENERIC6_IMMEDIATE_UPDATE, 1); break; case 7: REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC7_FRAME_UPDATE, 1); + AFMT_GENERIC7_IMMEDIATE_UPDATE, 1); break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index a512cbea00d17..b9656614950e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -275,7 +275,14 @@ struct dcn10_stream_enc_registers { SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ @@ -339,7 +346,14 @@ struct dcn10_stream_enc_registers { type AFMT_GENERIC2_FRAME_UPDATE;\ type AFMT_GENERIC3_FRAME_UPDATE;\ type AFMT_GENERIC4_FRAME_UPDATE;\ + type AFMT_GENERIC0_IMMEDIATE_UPDATE;\ + type AFMT_GENERIC1_IMMEDIATE_UPDATE;\ + type AFMT_GENERIC2_IMMEDIATE_UPDATE;\ + type AFMT_GENERIC3_IMMEDIATE_UPDATE;\ type AFMT_GENERIC4_IMMEDIATE_UPDATE;\ + type AFMT_GENERIC5_IMMEDIATE_UPDATE;\ + type AFMT_GENERIC6_IMMEDIATE_UPDATE;\ + type AFMT_GENERIC7_IMMEDIATE_UPDATE;\ type AFMT_GENERIC5_FRAME_UPDATE;\ type AFMT_GENERIC6_FRAME_UPDATE;\ type AFMT_GENERIC7_FRAME_UPDATE;\ -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH AUTOSEL 5.4 34/38] drm/amdgpu: disable gfxoff for navy_flounder [not found] <20200824163751.606577-1-sashal@kernel.org> ` (2 preceding siblings ...) 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 16/38] drm/amd/display: Switch to immediate mode for updating infopackets Sasha Levin @ 2020-08-24 16:37 ` Sasha Levin 2020-08-24 18:25 ` Alex Deucher 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 35/38] Revert "drm/amdgpu: disable gfxoff for navy_flounder" Sasha Levin 4 siblings, 1 reply; 7+ messages in thread From: Sasha Levin @ 2020-08-24 16:37 UTC (permalink / raw) To: linux-kernel, stable Cc: Sasha Levin, Tao Zhou, dri-devel, amd-gfx, Jiansong Chen, Alex Deucher From: Jiansong Chen <Jiansong.Chen@amd.com> [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ] gfxoff is temporarily disabled for navy_flounder, since at present the feature has broken some basic amdgpu test. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 64d96eb0a2337..3a5b4efa7a5e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -617,6 +617,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) case CHIP_NAVI10: adev->pm.pp_feature &= ~PP_GFXOFF_MASK; break; + case CHIP_NAVY_FLOUNDER: + adev->pm.pp_feature &= ~PP_GFXOFF_MASK; + break; default: break; } -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH AUTOSEL 5.4 34/38] drm/amdgpu: disable gfxoff for navy_flounder 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 34/38] drm/amdgpu: disable gfxoff for navy_flounder Sasha Levin @ 2020-08-24 18:25 ` Alex Deucher 0 siblings, 0 replies; 7+ messages in thread From: Alex Deucher @ 2020-08-24 18:25 UTC (permalink / raw) To: Sasha Levin Cc: Tao Zhou, LKML, amd-gfx list, Maling list - DRI developers, Jiansong Chen, Alex Deucher, for 3.8 On Mon, Aug 24, 2020 at 12:38 PM Sasha Levin <sashal@kernel.org> wrote: > > From: Jiansong Chen <Jiansong.Chen@amd.com> > > [ Upstream commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3 ] > > gfxoff is temporarily disabled for navy_flounder, > since at present the feature has broken some basic > amdgpu test. > > Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> > Reviewed-by: Tao Zhou <tao.zhou1@amd.com> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > Signed-off-by: Sasha Levin <sashal@kernel.org> Support for this chip does not exist in 5.4 or any other older trees. Please drop this. Alex > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 64d96eb0a2337..3a5b4efa7a5e6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -617,6 +617,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) > case CHIP_NAVI10: > adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > break; > + case CHIP_NAVY_FLOUNDER: > + adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > + break; > default: > break; > } > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH AUTOSEL 5.4 35/38] Revert "drm/amdgpu: disable gfxoff for navy_flounder" [not found] <20200824163751.606577-1-sashal@kernel.org> ` (3 preceding siblings ...) 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 34/38] drm/amdgpu: disable gfxoff for navy_flounder Sasha Levin @ 2020-08-24 16:37 ` Sasha Levin 2020-08-24 18:25 ` Alex Deucher 4 siblings, 1 reply; 7+ messages in thread From: Sasha Levin @ 2020-08-24 16:37 UTC (permalink / raw) To: linux-kernel, stable Cc: Sasha Levin, Tao Zhou, amd-gfx, dri-devel, Jiansong Chen, Alex Deucher, Kenneth Feng From: Jiansong Chen <Jiansong.Chen@amd.com> [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ] This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3. Newly released sdma fw (51.52) provides a fix for the issue. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 3a5b4efa7a5e6..64d96eb0a2337 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -617,9 +617,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) case CHIP_NAVI10: adev->pm.pp_feature &= ~PP_GFXOFF_MASK; break; - case CHIP_NAVY_FLOUNDER: - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; - break; default: break; } -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH AUTOSEL 5.4 35/38] Revert "drm/amdgpu: disable gfxoff for navy_flounder" 2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 35/38] Revert "drm/amdgpu: disable gfxoff for navy_flounder" Sasha Levin @ 2020-08-24 18:25 ` Alex Deucher 0 siblings, 0 replies; 7+ messages in thread From: Alex Deucher @ 2020-08-24 18:25 UTC (permalink / raw) To: Sasha Levin Cc: Tao Zhou, LKML, amd-gfx list, Maling list - DRI developers, Jiansong Chen, Alex Deucher, for 3.8, Kenneth Feng On Mon, Aug 24, 2020 at 12:38 PM Sasha Levin <sashal@kernel.org> wrote: > > From: Jiansong Chen <Jiansong.Chen@amd.com> > > [ Upstream commit da2446b66b5e2c7f3ab63912c8d999810e35e8b3 ] > > This reverts commit 9c9b17a7d19a8e21db2e378784fff1128b46c9d3. > Newly released sdma fw (51.52) provides a fix for the issue. > > Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> > Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> > Reviewed-by: Tao Zhou <tao.zhou1@amd.com> > Acked-by: Alex Deucher <alexander.deucher@amd.com> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com> > Signed-off-by: Sasha Levin <sashal@kernel.org> Support for this chip does not exist in 5.4 or any other older trees. Please drop this. Alex > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 3a5b4efa7a5e6..64d96eb0a2337 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -617,9 +617,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) > case CHIP_NAVI10: > adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > break; > - case CHIP_NAVY_FLOUNDER: > - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > - break; > default: > break; > } > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
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[not found] <20200824163751.606577-1-sashal@kernel.org>
2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 14/38] drm/amd/powerplay: correct Vega20 cached smu feature state Sasha Levin
2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 15/38] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading Sasha Levin
2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 16/38] drm/amd/display: Switch to immediate mode for updating infopackets Sasha Levin
2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 34/38] drm/amdgpu: disable gfxoff for navy_flounder Sasha Levin
2020-08-24 18:25 ` Alex Deucher
2020-08-24 16:37 ` [PATCH AUTOSEL 5.4 35/38] Revert "drm/amdgpu: disable gfxoff for navy_flounder" Sasha Levin
2020-08-24 18:25 ` Alex Deucher
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