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From: Evan Quan <evan.quan@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com, Evan Quan <evan.quan@amd.com>
Subject: [PATCH 3/9] drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init
Date: Wed,  2 Sep 2020 16:31:28 +0800	[thread overview]
Message-ID: <20200902083134.25569-3-evan.quan@amd.com> (raw)
In-Reply-To: <20200902083134.25569-1-evan.quan@amd.com>

That's where the uclk dpm get enabled and then the
uclk cdr workaround can be applied.

Change-Id: I520ae0fbc1c3be68324377c7d8c6dc4a346d3a57
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h        |  1 -
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c      |  6 ------
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c    | 18 ++++++++++++++----
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h    |  1 -
 4 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 4acc3c4c4737..701a94d4b9f6 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -590,7 +590,6 @@ struct pptable_funcs {
 	int (*mode2_reset)(struct smu_context *smu);
 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
 	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
-	int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
 	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
 	void (*log_thermal_throttling_event)(struct smu_context *smu);
 	size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 8d7c75c51fe5..a9c0c20efddb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -975,12 +975,6 @@ static int smu_smc_hw_setup(struct smu_context *smu)
 		return ret;
 	}
 
-	ret = smu_disable_umc_cdr_12gbps_workaround(smu);
-	if (ret) {
-		dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
-		return ret;
-	}
-
 	/*
 	 * For Navi1X, manually switch it to AC mode as PMFW
 	 * may boot it with DC mode.
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 8180b7f99991..6674f3abd457 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2568,6 +2568,7 @@ static int navi10_post_smu_init(struct smu_context *smu)
 	struct smu_feature *feature = &smu->smu_feature;
 	struct amdgpu_device *adev = smu->adev;
 	uint64_t feature_mask = 0;
+	int ret = 0;
 
 	/* For Naiv1x, enable these features only after DAL initialization */
 	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
@@ -2590,9 +2591,19 @@ static int navi10_post_smu_init(struct smu_context *smu)
 		  (unsigned long *)(&feature_mask),
 		  SMU_FEATURE_MAX);
 
-	return smu_cmn_feature_update_enable_state(smu,
-						   feature_mask,
-						   true);
+	ret = smu_cmn_feature_update_enable_state(smu,
+						  feature_mask,
+						  true);
+	if (ret) {
+		dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
+		return ret;
+	}
+
+	ret = navi10_disable_umc_cdr_12gbps_workaround(smu);
+	if (ret)
+		dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
+
+	return ret;
 }
 
 static const struct pptable_funcs navi10_ppt_funcs = {
@@ -2669,7 +2680,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 	.set_default_od_settings = navi10_set_default_od_settings,
 	.od_edit_dpm_table = navi10_od_edit_dpm_table,
 	.run_btc = navi10_run_btc,
-	.disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
 	.set_power_source = smu_v11_0_set_power_source,
 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index db903889f6a7..521b805c920e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -83,7 +83,6 @@
 #define smu_asic_set_performance_level(smu, level)			smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
 #define smu_dump_pptable(smu)						smu_ppt_funcs(dump_pptable, 0, smu)
 #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)	smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
-#define smu_disable_umc_cdr_12gbps_workaround(smu)			smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu)
 #define smu_set_power_source(smu, power_src)				smu_ppt_funcs(set_power_source, 0, smu, power_src)
 #define smu_i2c_init(smu, control)					smu_ppt_funcs(i2c_init, 0, smu, control)
 #define smu_i2c_fini(smu, control)					smu_ppt_funcs(i2c_fini, 0, smu, control)
-- 
2.28.0

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  parent reply	other threads:[~2020-09-02  8:32 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-02  8:31 [PATCH 1/9] drm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2) Evan Quan
2020-09-02  8:31 ` [PATCH 2/9] drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) Evan Quan
2020-09-02  8:31 ` Evan Quan [this message]
2020-09-02  8:31 ` [PATCH 4/9] drm/amd/pm: revise the umc hybrid cdr workaround Evan Quan
2020-09-02  8:31 ` [PATCH 5/9] drm/amd/pm: allocate a new buffer for pstate dummy reading Evan Quan
2020-09-02  8:31 ` [PATCH 6/9] drm/amd/pm: implement a new umc cdr workaround Evan Quan
2020-09-02  8:31 ` [PATCH 7/9] drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares Evan Quan
2020-09-02  8:31 ` [PATCH 8/9] drm/amd/pm: correct the requirement for umc cdr workaround Evan Quan
2020-09-02  8:31 ` [PATCH 9/9] drm/amd/pm: make namings and comments more readable Evan Quan
2020-09-03 13:41   ` Alex Deucher

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