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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Chiawen Huang <chiawen.huang@amd.com>,
	Aurabindo.Pillai@amd.com, Tony Cheng <Tony.Cheng@amd.com>,
	Bhawanpreet.Lakha@amd.com
Subject: [PATCH 4/9] drm/amd/display: disable stream if pixel clock changed with link active
Date: Fri, 25 Sep 2020 10:54:50 -0400	[thread overview]
Message-ID: <20200925145455.2398170-5-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20200925145455.2398170-1-Rodrigo.Siqueira@amd.com>

From: Chiawen Huang <chiawen.huang@amd.com>

[Why]
Vbios uses preferred timing to turn on edp but OS could use other
timing. If change pixel clock when link active, there is unexpected
garbage on monitor.

[How]
Once pixel clock changed, the driver needs to disable stream.

Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 62 ++++++++++++++++++-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  2 +-
 2 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7e74ddc1c708..9fabe264cdea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -842,6 +842,61 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 	dc_release_state(current_ctx);
 }
 
+static void disable_vbios_mode_if_required(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	unsigned int i;
+
+	/* check if timing_changed, disable stream*/
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_stream_state *stream = NULL;
+		struct dc_link *link = NULL;
+		struct pipe_ctx *pipe = NULL;
+
+		pipe = &context->res_ctx.pipe_ctx[i];
+		stream = pipe->stream;
+		if (stream == NULL)
+			continue;
+
+		if (stream->link->local_sink &&
+			stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+			link = stream->link;
+			break;
+		}
+
+		if (link != NULL) {
+			unsigned int enc_inst, tg_inst = 0;
+			unsigned int pix_clk_100hz;
+
+			enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+			if (enc_inst != ENGINE_ID_UNKNOWN) {
+				for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
+					if (dc->res_pool->stream_enc[i]->id == enc_inst) {
+						tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
+							dc->res_pool->stream_enc[i]);
+						break;
+					}
+				}
+
+				dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
+					dc->res_pool->dp_clock_source,
+					tg_inst, &pix_clk_100hz);
+
+				if (link->link_status.link_active) {
+					uint32_t requested_pix_clk_100hz =
+						pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
+
+					if (pix_clk_100hz != requested_pix_clk_100hz) {
+						core_link_disable_stream(pipe);
+						pipe->stream->dpms_off = false;
+					}
+				}
+			}
+		}
+	}
+}
+
 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 {
 	int i;
@@ -1278,13 +1333,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	for (i = 0; i < context->stream_count; i++)
 		dc_streams[i] =  context->streams[i];
 
-	if (!dcb->funcs->is_accelerated_mode(dcb))
+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+		disable_vbios_mode_if_required(dc, context);
 		dc->hwss.enable_accelerated_mode(dc, context);
+	}
 
-	for (i = 0; i < context->stream_count; i++) {
+	for (i = 0; i < context->stream_count; i++)
 		if (context->streams[i]->apply_seamless_boot_optimization)
 			dc->optimize_seamless_boot_streams++;
-	}
 
 	if (context->stream_count > dc->optimize_seamless_boot_streams ||
 		context->stream_count == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 27a1262a20f6..c73768ed250e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1654,7 +1654,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 		// enable fastboot if backend is enabled on eDP
 		if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
 			/* Set optimization flag on eDP stream*/
-			if (edp_stream) {
+			if (edp_stream && edp_link->link_status.link_active) {
 				edp_stream->apply_edp_fast_boot_optimization = true;
 				can_apply_edp_fast_boot = true;
 			}
-- 
2.28.0

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  parent reply	other threads:[~2020-09-25 14:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-25 14:54 [PATCH 0/9] DC Patches September 25, 2020 Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 1/9] drm/amd/display: Update NV1x SR latency values Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 2/9] drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoder Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 3/9] drm/amd/display: Ensure all debug bits are passed to fw Rodrigo Siqueira
2020-09-25 14:54 ` Rodrigo Siqueira [this message]
2020-09-25 14:54 ` [PATCH 5/9] drm/amd/display: Calc DLG from dummy p-state if full p-state unsupported Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 6/9] drm/amd/display: Add debug param to force dio disable Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes Rodrigo Siqueira
2020-09-25 15:52   ` Michel Dänzer
2020-09-25 17:52     ` Cyr, Aric
2020-09-25 14:54 ` [PATCH 8/9] drm/amd/display: [FW Promotion] Release 0.0.35 Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 9/9] drm/amd/display: disable stream if pixel clock changed with link active Rodrigo Siqueira

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