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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Aric Cyr <Aric.Cyr@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Aurabindo.Pillai@amd.com, Bhawanpreet.Lakha@amd.com
Subject: [PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes
Date: Fri, 25 Sep 2020 10:54:53 -0400	[thread overview]
Message-ID: <20200925145455.2398170-8-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20200925145455.2398170-1-Rodrigo.Siqueira@amd.com>

From: Aric Cyr <aric.cyr@amd.com>

This reverts commit e82d8eae9e81af243256f70bec593baed50b0bdb.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c             | 11 +++++++++--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 12 ++----------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h    |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h    |  2 +-
 4 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dc90d26e2663..76946a7d47ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2384,6 +2384,7 @@ static void commit_planes_for_stream(struct dc *dc,
 		enum surface_update_type update_type,
 		struct dc_state *context)
 {
+	bool mpcc_disconnected = false;
 	int i, j;
 	struct pipe_ctx *top_pipe_to_program = NULL;
 
@@ -2414,8 +2415,14 @@ static void commit_planes_for_stream(struct dc *dc,
 		context_clock_trace(dc, context);
 	}
 
-	if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
-		dc->hwss.disconnect_pipes(dc, context);
+	if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
+		dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
+		dc->hwss.interdependent_update_lock(dc, context, true);
+		mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
+		dc->hwss.interdependent_update_lock(dc, context, false);
+		if (mpcc_disconnected)
+			dc->hwss.wait_for_pending_cleared(dc, context);
+	}
 
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 79fe9571cf5d..d0f3bf953d02 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
 	return NULL;
 }
 
-void dcn10_disconnect_pipes(
+bool dcn10_disconnect_pipes(
 		struct dc *dc,
 		struct dc_state *context)
 {
@@ -2772,10 +2772,6 @@ void dcn10_disconnect_pipes(
 		bool mpcc_disconnected = false;
 		struct pipe_ctx *old_pipe;
 		struct pipe_ctx *new_pipe;
-
-		dc->hwss.wait_for_pending_cleared(dc, context);
-		dc->hwss.interdependent_update_lock(dc, context, true);
-
 		DC_LOGGER_INIT(dc->ctx->logger);
 
 		/* Set pipe update flags and lock pipes */
@@ -2878,11 +2874,7 @@ void dcn10_disconnect_pipes(
 				}
 			}
 		}
-
-		dc->hwss.interdependent_update_lock(dc, context, false);
-
-		if (mpcc_disconnected)
-			dc->hwss.wait_for_pending_cleared(dc, context);
+	return mpcc_disconnected;
 }
 
 void dcn10_wait_for_pending_cleared(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 9a0f7a8a85cd..e5691e499023 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
 void dcn10_get_hdr_visual_confirm_color(
 		struct pipe_ctx *pipe_ctx,
 		struct tg_color *color);
-void dcn10_disconnect_pipes(
+bool dcn10_disconnect_pipes(
 		struct dc *dc,
 		struct dc_state *context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index f48ee24d42f9..64c1be818b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
 			int num_planes, struct dc_state *context);
 	void (*program_front_end_for_ctx)(struct dc *dc,
 			struct dc_state *context);
-	void (*disconnect_pipes)(struct dc *dc,
+	bool (*disconnect_pipes)(struct dc *dc,
 			struct dc_state *context);
 	void (*wait_for_pending_cleared)(struct dc *dc,
 			struct dc_state *context);
-- 
2.28.0

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  parent reply	other threads:[~2020-09-25 14:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-25 14:54 [PATCH 0/9] DC Patches September 25, 2020 Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 1/9] drm/amd/display: Update NV1x SR latency values Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 2/9] drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoder Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 3/9] drm/amd/display: Ensure all debug bits are passed to fw Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 4/9] drm/amd/display: disable stream if pixel clock changed with link active Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 5/9] drm/amd/display: Calc DLG from dummy p-state if full p-state unsupported Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 6/9] drm/amd/display: Add debug param to force dio disable Rodrigo Siqueira
2020-09-25 14:54 ` Rodrigo Siqueira [this message]
2020-09-25 15:52   ` [PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes Michel Dänzer
2020-09-25 17:52     ` Cyr, Aric
2020-09-25 14:54 ` [PATCH 8/9] drm/amd/display: [FW Promotion] Release 0.0.35 Rodrigo Siqueira
2020-09-25 14:54 ` [PATCH 9/9] drm/amd/display: disable stream if pixel clock changed with link active Rodrigo Siqueira

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