From: Alex Deucher <alexdeucher@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>, Huang Rui <ray.huang@amd.com>
Subject: [PATCH 16/45] drm/amdgpu: add gfx support for van gogh (v2)
Date: Fri, 25 Sep 2020 16:10:00 -0400 [thread overview]
Message-ID: <20200925201029.1738724-16-alexander.deucher@amd.com> (raw)
In-Reply-To: <20200925201029.1738724-1-alexander.deucher@amd.com>
From: Huang Rui <ray.huang@amd.com>
Add van gogh checks to gfx10 code.
v2: squash in fixes
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 29 +++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
old mode 100644
new mode 100755
index 17fb2efdadd3..19ab5783214c
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -152,6 +152,13 @@ MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_10_1[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3554,6 +3561,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.cp_fw_write_wait = true;
break;
default:
@@ -3652,6 +3660,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
@@ -4186,6 +4197,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4309,6 +4321,7 @@ static int gfx_v10_0_sw_init(void *handle)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -4564,7 +4577,8 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
/* for ASICs that integrates GFX v10.3
* pa_sc_tile_steering_override should be set to 0 */
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
return 0;
/* init num_sc */
@@ -5801,6 +5815,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -5934,6 +5949,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
break;
default:
@@ -5944,6 +5960,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
(CP_MEC_CNTL__MEC_ME1_HALT_MASK |
CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6038,6 +6055,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -6758,6 +6776,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
return false;
}
break;
+ case CHIP_VANGOGH:
+ return true;
default:
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
@@ -6785,6 +6805,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7079,6 +7100,7 @@ static int gfx_v10_0_soft_reset(void *handle)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
GRBM_SOFT_RESET,
@@ -7178,6 +7200,7 @@ static int gfx_v10_0_early_init(void *handle)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
break;
default:
@@ -7231,6 +7254,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
/* wait for RLC_SAFE_MODE */
@@ -7263,6 +7287,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
break;
default:
@@ -7574,6 +7599,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
gfx_v10_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;
@@ -8676,6 +8702,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
break;
case CHIP_NAVI12:
--
2.25.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2020-09-25 20:11 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
2020-09-25 20:09 ` [PATCH 02/45] drm/amdgpu: add van gogh asic_type enum (v2) Alex Deucher
2020-09-25 20:09 ` [PATCH 03/45] drm/amdgpu: add uapi to define van gogh series Alex Deucher
2020-09-25 20:09 ` [PATCH 04/45] drm/amdgpu: add van gogh support for gpu_info and ip block setting Alex Deucher
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
2020-09-28 20:48 ` Luben Tuikov
2020-09-29 14:57 ` Alex Deucher
2020-09-29 18:59 ` Luben Tuikov
2020-09-29 20:15 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
2020-09-28 20:50 ` Luben Tuikov
2020-09-25 20:09 ` [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) Alex Deucher
2020-09-28 20:52 ` Luben Tuikov
2020-09-29 14:37 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 08/45] drm/amdgpu: add van gogh support for ih block Alex Deucher
2020-09-25 20:09 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
2020-09-28 20:57 ` Luben Tuikov
2020-09-29 15:02 ` Alex Deucher
2020-09-25 20:09 ` [PATCH 10/45] drm/amdgpu: add uapi to define van gogh memory type Alex Deucher
2020-09-25 20:09 ` [PATCH 11/45] drm/amdgpu: update new memory types in atomfirmware header Alex Deucher
2020-09-25 20:09 ` [PATCH 12/45] drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables Alex Deucher
2020-09-25 20:09 ` [PATCH 13/45] drm/amdgpu: get the correct vram type for van gogh Alex Deucher
2020-09-25 20:09 ` [PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3) Alex Deucher
2020-09-25 20:09 ` [PATCH 15/45] drm/amdgpu: set fw load type for van gogh Alex Deucher
2020-09-25 20:10 ` Alex Deucher [this message]
2020-09-28 20:18 ` [PATCH] drm/amdgpu: fix perms of gfx_v10_0.c Luben Tuikov
2020-09-30 18:07 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 17/45] drm/amdgpu: add gfx golden settings for vangogh (v3) Alex Deucher
2020-09-25 20:10 ` [PATCH 18/45] drm/amdgpu/gfx10: add updated register offsets for VGH Alex Deucher
2020-09-25 20:10 ` [PATCH 19/45] drm/amdgpu: add sdma support for van gogh Alex Deucher
2020-09-25 20:10 ` [PATCH 20/45] drm/amdgpu: set ip blocks " Alex Deucher
2020-09-25 20:10 ` [PATCH 21/45] drm/amdkfd: add Van Gogh KFD support Alex Deucher
2020-09-25 20:10 ` [PATCH 22/45] drm/amdgpu: add mmhub v2.3 for vangogh (v4) Alex Deucher
2020-09-25 20:10 ` [PATCH 23/45] drm/amdgpu: enable vcn3.0 for van gogh Alex Deucher
2020-09-25 20:10 ` [PATCH 24/45] drm/amdgpu: add pcie port indirect read and write on nv Alex Deucher
2020-09-25 20:10 ` [PATCH 25/45] drm/amdgpu: add nbio v7.2 for vangogh (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 26/45] drm/amdgpu/powerplay: add new smu messages and feature masks " Alex Deucher
2020-09-25 20:10 ` [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh Alex Deucher
2020-09-28 21:41 ` Luben Tuikov
2020-09-29 14:39 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 28/45] drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 29/45] drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 30/45] drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 31/45] drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 32/45] drm/amd/powerplay: partially enable swsmu for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 33/45] drm/amd/powerplay: add vangogh ppt into swSMU Alex Deucher
2020-09-25 20:10 ` [PATCH 34/45] drm/amdgpu: add smu ip block for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 35/45] drm/amdgpu: add TOC firmware definition Alex Deucher
2020-09-25 20:10 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2) Alex Deucher
2020-09-28 22:26 ` Luben Tuikov
2020-09-29 15:09 ` Alex Deucher
2020-09-29 19:02 ` Luben Tuikov
2020-09-30 1:15 ` gfx timeout and GPU reset while hundreds apps run on AMD GPU wales wang
2020-09-25 20:10 ` [PATCH 37/45] drm/amdgpu: enable psp support for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 38/45] drm/amdgpu: disable gfxoff on vangogh for the moment (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 39/45] drm/amdgpu: IP discovery table is not ready yet for VG Alex Deucher
2020-09-25 20:10 ` [PATCH 40/45] drm/amdgpu/mmhub2.3: print client id string for mmhub Alex Deucher
2020-09-25 20:10 ` [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10 Alex Deucher
2020-09-28 22:48 ` Luben Tuikov
2020-09-29 15:13 ` Alex Deucher
2020-09-25 20:10 ` [PATCH 42/45] drm/amdgpu: enable gfx clock gating and power gating for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 43/45] drm/amd/display: Add dcn3.01 support to DC Alex Deucher
2020-09-25 20:10 ` [PATCH 44/45] drm/amd/display: Add dcn3.01 support to DM Alex Deucher
2020-09-25 20:10 ` [PATCH 45/45] drm/amdgpu: add van gogh pci id Alex Deucher
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200925201029.1738724-16-alexander.deucher@amd.com \
--to=alexdeucher@gmail.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=ray.huang@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox