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From: Alex Deucher <alexdeucher@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>, Huang Rui <ray.huang@amd.com>
Subject: [PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3)
Date: Fri, 25 Sep 2020 16:09:58 -0400	[thread overview]
Message-ID: <20200925201029.1738724-14-alexander.deucher@amd.com> (raw)
In-Reply-To: <20200925201029.1738724-1-alexander.deucher@amd.com>

From: Huang Rui <ray.huang@amd.com>

Add gfx memory controller support for van gogh.

v2: don't use dynamic invalidate eng allocation for van gogh.
v3: squash in other fixes

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 33 ++++++++++++++++++++------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 31359e519d69..fa0a0c8a6b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -677,7 +677,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 	u64 base = 0;
 
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_VANGOGH)
 		base = gfxhub_v2_1_get_fb_location(adev);
 	else
 		base = gfxhub_v2_0_get_fb_location(adev);
@@ -690,7 +691,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 
 	/* base offset of vram pages */
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_VANGOGH)
 		adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);
 	else
 		adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
@@ -726,6 +728,13 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 
+#ifdef CONFIG_X86_64
+	if (adev->flags & AMD_IS_APU) {
+		adev->gmc.aper_base = gfxhub_v2_1_get_mc_fb_offset(adev);
+		adev->gmc.aper_size = adev->gmc.real_vram_size;
+	}
+#endif
+
 	/* In case the PCI BAR is larger than the actual amount of vram */
 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
@@ -739,6 +748,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 		case CHIP_NAVI12:
 		case CHIP_SIENNA_CICHLID:
 		case CHIP_NAVY_FLOUNDER:
+		case CHIP_VANGOGH:
 		default:
 			adev->gmc.gart_size = 512ULL << 20;
 			break;
@@ -778,7 +788,8 @@ static int gmc_v10_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_VANGOGH)
 		gfxhub_v2_1_init(adev);
 	else
 		gfxhub_v2_0_init(adev);
@@ -787,7 +798,10 @@ static int gmc_v10_0_sw_init(void *handle)
 
 	spin_lock_init(&adev->gmc.invalidate_lock);
 
-	if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+	if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
+		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
+		adev->gmc.vram_width = 64;
+	} else if (amdgpu_emu_mode == 1) {
 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
 	} else {
@@ -805,6 +819,7 @@ static int gmc_v10_0_sw_init(void *handle)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
 		adev->num_vmhubs = 2;
 		/*
 		 * To fulfill 4-level page support,
@@ -918,6 +933,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
 		break;
 	default:
 		break;
@@ -945,7 +961,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
 		return r;
 
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_VANGOGH)
 		r = gfxhub_v2_1_gart_enable(adev);
 	else
 		r = gfxhub_v2_0_gart_enable(adev);
@@ -970,7 +987,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
 		false : true;
 
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_VANGOGH)
 		gfxhub_v2_1_set_fault_enable_default(adev, value);
 	else
 		gfxhub_v2_0_set_fault_enable_default(adev, value);
@@ -1015,7 +1033,8 @@ static int gmc_v10_0_hw_init(void *handle)
 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
 {
 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_VANGOGH)
 		gfxhub_v2_1_gart_disable(adev);
 	else
 		gfxhub_v2_0_gart_disable(adev);
-- 
2.25.4

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  parent reply	other threads:[~2020-09-25 20:11 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-25 20:09 [PATCH 00/45] Add support for vangoh Alex Deucher
2020-09-25 20:09 ` [PATCH 02/45] drm/amdgpu: add van gogh asic_type enum (v2) Alex Deucher
2020-09-25 20:09 ` [PATCH 03/45] drm/amdgpu: add uapi to define van gogh series Alex Deucher
2020-09-25 20:09 ` [PATCH 04/45] drm/amdgpu: add van gogh support for gpu_info and ip block setting Alex Deucher
2020-09-25 20:09 ` [PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh Alex Deucher
2020-09-28 20:48   ` Luben Tuikov
2020-09-29 14:57     ` Alex Deucher
2020-09-29 18:59       ` Luben Tuikov
2020-09-29 20:15         ` Alex Deucher
2020-09-25 20:09 ` [PATCH 06/45] drm/amdgpu: add nv common ip block support " Alex Deucher
2020-09-28 20:50   ` Luben Tuikov
2020-09-25 20:09 ` [PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) Alex Deucher
2020-09-28 20:52   ` Luben Tuikov
2020-09-29 14:37     ` Alex Deucher
2020-09-25 20:09 ` [PATCH 08/45] drm/amdgpu: add van gogh support for ih block Alex Deucher
2020-09-25 20:09 ` [PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh Alex Deucher
2020-09-28 20:57   ` Luben Tuikov
2020-09-29 15:02     ` Alex Deucher
2020-09-25 20:09 ` [PATCH 10/45] drm/amdgpu: add uapi to define van gogh memory type Alex Deucher
2020-09-25 20:09 ` [PATCH 11/45] drm/amdgpu: update new memory types in atomfirmware header Alex Deucher
2020-09-25 20:09 ` [PATCH 12/45] drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables Alex Deucher
2020-09-25 20:09 ` [PATCH 13/45] drm/amdgpu: get the correct vram type for van gogh Alex Deucher
2020-09-25 20:09 ` Alex Deucher [this message]
2020-09-25 20:09 ` [PATCH 15/45] drm/amdgpu: set fw load " Alex Deucher
2020-09-25 20:10 ` [PATCH 16/45] drm/amdgpu: add gfx support for van gogh (v2) Alex Deucher
2020-09-28 20:18   ` [PATCH] drm/amdgpu: fix perms of gfx_v10_0.c Luben Tuikov
2020-09-30 18:07     ` Alex Deucher
2020-09-25 20:10 ` [PATCH 17/45] drm/amdgpu: add gfx golden settings for vangogh (v3) Alex Deucher
2020-09-25 20:10 ` [PATCH 18/45] drm/amdgpu/gfx10: add updated register offsets for VGH Alex Deucher
2020-09-25 20:10 ` [PATCH 19/45] drm/amdgpu: add sdma support for van gogh Alex Deucher
2020-09-25 20:10 ` [PATCH 20/45] drm/amdgpu: set ip blocks " Alex Deucher
2020-09-25 20:10 ` [PATCH 21/45] drm/amdkfd: add Van Gogh KFD support Alex Deucher
2020-09-25 20:10 ` [PATCH 22/45] drm/amdgpu: add mmhub v2.3 for vangogh (v4) Alex Deucher
2020-09-25 20:10 ` [PATCH 23/45] drm/amdgpu: enable vcn3.0 for van gogh Alex Deucher
2020-09-25 20:10 ` [PATCH 24/45] drm/amdgpu: add pcie port indirect read and write on nv Alex Deucher
2020-09-25 20:10 ` [PATCH 25/45] drm/amdgpu: add nbio v7.2 for vangogh (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 26/45] drm/amdgpu/powerplay: add new smu messages and feature masks " Alex Deucher
2020-09-25 20:10 ` [PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh Alex Deucher
2020-09-28 21:41   ` Luben Tuikov
2020-09-29 14:39     ` Alex Deucher
2020-09-25 20:10 ` [PATCH 28/45] drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 29/45] drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 30/45] drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 31/45] drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 32/45] drm/amd/powerplay: partially enable swsmu for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 33/45] drm/amd/powerplay: add vangogh ppt into swSMU Alex Deucher
2020-09-25 20:10 ` [PATCH 34/45] drm/amdgpu: add smu ip block for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 35/45] drm/amdgpu: add TOC firmware definition Alex Deucher
2020-09-25 20:10 ` [PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2) Alex Deucher
2020-09-28 22:26   ` Luben Tuikov
2020-09-29 15:09     ` Alex Deucher
2020-09-29 19:02       ` Luben Tuikov
2020-09-30  1:15         ` gfx timeout and GPU reset while hundreds apps run on AMD GPU wales wang
2020-09-25 20:10 ` [PATCH 37/45] drm/amdgpu: enable psp support for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 38/45] drm/amdgpu: disable gfxoff on vangogh for the moment (v2) Alex Deucher
2020-09-25 20:10 ` [PATCH 39/45] drm/amdgpu: IP discovery table is not ready yet for VG Alex Deucher
2020-09-25 20:10 ` [PATCH 40/45] drm/amdgpu/mmhub2.3: print client id string for mmhub Alex Deucher
2020-09-25 20:10 ` [PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10 Alex Deucher
2020-09-28 22:48   ` Luben Tuikov
2020-09-29 15:13     ` Alex Deucher
2020-09-25 20:10 ` [PATCH 42/45] drm/amdgpu: enable gfx clock gating and power gating for vangogh Alex Deucher
2020-09-25 20:10 ` [PATCH 43/45] drm/amd/display: Add dcn3.01 support to DC Alex Deucher
2020-09-25 20:10 ` [PATCH 44/45] drm/amd/display: Add dcn3.01 support to DM Alex Deucher
2020-09-25 20:10 ` [PATCH 45/45] drm/amdgpu: add van gogh pci id Alex Deucher

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