* [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency
@ 2020-10-14 5:20 Evan Quan
2020-10-14 5:20 ` [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state Evan Quan
2020-10-14 13:19 ` [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency Alex Deucher
0 siblings, 2 replies; 6+ messages in thread
From: Evan Quan @ 2020-10-14 5:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
As for other clock domains.
Change-Id: I0a78c133f00cd11133bc755bf0443505088f024c
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index fafa9c57e32f..9fa9473d418f 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -226,6 +226,7 @@ struct smu_bios_boot_up_values
uint32_t format_revision;
uint32_t content_revision;
uint32_t fclk;
+ uint32_t lclk;
};
enum smu_table_id
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index a057d1d15087..fbf6d3e35173 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -603,6 +603,11 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
(uint8_t)SMU11_SYSPLL1_2_ID,
&smu->smu_table.boot_values.fclk);
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
+ (uint8_t)SMU11_SYSPLL3_1_ID,
+ &smu->smu_table.boot_values.lclk);
+
return 0;
}
--
2.28.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
2020-10-14 5:20 [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency Evan Quan
@ 2020-10-14 5:20 ` Evan Quan
2020-10-14 13:18 ` Alex Deucher
2020-10-14 13:19 ` [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency Alex Deucher
1 sibling, 1 reply; 6+ messages in thread
From: Evan Quan @ 2020-10-14 5:20 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Populate current link speed, width and clock domain frequency.
Change-Id: Ic342fbd8f5e2495d212eaa4b85b4e146838e0525
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 18 ++++++++++++++++++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 46eea3f8f958..f87411cfa4da 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2124,9 +2124,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (asic_type < CHIP_VEGA20)
*states = ATTR_STATE_UNSUPPORTED;
- } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
- if (asic_type == CHIP_ARCTURUS)
- *states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
*states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index f982b9090d7b..46d950757230 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -720,6 +720,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
struct smu_11_0_dpm_table *single_dpm_table;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
struct smu_11_0_dpm_context *dpm_context = NULL;
+ uint32_t gen_speed, lane_width;
if (amdgpu_ras_intr_triggered())
return snprintf(buf, PAGE_SIZE, "unavailable\n");
@@ -823,6 +824,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
now) ? "*" : ""));
break;
+ case SMU_PCIE:
+ gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
+ lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
+ size += sprintf(buf + size, "0: %s %s %dMhz *\n",
+ (gen_speed == 0) ? "2.5GT/s," :
+ (gen_speed == 1) ? "5.0GT/s," :
+ (gen_speed == 2) ? "8.0GT/s," :
+ (gen_speed == 3) ? "16.0GT/s," : "",
+ (lane_width == 1) ? "x1" :
+ (lane_width == 2) ? "x2" :
+ (lane_width == 3) ? "x4" :
+ (lane_width == 4) ? "x8" :
+ (lane_width == 5) ? "x12" :
+ (lane_width == 6) ? "x16" : "",
+ smu->smu_table.boot_values.lclk / 100);
+ break;
+
default:
break;
}
--
2.28.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
2020-10-14 5:20 ` [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state Evan Quan
@ 2020-10-14 13:18 ` Alex Deucher
2020-10-15 1:05 ` Quan, Evan
0 siblings, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2020-10-14 13:18 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Wed, Oct 14, 2020 at 1:21 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Populate current link speed, width and clock domain frequency.
>
> Change-Id: Ic342fbd8f5e2495d212eaa4b85b4e146838e0525
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 18 ++++++++++++++++++
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 46eea3f8f958..f87411cfa4da 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2124,9 +2124,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
> } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
> if (asic_type < CHIP_VEGA20)
> *states = ATTR_STATE_UNSUPPORTED;
> - } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
> - if (asic_type == CHIP_ARCTURUS)
> - *states = ATTR_STATE_UNSUPPORTED;
> } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
> *states = ATTR_STATE_UNSUPPORTED;
> if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index f982b9090d7b..46d950757230 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -720,6 +720,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> struct smu_11_0_dpm_table *single_dpm_table;
> struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
> struct smu_11_0_dpm_context *dpm_context = NULL;
> + uint32_t gen_speed, lane_width;
>
> if (amdgpu_ras_intr_triggered())
> return snprintf(buf, PAGE_SIZE, "unavailable\n");
> @@ -823,6 +824,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> now) ? "*" : ""));
> break;
>
> + case SMU_PCIE:
> + gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
> + lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
> + size += sprintf(buf + size, "0: %s %s %dMhz *\n",
> + (gen_speed == 0) ? "2.5GT/s," :
> + (gen_speed == 1) ? "5.0GT/s," :
> + (gen_speed == 2) ? "8.0GT/s," :
> + (gen_speed == 3) ? "16.0GT/s," : "",
> + (lane_width == 1) ? "x1" :
> + (lane_width == 2) ? "x2" :
> + (lane_width == 3) ? "x4" :
> + (lane_width == 4) ? "x8" :
> + (lane_width == 5) ? "x12" :
> + (lane_width == 6) ? "x16" : "",
> + smu->smu_table.boot_values.lclk / 100);
We should put a * by the link speed for consistency with other asics.
Alex
> + break;
> +
> default:
> break;
> }
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency
2020-10-14 5:20 [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency Evan Quan
2020-10-14 5:20 ` [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state Evan Quan
@ 2020-10-14 13:19 ` Alex Deucher
1 sibling, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2020-10-14 13:19 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Wed, Oct 14, 2020 at 1:20 AM Evan Quan <evan.quan@amd.com> wrote:
>
> As for other clock domains.
>
> Change-Id: I0a78c133f00cd11133bc755bf0443505088f024c
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
> drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index fafa9c57e32f..9fa9473d418f 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -226,6 +226,7 @@ struct smu_bios_boot_up_values
> uint32_t format_revision;
> uint32_t content_revision;
> uint32_t fclk;
> + uint32_t lclk;
> };
>
> enum smu_table_id
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index a057d1d15087..fbf6d3e35173 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -603,6 +603,11 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
> (uint8_t)SMU11_SYSPLL1_2_ID,
> &smu->smu_table.boot_values.fclk);
>
> + smu_v11_0_atom_get_smu_clockinfo(smu->adev,
> + (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
> + (uint8_t)SMU11_SYSPLL3_1_ID,
> + &smu->smu_table.boot_values.lclk);
> +
> return 0;
> }
>
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
2020-10-14 13:18 ` Alex Deucher
@ 2020-10-15 1:05 ` Quan, Evan
2020-10-15 1:08 ` Alex Deucher
0 siblings, 1 reply; 6+ messages in thread
From: Quan, Evan @ 2020-10-15 1:05 UTC (permalink / raw)
To: Alex Deucher; +Cc: Deucher, Alexander, amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
Hi Alex,
It was intended to align with other ASICs. The output for this on Arcturus is:
0: 8.0GT/s, x16 618Mhz *
Is not that OK?
BR
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Wednesday, October 14, 2020 9:18 PM
To: Quan, Evan <Evan.Quan@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
On Wed, Oct 14, 2020 at 1:21 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Populate current link speed, width and clock domain frequency.
>
> Change-Id: Ic342fbd8f5e2495d212eaa4b85b4e146838e0525
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 18
> ++++++++++++++++++
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 46eea3f8f958..f87411cfa4da 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2124,9 +2124,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
> } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
> if (asic_type < CHIP_VEGA20)
> *states = ATTR_STATE_UNSUPPORTED;
> - } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
> - if (asic_type == CHIP_ARCTURUS)
> - *states = ATTR_STATE_UNSUPPORTED;
> } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
> *states = ATTR_STATE_UNSUPPORTED;
> if ((is_support_sw_smu(adev) && adev->smu.od_enabled)
> || diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index f982b9090d7b..46d950757230 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -720,6 +720,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> struct smu_11_0_dpm_table *single_dpm_table;
> struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
> struct smu_11_0_dpm_context *dpm_context = NULL;
> + uint32_t gen_speed, lane_width;
>
> if (amdgpu_ras_intr_triggered())
> return snprintf(buf, PAGE_SIZE, "unavailable\n"); @@
> -823,6 +824,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> now) ? "*" : ""));
> break;
>
> + case SMU_PCIE:
> + gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
> + lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
> + size += sprintf(buf + size, "0: %s %s %dMhz *\n",
> + (gen_speed == 0) ? "2.5GT/s," :
> + (gen_speed == 1) ? "5.0GT/s," :
> + (gen_speed == 2) ? "8.0GT/s," :
> + (gen_speed == 3) ? "16.0GT/s," : "",
> + (lane_width == 1) ? "x1" :
> + (lane_width == 2) ? "x2" :
> + (lane_width == 3) ? "x4" :
> + (lane_width == 4) ? "x8" :
> + (lane_width == 5) ? "x12" :
> + (lane_width == 6) ? "x16" : "",
> + smu->smu_table.boot_values.lclk /
> + 100);
We should put a * by the link speed for consistency with other asics.
Alex
> + break;
> +
> default:
> break;
> }
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
> an.quan%40amd.com%7C880ed84a1bc14d8df30108d87043a997%7C3dd8961fe4884e6
> 08e11a82d994e183d%7C0%7C0%7C637382783197264100&sdata=kz2KbU6Sn00k9
> jjihiqBnQEkfgI3dFbApLnqLf1Dw98%3D&reserved=0
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
2020-10-15 1:05 ` Quan, Evan
@ 2020-10-15 1:08 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2020-10-15 1:08 UTC (permalink / raw)
To: Quan, Evan; +Cc: Deucher, Alexander, amd-gfx list
On Wed, Oct 14, 2020 at 9:05 PM Quan, Evan <Evan.Quan@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
>
> It was intended to align with other ASICs. The output for this on Arcturus is:
> 0: 8.0GT/s, x16 618Mhz *
> Is not that OK?
Nevermind, I missed the *. I got mixed up comparing with the code for
other asics.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> BR
> Evan
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Wednesday, October 14, 2020 9:18 PM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state
>
> On Wed, Oct 14, 2020 at 1:21 AM Evan Quan <evan.quan@amd.com> wrote:
> >
> > Populate current link speed, width and clock domain frequency.
> >
> > Change-Id: Ic342fbd8f5e2495d212eaa4b85b4e146838e0525
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ---
> > .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 18
> > ++++++++++++++++++
> > 2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > index 46eea3f8f958..f87411cfa4da 100644
> > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > @@ -2124,9 +2124,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
> > } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
> > if (asic_type < CHIP_VEGA20)
> > *states = ATTR_STATE_UNSUPPORTED;
> > - } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
> > - if (asic_type == CHIP_ARCTURUS)
> > - *states = ATTR_STATE_UNSUPPORTED;
> > } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
> > *states = ATTR_STATE_UNSUPPORTED;
> > if ((is_support_sw_smu(adev) && adev->smu.od_enabled)
> > || diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > index f982b9090d7b..46d950757230 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > @@ -720,6 +720,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> > struct smu_11_0_dpm_table *single_dpm_table;
> > struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
> > struct smu_11_0_dpm_context *dpm_context = NULL;
> > + uint32_t gen_speed, lane_width;
> >
> > if (amdgpu_ras_intr_triggered())
> > return snprintf(buf, PAGE_SIZE, "unavailable\n"); @@
> > -823,6 +824,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> > now) ? "*" : ""));
> > break;
> >
> > + case SMU_PCIE:
> > + gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
> > + lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
> > + size += sprintf(buf + size, "0: %s %s %dMhz *\n",
> > + (gen_speed == 0) ? "2.5GT/s," :
> > + (gen_speed == 1) ? "5.0GT/s," :
> > + (gen_speed == 2) ? "8.0GT/s," :
> > + (gen_speed == 3) ? "16.0GT/s," : "",
> > + (lane_width == 1) ? "x1" :
> > + (lane_width == 2) ? "x2" :
> > + (lane_width == 3) ? "x4" :
> > + (lane_width == 4) ? "x8" :
> > + (lane_width == 5) ? "x12" :
> > + (lane_width == 6) ? "x16" : "",
> > + smu->smu_table.boot_values.lclk /
> > + 100);
>
> We should put a * by the link speed for consistency with other asics.
>
> Alex
>
>
> > + break;
> > +
> > default:
> > break;
> > }
> > --
> > 2.28.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
> > an.quan%40amd.com%7C880ed84a1bc14d8df30108d87043a997%7C3dd8961fe4884e6
> > 08e11a82d994e183d%7C0%7C0%7C637382783197264100&sdata=kz2KbU6Sn00k9
> > jjihiqBnQEkfgI3dFbApLnqLf1Dw98%3D&reserved=0
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-10-15 1:08 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-14 5:20 [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency Evan Quan
2020-10-14 5:20 ` [PATCH 2/2] drm/amd/pm: populate Arcturus PCIE link state Evan Quan
2020-10-14 13:18 ` Alex Deucher
2020-10-15 1:05 ` Quan, Evan
2020-10-15 1:08 ` Alex Deucher
2020-10-14 13:19 ` [PATCH 1/2] drm/amd/pm: populate the bootup LCLK frequency Alex Deucher
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