* [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag
@ 2020-11-03 6:16 Jinzhou.Su
2020-11-03 6:16 ` [PATCH 2/3] drm/amdgpu: Add Fine Grain Clock Gating for GFX10 Jinzhou.Su
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jinzhou.Su @ 2020-11-03 6:16 UTC (permalink / raw)
To: amd-gfx; +Cc: Jinzhou.Su, ray.huang
Add AMD_CG_SUPPORT_GFX_FGCG for FGCG
Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Change-Id: I97e10e258e25a60de2604b8a31514421f6819448
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 412602d84f71..9676016a37ce 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -144,6 +144,7 @@ enum amd_powergating_state {
#define AMD_CG_SUPPORT_ATHUB_LS (1 << 28)
#define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
#define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30)
+#define AMD_CG_SUPPORT_GFX_FGCG (1 << 31)
/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 080af05724ed..e57153d1fa24 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -39,6 +39,7 @@
#include "hwmgr.h"
static const struct cg_flag_name clocks[] = {
+ {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
{AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
{AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/amdgpu: Add Fine Grain Clock Gating for GFX10
2020-11-03 6:16 [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag Jinzhou.Su
@ 2020-11-03 6:16 ` Jinzhou.Su
2020-11-03 6:16 ` [PATCH 3/3] drm/amdgpu: Enable FGCG for Vangogh Jinzhou.Su
2020-11-03 7:04 ` [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag Huang Rui
2 siblings, 0 replies; 4+ messages in thread
From: Jinzhou.Su @ 2020-11-03 6:16 UTC (permalink / raw)
To: amd-gfx; +Cc: Jinzhou.Su, ray.huang
1. Add FGCG for gfx10
2. Get FGCG status for pm info debugfs
Change-Id: I4df242c4afb0907706a1aaafb04c89cad2495b13
Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 76eba25b2d9a..7b396b21099e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7658,12 +7658,50 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
}
}
+static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
+ def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+ /* unset FGCG override */
+ data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
+ /* update FGCG override bits */
+ if (def != data)
+ WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
+
+ def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
+ /* unset RLC SRAM CLK GATER override */
+ data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
+ /* update RLC SRAM CLK GATER override bits */
+ if (def != data)
+ WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
+ } else {
+ def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+ /* reset FGCG bits */
+ data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
+ /* disable FGCG*/
+ if (def != data)
+ WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
+
+ def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
+ /* reset RLC SRAM CLK GATER bits */
+ data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
+ /* disable RLC SRAM CLK*/
+ if (def != data)
+ WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
+ }
+}
+
static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
+ /* enable FGCG firstly*/
+ gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
/* CGCG/CGLS should be enabled after MGCG/MGLS
* === MGCG + MGLS ===
*/
@@ -7681,6 +7719,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
gfx_v10_0_update_3d_clock_gating(adev, enable);
/* === MGCG + MGLS === */
gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
+ /* disable fgcg at last*/
+ gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
}
if (adev->cg_flags &
@@ -7849,6 +7889,11 @@ static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int data;
+ /* AMD_CG_SUPPORT_GFX_FGCG */
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
+ if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
+ *flags |= AMD_CG_SUPPORT_GFX_FGCG;
+
/* AMD_CG_SUPPORT_GFX_MGCG */
data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amdgpu: Enable FGCG for Vangogh
2020-11-03 6:16 [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag Jinzhou.Su
2020-11-03 6:16 ` [PATCH 2/3] drm/amdgpu: Add Fine Grain Clock Gating for GFX10 Jinzhou.Su
@ 2020-11-03 6:16 ` Jinzhou.Su
2020-11-03 7:04 ` [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag Huang Rui
2 siblings, 0 replies; 4+ messages in thread
From: Jinzhou.Su @ 2020-11-03 6:16 UTC (permalink / raw)
To: amd-gfx; +Cc: Jinzhou.Su, ray.huang
Add flags AMD_CG_SUPPORT_GFX_FGCG for Vangogh
Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Change-Id: I730754a0929368bb35221e586fbfa5bda0af0eaf
---
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 1f8659a1a4cf..e33d8022cc32 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -953,6 +953,7 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_GFX_FGCG |
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag
2020-11-03 6:16 [PATCH 1/3] drm/amdgpu: Add GFX Fine Grain Clock Gating flag Jinzhou.Su
2020-11-03 6:16 ` [PATCH 2/3] drm/amdgpu: Add Fine Grain Clock Gating for GFX10 Jinzhou.Su
2020-11-03 6:16 ` [PATCH 3/3] drm/amdgpu: Enable FGCG for Vangogh Jinzhou.Su
@ 2020-11-03 7:04 ` Huang Rui
2 siblings, 0 replies; 4+ messages in thread
From: Huang Rui @ 2020-11-03 7:04 UTC (permalink / raw)
To: Su, Jinzhou (Joe); +Cc: amd-gfx@lists.freedesktop.org
With Kevin's comments addressed (remove change-id), the series are
Reviewed-by: Huang Rui <ray.huang@amd.com>
On Tue, Nov 03, 2020 at 02:16:19PM +0800, Su, Jinzhou (Joe) wrote:
> Add AMD_CG_SUPPORT_GFX_FGCG for FGCG
>
> Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
> Change-Id: I97e10e258e25a60de2604b8a31514421f6819448
> ---
> drivers/gpu/drm/amd/include/amd_shared.h | 1 +
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index 412602d84f71..9676016a37ce 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -144,6 +144,7 @@ enum amd_powergating_state {
> #define AMD_CG_SUPPORT_ATHUB_LS (1 << 28)
> #define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
> #define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30)
> +#define AMD_CG_SUPPORT_GFX_FGCG (1 << 31)
> /* PG flags */
> #define AMD_PG_SUPPORT_GFX_PG (1 << 0)
> #define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 080af05724ed..e57153d1fa24 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -39,6 +39,7 @@
> #include "hwmgr.h"
>
> static const struct cg_flag_name clocks[] = {
> + {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
> {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
> {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
> {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2020-11-03 6:16 ` [PATCH 3/3] drm/amdgpu: Enable FGCG for Vangogh Jinzhou.Su
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