Re: [PATCH 3/4] drm/amdgpu: fix mode2 reset sequence for vangogh

From: Huang Rui <ray.huang@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/amdgpu: fix mode2 reset sequence for vangogh
Date: Thu, 26 Nov 2020 11:13:11 +0800	[thread overview]
Message-ID: <20201126031311.GA587229@hr-amd> (raw)
In-Reply-To: <20201125162132.237264-3-alexander.deucher@amd.com>

On Wed, Nov 25, 2020 at 11:21:31AM -0500, Alex Deucher wrote:
> We need to save and restore PCI config space.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Series are Reviewed-by: Huang Rui <ray.huang@amd.com>

Hi xiaomeng, let's verify these patch set in your platform.

> ---
>  drivers/gpu/drm/amd/amdgpu/nv.c | 34 ++++++++++++++++++++++++++++++++-
>  1 file changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 221a29cdc0aa..70d6556cd01d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -336,6 +336,38 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
>  	return ret;
>  }
>  
> +static int nv_asic_mode2_reset(struct amdgpu_device *adev)
> +{
> +	u32 i;
> +	int ret = 0;
> +
> +	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
> +
> +	/* disable BM */
> +	pci_clear_master(adev->pdev);
> +
> +	amdgpu_device_cache_pci_state(adev->pdev);
> +
> +	ret = amdgpu_dpm_mode2_reset(adev);
> +	if (ret)
> +		dev_err(adev->dev, "GPU mode2 reset failed\n");
> +
> +	amdgpu_device_load_pci_state(adev->pdev);
> +
> +	/* wait for asic to come out of reset */
> +	for (i = 0; i < adev->usec_timeout; i++) {
> +		u32 memsize = adev->nbio.funcs->get_memsize(adev);
> +
> +		if (memsize != 0xffffffff)
> +			break;
> +		udelay(1);
> +	}
> +
> +	amdgpu_atombios_scratch_regs_engine_hung(adev, false);
> +
> +	return ret;
> +}
> +
>  static bool nv_asic_supports_baco(struct amdgpu_device *adev)
>  {
>  	struct smu_context *smu = &adev->smu;
> @@ -392,7 +424,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
>  		break;
>  	case AMD_RESET_METHOD_MODE2:
>  		dev_info(adev->dev, "MODE2 reset\n");
> -		ret = amdgpu_dpm_mode2_reset(adev);
> +		ret = nv_asic_mode2_reset(adev);
>  		break;
>  	default:
>  		dev_info(adev->dev, "MODE1 reset\n");
> -- 
> 2.25.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cray.huang%40amd.com%7C232f4d9376fa46595ab708d8915e348c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637419181097974222%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=G4MJVzemXHXDbWv53OWKVtD3DnJGgSs4TYbIEkQE2PE%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx