* [PATCH 1/3] drm/amdgpu: check number of gfx ring before init cp gfx
@ 2020-12-09 15:28 Hawking Zhang
2020-12-09 15:28 ` [PATCH 2/3] drm/amdgpu: remove unnecessary asic type check Hawking Zhang
2020-12-09 15:28 ` [PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts Hawking Zhang
0 siblings, 2 replies; 4+ messages in thread
From: Hawking Zhang @ 2020-12-09 15:28 UTC (permalink / raw)
To: amd-gfx, Alex Deucher; +Cc: Hawking Zhang
Check number of gfx ring, rather than asic type,
before cp gfx engine initialization so driver just
need to make sure number of gfx ring is initialized
correctly in gfx early_init phase. No need to add
additional asic type check everywhere when there is
new asic with gfx pipe removed.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fc9bb94eaaf4..ef430f285472 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1647,7 +1647,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
}
/* No CPG in Arcturus */
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
if (r)
return r;
@@ -3822,7 +3822,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
gfx_v9_0_enable_gui_idle_interrupt(adev, false);
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
/* legacy firmware loading */
r = gfx_v9_0_cp_gfx_load_microcode(adev);
if (r)
@@ -3838,7 +3838,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
if (r)
return r;
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
r = gfx_v9_0_cp_gfx_resume(adev);
if (r)
return r;
@@ -3848,7 +3848,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
if (r)
return r;
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
ring = &adev->gfx.gfx_ring[0];
r = amdgpu_ring_test_helper(ring);
if (r)
@@ -3884,7 +3884,7 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
{
- if (adev->asic_type != CHIP_ARCTURUS)
+ if (adev->gfx.num_gfx_rings)
gfx_v9_0_cp_gfx_enable(adev, enable);
gfx_v9_0_cp_compute_enable(adev, enable);
}
@@ -4025,7 +4025,7 @@ static int gfx_v9_0_soft_reset(void *handle)
/* stop the rlc */
adev->gfx.rlc.funcs->stop(adev);
- if (adev->asic_type != CHIP_ARCTURUS)
+ if (adev->gfx.num_gfx_rings)
/* Disable GFX parsing/prefetching */
gfx_v9_0_cp_gfx_enable(adev, false);
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/3] drm/amdgpu: remove unnecessary asic type check
2020-12-09 15:28 [PATCH 1/3] drm/amdgpu: check number of gfx ring before init cp gfx Hawking Zhang
@ 2020-12-09 15:28 ` Hawking Zhang
2020-12-09 15:28 ` [PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts Hawking Zhang
1 sibling, 0 replies; 4+ messages in thread
From: Hawking Zhang @ 2020-12-09 15:28 UTC (permalink / raw)
To: amd-gfx, Alex Deucher; +Cc: Hawking Zhang
The number of crtc should be 0 for ASICs that don't
have display engine. Remove the unnecessary asic type
check then.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 07126b2b46c2..f34d39e43ea4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1579,13 +1579,10 @@ static int gmc_v9_0_hw_init(void *handle)
gmc_v9_0_init_golden_registers(adev);
if (adev->mode_info.num_crtc) {
- if (adev->asic_type != CHIP_ARCTURUS) {
- /* Lockout access through VGA aperture*/
- WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
-
- /* disable VGA render */
- WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
- }
+ /* Lockout access through VGA aperture*/
+ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
+ /* disable VGA render */
+ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
}
amdgpu_device_program_register_sequence(adev,
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts
2020-12-09 15:28 [PATCH 1/3] drm/amdgpu: check number of gfx ring before init cp gfx Hawking Zhang
2020-12-09 15:28 ` [PATCH 2/3] drm/amdgpu: remove unnecessary asic type check Hawking Zhang
@ 2020-12-09 15:28 ` Hawking Zhang
2020-12-10 18:17 ` Alex Deucher
1 sibling, 1 reply; 4+ messages in thread
From: Hawking Zhang @ 2020-12-09 15:28 UTC (permalink / raw)
To: amd-gfx, Alex Deucher; +Cc: Hawking Zhang
GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0
are only applicable to me0 pipe0.
For ASICs that have gfx pipe removed, don't toggle
those bits.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ef430f285472..5f4805e4d04a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
- u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
+ u32 tmp;
+
+ /* don't toggle interrupts that are only applicable
+ * to me0 pipe0 on AISCs that have me0 removed */
+ if (!adev->gfx.num_gfx_rings)
+ return;
+
+ tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts
2020-12-09 15:28 ` [PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts Hawking Zhang
@ 2020-12-10 18:17 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2020-12-10 18:17 UTC (permalink / raw)
To: Hawking Zhang; +Cc: Alex Deucher, amd-gfx list
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
On Wed, Dec 9, 2020 at 10:29 AM Hawking Zhang <Hawking.Zhang@amd.com> wrote:
>
> GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0
> are only applicable to me0 pipe0.
>
> For ASICs that have gfx pipe removed, don't toggle
> those bits.
>
> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ef430f285472..5f4805e4d04a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
> static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> bool enable)
> {
> - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
> + u32 tmp;
> +
> + /* don't toggle interrupts that are only applicable
> + * to me0 pipe0 on AISCs that have me0 removed */
> + if (!adev->gfx.num_gfx_rings)
> + return;
> +
> + tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
> tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-12-10 18:18 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2020-12-09 15:28 [PATCH 1/3] drm/amdgpu: check number of gfx ring before init cp gfx Hawking Zhang
2020-12-09 15:28 ` [PATCH 2/3] drm/amdgpu: remove unnecessary asic type check Hawking Zhang
2020-12-09 15:28 ` [PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts Hawking Zhang
2020-12-10 18:17 ` Alex Deucher
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