* [PATCH 1/2] drm/amd/pm: modify the fine grain tuning function for Renoir
@ 2021-01-13 11:22 Xiaojian Du
2021-01-13 11:22 ` [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh Xiaojian Du
0 siblings, 1 reply; 4+ messages in thread
From: Xiaojian Du @ 2021-01-13 11:22 UTC (permalink / raw)
To: amd-gfx; +Cc: lijo.lazar, kevin1.wang, ray.huang, Xiaojian Du, evan.quan
This patch is to modify the fine grain tuning function for Renoir.
The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage
to config gfxclk. Meanwhile, another sysfs
node -- power_dpm_force_perfomance_level also affects the gfx clk.
It will cause confusion when these two sysfs nodes works
together.
This patch uses the existing flag to make these two sysfs nodes works
separately. Only when power_dpm_force_perfomance_level is changed
to "manual" mode, the fine grain function will be started.
In other profile modes, including "auto", "high", "low", "profile_peak",
"profile_standard", "profile_min_sclk", "profile_min_mclk",
the fine grain tuning function will be shut down and the frequency range
of gfx will be restored the default value.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ----
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 20 +++++--------------
3 files changed, 6 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index ecd72d896b49..80d6298912aa 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2221,7 +2221,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
*states = ATTR_STATE_UNSUPPORTED;
if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
- (is_support_sw_smu(adev) && adev->smu.fine_grain_enabled) ||
+ (is_support_sw_smu(adev) && adev->smu.is_apu) ||
(!is_support_sw_smu(adev) && hwmgr->od_enabled))
*states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index e94d1b4551b4..976a9105aecc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -416,10 +416,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
break;
case CHIP_RENOIR:
renoir_set_ppt_funcs(smu);
- /* enable the fine grain tuning function by default */
- smu->fine_grain_enabled = true;
- /* close the fine grain tuning function by default */
- smu->fine_grain_started = false;
break;
case CHIP_VANGOGH:
vangogh_set_ppt_funcs(smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index f33f5141cbe1..6c8a8ccd2f84 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -349,17 +349,13 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu,
long input[], uint32_t size)
{
int ret = 0;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- if (!smu->fine_grain_enabled) {
+ if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
return -EINVAL;
}
- if (!smu->fine_grain_started) {
- dev_warn(smu->adev->dev, "Fine grain is enabled but not started!\n");
- return -EINVAL;
- }
-
switch (type) {
case PP_OD_EDIT_SCLK_VDDC_TABLE:
if (size != 2) {
@@ -482,6 +478,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
SmuMetrics_t metrics;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
bool cur_value_match_level = false;
memset(&metrics, 0, sizeof(metrics));
@@ -492,7 +489,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
switch (clk_type) {
case SMU_OD_RANGE:
- if (smu->fine_grain_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetMinGfxclkFrequency,
0, &min);
@@ -507,7 +504,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
}
break;
case SMU_OD_SCLK:
- if (smu->fine_grain_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
size += sprintf(buf + size, "OD_SCLK\n");
@@ -897,28 +894,24 @@ static int renoir_set_performance_level(struct smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- smu->fine_grain_started = 0;
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
ret = renoir_force_dpm_limit_value(smu, true);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- smu->fine_grain_started = 0;
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
ret = renoir_force_dpm_limit_value(smu, false);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
- smu->fine_grain_started = 0;
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
ret = renoir_unforce_dpm_levels(smu);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- smu->fine_grain_started = 0;
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
@@ -974,7 +967,6 @@ static int renoir_set_performance_level(struct smu_context *smu,
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
- smu->fine_grain_started = 0;
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
@@ -989,14 +981,12 @@ static int renoir_set_performance_level(struct smu_context *smu,
renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- smu->fine_grain_started = 0;
smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
ret = renoir_set_peak_clock_by_device(smu);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
- smu->fine_grain_started = 1;
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
default:
break;
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh
2021-01-13 11:22 [PATCH 1/2] drm/amd/pm: modify the fine grain tuning function for Renoir Xiaojian Du
@ 2021-01-13 11:22 ` Xiaojian Du
2021-01-13 11:49 ` Wang, Kevin(Yang)
2021-01-14 2:57 ` Huang Rui
0 siblings, 2 replies; 4+ messages in thread
From: Xiaojian Du @ 2021-01-13 11:22 UTC (permalink / raw)
To: amd-gfx; +Cc: lijo.lazar, kevin1.wang, ray.huang, Xiaojian Du, evan.quan
This patch is to modify the fine grain tuning function for vangogh.
It is risky to add two new flags to common smu struct.
So this patch uses the existing old flag to make the two sysfs files
work separately -- "power_dpm_force_performance_level" and
"pp_od_clk_voltage".
Only the power_dpm_force_performance_level is switched to "manual"
mode, the fine grain tuning function will be started.
In other mode, including "high","low","min_sclk","min_mclk",
"standard" and "peak", the fine grain tuning function will be shut down,
and the frequency range of gfx and cpu clock will be restored the
default values.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 --
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 52 +++++++++++++++++--
3 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 277559e80961..25ee9f51813b 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -466,9 +466,6 @@ struct smu_context
uint32_t gfx_actual_hard_min_freq;
uint32_t gfx_actual_soft_max_freq;
- bool fine_grain_enabled;
- bool fine_grain_started;
-
uint32_t cpu_default_soft_min_freq;
uint32_t cpu_default_soft_max_freq;
uint32_t cpu_actual_soft_min_freq;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 976a9105aecc..7fe61ad3ed10 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -419,8 +419,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
break;
case CHIP_VANGOGH:
vangogh_set_ppt_funcs(smu);
- /* enable the OD by default to allow the fine grain tuning function */
- smu->od_enabled = true;
break;
default:
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index b49044825680..3e32b223d47b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -438,6 +438,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
@@ -450,7 +451,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
switch (clk_type) {
case SMU_OD_SCLK:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "%s:\n", "OD_SCLK");
size += sprintf(buf + size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
@@ -459,7 +460,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
}
break;
case SMU_OD_CCLK:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
size += sprintf(buf + size, "0: %10uMhz\n",
(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
@@ -468,7 +469,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
}
break;
case SMU_OD_RANGE:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "%s:\n", "OD_RANGE");
size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
@@ -1127,15 +1128,39 @@ static int vangogh_set_performance_level(struct smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_force_dpm_limit_value(smu, true);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_force_dpm_limit_value(smu, false);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_unforce_dpm_levels(smu);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_SetHardMinGfxClk,
VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
@@ -1165,6 +1190,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
if (ret)
@@ -1176,6 +1207,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
return ret;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_get_profiling_clk_mask(smu, level,
NULL,
NULL,
@@ -1189,6 +1226,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
if (ret)
@@ -1401,8 +1444,9 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
{
int ret = 0;
int i;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- if (!smu->od_enabled) {
+ if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
return -EINVAL;
}
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh
2021-01-13 11:22 ` [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh Xiaojian Du
@ 2021-01-13 11:49 ` Wang, Kevin(Yang)
2021-01-14 2:57 ` Huang Rui
1 sibling, 0 replies; 4+ messages in thread
From: Wang, Kevin(Yang) @ 2021-01-13 11:49 UTC (permalink / raw)
To: Du, Xiaojian, amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo, Huang, Ray, Quan, Evan
[-- Attachment #1.1: Type: text/plain, Size: 9832 bytes --]
[AMD Official Use Only - Internal Distribution Only]
________________________________
From: Du, Xiaojian <Xiaojian.Du@amd.com>
Sent: Wednesday, January 13, 2021 7:22 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Huang, Ray <Ray.Huang@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Lazar, Lijo <Lijo.Lazar@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
Subject: [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh
This patch is to modify the fine grain tuning function for vangogh.
It is risky to add two new flags to common smu struct.
So this patch uses the existing old flag to make the two sysfs files
work separately -- "power_dpm_force_performance_level" and
"pp_od_clk_voltage".
Only the power_dpm_force_performance_level is switched to "manual"
mode, the fine grain tuning function will be started.
In other mode, including "high","low","min_sclk","min_mclk",
"standard" and "peak", the fine grain tuning function will be shut down,
and the frequency range of gfx and cpu clock will be restored the
default values.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 --
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 52 +++++++++++++++++--
3 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 277559e80961..25ee9f51813b 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -466,9 +466,6 @@ struct smu_context
uint32_t gfx_actual_hard_min_freq;
uint32_t gfx_actual_soft_max_freq;
- bool fine_grain_enabled;
- bool fine_grain_started;
-
[Kevin]:
the above codes should be merge into previous patch.
with the fixed, the patch is
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Best Regards,
Kevin
uint32_t cpu_default_soft_min_freq;
uint32_t cpu_default_soft_max_freq;
uint32_t cpu_actual_soft_min_freq;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 976a9105aecc..7fe61ad3ed10 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -419,8 +419,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
break;
case CHIP_VANGOGH:
vangogh_set_ppt_funcs(smu);
- /* enable the OD by default to allow the fine grain tuning function */
- smu->od_enabled = true;
break;
default:
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index b49044825680..3e32b223d47b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -438,6 +438,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
{
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
@@ -450,7 +451,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
switch (clk_type) {
case SMU_OD_SCLK:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "%s:\n", "OD_SCLK");
size += sprintf(buf + size, "0: %10uMhz\n",
(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
@@ -459,7 +460,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
}
break;
case SMU_OD_CCLK:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
size += sprintf(buf + size, "0: %10uMhz\n",
(smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
@@ -468,7 +469,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
}
break;
case SMU_OD_RANGE:
- if (smu->od_enabled) {
+ if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
size = sprintf(buf, "%s:\n", "OD_RANGE");
size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
@@ -1127,15 +1128,39 @@ static int vangogh_set_performance_level(struct smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_force_dpm_limit_value(smu, true);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_force_dpm_limit_value(smu, false);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_unforce_dpm_levels(smu);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_SetHardMinGfxClk,
VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
@@ -1165,6 +1190,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
if (ret)
@@ -1176,6 +1207,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
return ret;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = vangogh_get_profiling_clk_mask(smu, level,
NULL,
NULL,
@@ -1189,6 +1226,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+ smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+ smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
+ smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
if (ret)
@@ -1401,8 +1444,9 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
{
int ret = 0;
int i;
+ struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- if (!smu->od_enabled) {
+ if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
return -EINVAL;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh
2021-01-13 11:22 ` [PATCH 2/2] drm/amd/pm: modify the fine grain tuning function for vangogh Xiaojian Du
2021-01-13 11:49 ` Wang, Kevin(Yang)
@ 2021-01-14 2:57 ` Huang Rui
1 sibling, 0 replies; 4+ messages in thread
From: Huang Rui @ 2021-01-14 2:57 UTC (permalink / raw)
To: Du, Xiaojian
Cc: Lazar, Lijo, Wang, Kevin(Yang), Quan, Evan,
amd-gfx@lists.freedesktop.org
On Wed, Jan 13, 2021 at 07:22:04PM +0800, Du, Xiaojian wrote:
> This patch is to modify the fine grain tuning function for vangogh.
> It is risky to add two new flags to common smu struct.
> So this patch uses the existing old flag to make the two sysfs files
> work separately -- "power_dpm_force_performance_level" and
> "pp_od_clk_voltage".
> Only the power_dpm_force_performance_level is switched to "manual"
> mode, the fine grain tuning function will be started.
> In other mode, including "high","low","min_sclk","min_mclk",
> "standard" and "peak", the fine grain tuning function will be shut down,
> and the frequency range of gfx and cpu clock will be restored the
> default values.
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Series are Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 --
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 52 +++++++++++++++++--
> 3 files changed, 48 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 277559e80961..25ee9f51813b 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -466,9 +466,6 @@ struct smu_context
> uint32_t gfx_actual_hard_min_freq;
> uint32_t gfx_actual_soft_max_freq;
>
> - bool fine_grain_enabled;
> - bool fine_grain_started;
> -
> uint32_t cpu_default_soft_min_freq;
> uint32_t cpu_default_soft_max_freq;
> uint32_t cpu_actual_soft_min_freq;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 976a9105aecc..7fe61ad3ed10 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -419,8 +419,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> break;
> case CHIP_VANGOGH:
> vangogh_set_ppt_funcs(smu);
> - /* enable the OD by default to allow the fine grain tuning function */
> - smu->od_enabled = true;
> break;
> default:
> return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index b49044825680..3e32b223d47b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -438,6 +438,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
> {
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> int i, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> @@ -450,7 +451,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
>
> switch (clk_type) {
> case SMU_OD_SCLK:
> - if (smu->od_enabled) {
> + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
> size = sprintf(buf, "%s:\n", "OD_SCLK");
> size += sprintf(buf + size, "0: %10uMhz\n",
> (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
> @@ -459,7 +460,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
> }
> break;
> case SMU_OD_CCLK:
> - if (smu->od_enabled) {
> + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
> size = sprintf(buf, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
> size += sprintf(buf + size, "0: %10uMhz\n",
> (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
> @@ -468,7 +469,7 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
> }
> break;
> case SMU_OD_RANGE:
> - if (smu->od_enabled) {
> + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
> size = sprintf(buf, "%s:\n", "OD_RANGE");
> size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
> smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
> @@ -1127,15 +1128,39 @@ static int vangogh_set_performance_level(struct smu_context *smu,
>
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_force_dpm_limit_value(smu, true);
> break;
> case AMD_DPM_FORCED_LEVEL_LOW:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_force_dpm_limit_value(smu, false);
> break;
> case AMD_DPM_FORCED_LEVEL_AUTO:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_unforce_dpm_levels(smu);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetHardMinGfxClk,
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
> @@ -1165,6 +1190,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
>
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn,
> VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
> if (ret)
> @@ -1176,6 +1207,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
> return ret;
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = vangogh_get_profiling_clk_mask(smu, level,
> NULL,
> NULL,
> @@ -1189,6 +1226,12 @@ static int vangogh_set_performance_level(struct smu_context *smu,
> vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
> + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +
> + smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> +
> ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
> VANGOGH_UMD_PSTATE_PEAK_GFXCLK, NULL);
> if (ret)
> @@ -1401,8 +1444,9 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
> {
> int ret = 0;
> int i;
> + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
>
> - if (!smu->od_enabled) {
> + if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
> dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
> return -EINVAL;
> }
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-01-14 2:57 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2021-01-13 11:22 [PATCH 1/2] drm/amd/pm: modify the fine grain tuning function for Renoir Xiaojian Du
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2021-01-13 11:49 ` Wang, Kevin(Yang)
2021-01-14 2:57 ` Huang Rui
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