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From: Anson Jacob <Anson.Jacob@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Sung Lee <Sung.Lee@amd.com>,
	Eryk.Brol@amd.com, Jake Wang <haonan.wang2@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Anson Jacob <anson.jacob@amd.com>,
	Aurabindo.Pillai@amd.com, Bhawanpreet.Lakha@amd.com,
	bindu.r@amd.com
Subject: [PATCH 14/16] drm/amd/display: Update dram_clock_change_latency for DCN2.1
Date: Fri, 15 Jan 2021 12:27:16 -0500	[thread overview]
Message-ID: <20210115172714.126866-15-Anson.Jacob@amd.com> (raw)
In-Reply-To: <20210115172714.126866-1-Anson.Jacob@amd.com>

From: Jake Wang <haonan.wang2@amd.com>

[WHY]
dram clock change latencies get updated using ddr4 latency table, but
that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.

[HOW]
Update latency from 23.84 to 11.72.

Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 1c88d2edd381..b000b43a820d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -296,7 +296,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 	.num_banks = 8,
 	.num_chans = 4,
 	.vmm_page_size_bytes = 4096,
-	.dram_clock_change_latency_us = 23.84,
+	.dram_clock_change_latency_us = 11.72,
 	.return_bus_width_bytes = 64,
 	.dispclk_dppclk_vco_speed_mhz = 3600,
 	.xfc_bus_transport_time_us = 4,
-- 
2.25.1

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  parent reply	other threads:[~2021-01-15 17:31 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15 17:26 [PATCH 00/16] DC Patches January 15, 2020 Anson Jacob
2021-01-15 17:27 ` [PATCH 01/16] drm/amd/display: Fixed corruptions on HPDRX link loss restore Anson Jacob
2021-01-15 17:27 ` [PATCH 02/16] drm/amd/display: disable FEC while using eDP Anson Jacob
2021-01-15 17:27 ` [PATCH 03/16] drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM Case Anson Jacob
2021-01-15 17:27 ` [PATCH 04/16] drm/amd/display: Use hardware sequencer functions for PG control Anson Jacob
2021-01-15 17:27 ` [PATCH 05/16] drm/amd/display: Report Freesync to vrr_range debugfs entry in DRM Anson Jacob
2021-01-15 17:27 ` [PATCH 06/16] drm/amd/display: Allow dmub srv hardware reset before HW init Anson Jacob
2021-01-15 17:27 ` [PATCH 07/16] drm/amd/display: Guard against NULL pointer deref when get_i2c_info fails Anson Jacob
2021-01-15 17:27 ` [PATCH 08/16] drm/amd/display: Fix reset sequence with driver direct DMCUB fw load Anson Jacob
2021-01-15 17:27 ` [PATCH 09/16] drm/amd/display: Change function decide_dp_link_settings to avoid infinite looping Anson Jacob
2021-01-15 17:27 ` [PATCH 10/16] drm/amd/display: Allow dmu_stg to support cached inbox for dmub Anson Jacob
2021-01-15 17:27 ` [PATCH 11/16] drm/amd/display: Log link/connector info provided in BIOS object table Anson Jacob
2021-01-15 17:27 ` [PATCH 12/16] drm/amd/display: Fix dml20v2_ModeSupportAndSystemConfigurationFull() to check DesiredBPP Anson Jacob
2021-01-15 17:27 ` [PATCH 13/16] drm/amd/display: Allow PSTATE chnage when no displays are enabled Anson Jacob
2021-01-15 17:27 ` Anson Jacob [this message]
2021-01-15 17:27 ` [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.48 Anson Jacob
2021-01-15 17:27 ` [PATCH 16/16] drm/amd/display: 3.2.119 Anson Jacob
2021-01-18 12:04   ` Paul Menzel
2021-01-15 22:36 ` [PATCH 00/16] DC Patches January 15, 2020 Wheeler, Daniel

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