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From: Anson Jacob <Anson.Jacob@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eric Yang <eric.yang2@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Anson Jacob <anson.jacob@amd.com>,
	Aurabindo.Pillai@amd.com, Bhawanpreet.Lakha@amd.com,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
	bindu.r@amd.com
Subject: [PATCH 04/16] drm/amd/display: Use hardware sequencer functions for PG control
Date: Fri, 15 Jan 2021 12:27:06 -0500	[thread overview]
Message-ID: <20210115172714.126866-5-Anson.Jacob@amd.com> (raw)
In-Reply-To: <20210115172714.126866-1-Anson.Jacob@amd.com>

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why & How]
These can differ per ASIC or not be present. Don't call the dcn20 ones
directly but rather the ones defined by the ASIC init table.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 18 ++++++++++++++----
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  9 +++++++--
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index add86d4086e8..7a30d1d9b535 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -647,8 +647,13 @@ static void power_on_plane(
 	if (REG(DC_IP_REQUEST_CNTL)) {
 		REG_SET(DC_IP_REQUEST_CNTL, 0,
 				IP_REQUEST_EN, 1);
-		hws->funcs.dpp_pg_control(hws, plane_id, true);
-		hws->funcs.hubp_pg_control(hws, plane_id, true);
+
+		if (hws->funcs.dpp_pg_control)
+			hws->funcs.dpp_pg_control(hws, plane_id, true);
+
+		if (hws->funcs.hubp_pg_control)
+			hws->funcs.hubp_pg_control(hws, plane_id, true);
+
 		REG_SET(DC_IP_REQUEST_CNTL, 0,
 				IP_REQUEST_EN, 0);
 		DC_LOG_DEBUG(
@@ -1082,8 +1087,13 @@ void dcn10_plane_atomic_power_down(struct dc *dc,
 	if (REG(DC_IP_REQUEST_CNTL)) {
 		REG_SET(DC_IP_REQUEST_CNTL, 0,
 				IP_REQUEST_EN, 1);
-		hws->funcs.dpp_pg_control(hws, dpp->inst, false);
-		hws->funcs.hubp_pg_control(hws, hubp->inst, false);
+
+		if (hws->funcs.dpp_pg_control)
+			hws->funcs.dpp_pg_control(hws, dpp->inst, false);
+
+		if (hws->funcs.hubp_pg_control)
+			hws->funcs.hubp_pg_control(hws, hubp->inst, false);
+
 		dpp->funcs->dpp_reset(dpp);
 		REG_SET(DC_IP_REQUEST_CNTL, 0,
 				IP_REQUEST_EN, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 18653c423c96..0726fb435e2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1062,8 +1062,13 @@ static void dcn20_power_on_plane(
 	if (REG(DC_IP_REQUEST_CNTL)) {
 		REG_SET(DC_IP_REQUEST_CNTL, 0,
 				IP_REQUEST_EN, 1);
-		dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
-		dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
+
+		if (hws->funcs.dpp_pg_control)
+			hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
+
+		if (hws->funcs.hubp_pg_control)
+			hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
+
 		REG_SET(DC_IP_REQUEST_CNTL, 0,
 				IP_REQUEST_EN, 0);
 		DC_LOG_DEBUG(
-- 
2.25.1

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  parent reply	other threads:[~2021-01-15 17:30 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15 17:26 [PATCH 00/16] DC Patches January 15, 2020 Anson Jacob
2021-01-15 17:27 ` [PATCH 01/16] drm/amd/display: Fixed corruptions on HPDRX link loss restore Anson Jacob
2021-01-15 17:27 ` [PATCH 02/16] drm/amd/display: disable FEC while using eDP Anson Jacob
2021-01-15 17:27 ` [PATCH 03/16] drm/amd/display: DCN2X Find Secondary Pipe properly in MPO + ODM Case Anson Jacob
2021-01-15 17:27 ` Anson Jacob [this message]
2021-01-15 17:27 ` [PATCH 05/16] drm/amd/display: Report Freesync to vrr_range debugfs entry in DRM Anson Jacob
2021-01-15 17:27 ` [PATCH 06/16] drm/amd/display: Allow dmub srv hardware reset before HW init Anson Jacob
2021-01-15 17:27 ` [PATCH 07/16] drm/amd/display: Guard against NULL pointer deref when get_i2c_info fails Anson Jacob
2021-01-15 17:27 ` [PATCH 08/16] drm/amd/display: Fix reset sequence with driver direct DMCUB fw load Anson Jacob
2021-01-15 17:27 ` [PATCH 09/16] drm/amd/display: Change function decide_dp_link_settings to avoid infinite looping Anson Jacob
2021-01-15 17:27 ` [PATCH 10/16] drm/amd/display: Allow dmu_stg to support cached inbox for dmub Anson Jacob
2021-01-15 17:27 ` [PATCH 11/16] drm/amd/display: Log link/connector info provided in BIOS object table Anson Jacob
2021-01-15 17:27 ` [PATCH 12/16] drm/amd/display: Fix dml20v2_ModeSupportAndSystemConfigurationFull() to check DesiredBPP Anson Jacob
2021-01-15 17:27 ` [PATCH 13/16] drm/amd/display: Allow PSTATE chnage when no displays are enabled Anson Jacob
2021-01-15 17:27 ` [PATCH 14/16] drm/amd/display: Update dram_clock_change_latency for DCN2.1 Anson Jacob
2021-01-15 17:27 ` [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.48 Anson Jacob
2021-01-15 17:27 ` [PATCH 16/16] drm/amd/display: 3.2.119 Anson Jacob
2021-01-18 12:04   ` Paul Menzel
2021-01-15 22:36 ` [PATCH 00/16] DC Patches January 15, 2020 Wheeler, Daniel

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