* [PATCH] drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
@ 2021-01-20 3:09 Jinzhou Su
2021-01-20 3:14 ` Huang Rui
0 siblings, 1 reply; 4+ messages in thread
From: Jinzhou Su @ 2021-01-20 3:09 UTC (permalink / raw)
To: amd-gfx; +Cc: Jinzhou Su, ray.huang
Driver should enable the CGPG feature for RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence.
Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in refclk count.
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c4314e25f560..dd102cc2516a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -120,6 +120,7 @@
#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
#define mmGCR_GENERAL_CNTL_Vangogh 0x1580
#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
@@ -7829,6 +7830,20 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+
+ /*
+ * CGPG enablement required and the register to program the hysteresis value
+ * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
+ * in refclk count. Note that RLC FW is modified to take 16 bits from
+ * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
+ *
+ * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
+ * as part of CGPG enablement starting point.
+ */
+ if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
+ data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+ WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+ }
}
static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
2021-01-20 3:09 [PATCH] drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh Jinzhou Su
@ 2021-01-20 3:14 ` Huang Rui
0 siblings, 0 replies; 4+ messages in thread
From: Huang Rui @ 2021-01-20 3:14 UTC (permalink / raw)
To: Su, Jinzhou (Joe); +Cc: amd-gfx@lists.freedesktop.org
On Wed, Jan 20, 2021 at 11:09:11AM +0800, Su, Jinzhou (Joe) wrote:
> Driver should enable the CGPG feature for RLC in safe mode to
> prevent any misalignment or conflict in middle of any power
> feature entry/exit sequence.
> Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
> and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
> hysteresis value in refclk count.
>
> Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c4314e25f560..dd102cc2516a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -120,6 +120,7 @@
> #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
> #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
> #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
> +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
>
> #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
> #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
> @@ -7829,6 +7830,20 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
>
> WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> +
> + /*
> + * CGPG enablement required and the register to program the hysteresis value
> + * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
> + * in refclk count. Note that RLC FW is modified to take 16 bits from
> + * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
> + *
> + * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
> + * as part of CGPG enablement starting point.
> + */
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
> + data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
> + WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
> + }
> }
>
> static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
@ 2021-01-19 10:48 Jinzhou Su
2021-01-19 14:08 ` Huang Rui
0 siblings, 1 reply; 4+ messages in thread
From: Jinzhou Su @ 2021-01-19 10:48 UTC (permalink / raw)
To: amd-gfx; +Cc: Jinzhou Su, ray.huang
Copy from RLC MAS:
Driver should enable the CGPG feature for RLC while it is in
safe mode to prevent any misalignment or conflict while it is
in middle of any power feature entry/exit sequence. This can
be achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in refclk count.
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c4314e25f560..23a11ec40c33 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -120,6 +120,7 @@
#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
#define mmGCR_GENERAL_CNTL_Vangogh 0x1580
#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
@@ -7829,6 +7830,17 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+
+ /*
+ * CGPG enablement required and the register to program the hysteresis value
+ * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
+ * in refclk count. Note that RLC FW is modified to take 16 bits from
+ * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
+ */
+ if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
+ data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+ WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+ }
}
static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
2021-01-19 10:48 Jinzhou Su
@ 2021-01-19 14:08 ` Huang Rui
0 siblings, 0 replies; 4+ messages in thread
From: Huang Rui @ 2021-01-19 14:08 UTC (permalink / raw)
To: Su, Jinzhou (Joe); +Cc: amd-gfx@lists.freedesktop.org
On Tue, Jan 19, 2021 at 06:48:54PM +0800, Su, Jinzhou (Joe) wrote:
> Copy from RLC MAS:
Remove this line.
>
> Driver should enable the CGPG feature for RLC while it is in
> safe mode to prevent any misalignment or conflict while it is
> in middle of any power feature entry/exit sequence. This can
> be achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
> and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
> hysteresis value in refclk count.
>
> Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c4314e25f560..23a11ec40c33 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -120,6 +120,7 @@
> #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
> #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
> #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
> +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
>
> #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
> #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
> @@ -7829,6 +7830,17 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
>
> WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
> +
> + /*
> + * CGPG enablement required and the register to program the hysteresis value
> + * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
> + * in refclk count. Note that RLC FW is modified to take 16 bits from
> + * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
> + */
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
> + data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
How can you get the "0x4E20" here?
Thanks,
Ray
> + WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
> + }
> }
>
> static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
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