From: Peng Ju Zhou <PengJu.Zhou@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Subject: [PATCH v2 04/12] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c
Date: Thu, 29 Apr 2021 18:26:36 +0800 [thread overview]
Message-ID: <20210429102644.31172-4-PengJu.Zhou@amd.com> (raw)
In-Reply-To: <20210429102644.31172-1-PengJu.Zhou@amd.com>
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index d80e12b80c7e..bbd6ec2277d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -632,7 +632,9 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
if (entry->and_mask == 0xffffffff) {
tmp = entry->or_mask;
} else {
- tmp = RREG32(reg);
+ tmp = (entry->hwip == GC_HWIP) ?
+ RREG32_SOC15_IP(GC, reg) : RREG32(reg);
+
tmp &= ~(entry->and_mask);
tmp |= (entry->or_mask & entry->and_mask);
}
@@ -643,7 +645,8 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
WREG32_RLC(reg, tmp);
else
- WREG32(reg, tmp);
+ (entry->hwip == GC_HWIP) ?
+ WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
}
--
2.17.1
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next prev parent reply other threads:[~2021-04-29 10:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-29 10:26 [PATCH v2 01/12] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 02/12] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 03/12] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
2021-04-29 10:26 ` Peng Ju Zhou [this message]
2021-04-29 10:26 ` [PATCH v2 05/12] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 06/12] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 07/12] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 08/12] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 09/12] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 10/12] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 11/12] drm/amdgpu: Skip the program of GRBM_CAM* " Peng Ju Zhou
2021-04-29 10:26 ` [PATCH v2 12/12] drm/amdgpu: Refine the error report when flush tlb Peng Ju Zhou
2021-04-29 11:28 ` Christian König
2021-04-30 3:55 ` Zhou, Peng Ju
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