From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, Wenjing Liu <wenjing.liu@amd.com>,
solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
Ariel Bernstein <Eric.Bernstein@amd.com>,
wayne.lin@amd.com, mikita.lipski@amd.com,
Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
pavle.kotarac@amd.com
Subject: [PATCH 04/14] drm/amd/display: set MSA vsp/hsp to 0 for positive polarity for DP 128b/132b
Date: Fri, 12 Nov 2021 08:54:28 +0800 [thread overview]
Message-ID: <20211112005438.5505-5-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20211112005438.5505-1-Wayne.Lin@amd.com>
From: Wenjing Liu <wenjing.liu@amd.com>
[why]
There is a bug in MSA programming sequence that mistakenly set
MSA vsp/hsp to 1 for positive polarity. This is incorrect.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
.../drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
index 565f12dd179a..5065904c7833 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
@@ -358,8 +358,8 @@ static void dcn31_hpo_dp_stream_enc_set_stream_attribute(
h_width = hw_crtc_timing.h_border_left + hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right;
v_height = hw_crtc_timing.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom;
- hsp = hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 0x80 : 0;
- vsp = hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 0x80 : 0;
+ hsp = hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 0 : 0x80;
+ vsp = hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 0 : 0x80;
v_freq = hw_crtc_timing.pix_clk_100hz * 100;
/* MSA Packet Mapping to 32-bit Link Symbols - DP2 spec, section 2.7.4.1
--
2.25.1
next prev parent reply other threads:[~2021-11-12 0:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 0:54 [PATCH 00/14] DC Patches November 12, 2021 Wayne Lin
2021-11-12 0:54 ` [PATCH 01/14] drm/amd/display: Secondary display goes blank on Non DCN31 Wayne Lin
2021-11-12 0:54 ` [PATCH 02/14] drm/amd/display: Only flush delta from last command execution Wayne Lin
2021-11-12 0:54 ` [PATCH 03/14] drm/amd/display: Revert changes for MPO underflow Wayne Lin
2021-11-12 0:54 ` Wayne Lin [this message]
2021-11-12 0:54 ` [PATCH 05/14] drm/amd/display: Code change for DML isolation Wayne Lin
2021-11-12 0:54 ` [PATCH 06/14] drm/amd/display: Reset fifo after enable otg Wayne Lin
2021-11-12 0:54 ` [PATCH 07/14] drm/amd/display: Enable DSC over eDP Wayne Lin
2021-11-12 0:54 ` [PATCH 08/14] drm/amd/display: Fix eDP will flash when boot to OS Wayne Lin
2021-11-12 0:54 ` [PATCH 09/14] drm/amd/display: Visual Confirm Bar Height Adjust Wayne Lin
2021-11-12 0:54 ` [PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.92 Wayne Lin
2021-11-12 0:54 ` [PATCH 11/14] drm/amd/display: [FW Promotion] Release 0.0.93 Wayne Lin
2021-11-12 0:54 ` [PATCH 12/14] drm/amd/display: fixed the DSC power off sequence during Driver PnP Wayne Lin
2021-11-12 0:54 ` [PATCH 13/14] drm/amd/display: 3.2.162 Wayne Lin
2021-11-12 0:54 ` [PATCH 14/14] drm/amd/display: Revert "retain/release stream pointer in link enc table" Wayne Lin
2021-11-15 14:35 ` [PATCH 00/14] DC Patches November 12, 2021 Wheeler, Daniel
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