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From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Jun Lei <Jun.Lei@amd.com>,
	Anthony Koo <Anthony.Koo@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, "Xu, Jinze" <JinZe.Xu@amd.com>,
	Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com,
	Aurabindo.Pillai@amd.com, wayne.lin@amd.com,
	mikita.lipski@amd.com, Bhawanpreet.Lakha@amd.com,
	agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH 06/14] drm/amd/display: Reset fifo after enable otg
Date: Fri, 12 Nov 2021 08:54:30 +0800	[thread overview]
Message-ID: <20211112005438.5505-7-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20211112005438.5505-1-Wayne.Lin@amd.com>

From: "Xu, Jinze" <JinZe.Xu@amd.com>

[Why]
In fast boot sequence, when change dispclk, otg is disabled but digfe
is enabled. This may cause dig fifo error.

[How]
Reset dig fifo after enable otg.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com>
---
 .../amd/display/dc/dce110/dce110_hw_sequencer.c   |  5 +++++
 .../amd/display/dc/dcn10/dcn10_stream_encoder.c   | 15 +++++++++++++++
 .../amd/display/dc/dcn10/dcn10_stream_encoder.h   |  3 +++
 .../amd/display/dc/dcn20/dcn20_stream_encoder.c   |  2 ++
 .../display/dc/dcn30/dcn30_dio_stream_encoder.c   |  2 ++
 .../drm/amd/display/dc/inc/hw/stream_encoder.h    |  4 ++++
 6 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e7e2aa46218d..665cf58b0724 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1602,6 +1602,11 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 			pipe_ctx->stream_res.stream_enc,
 			pipe_ctx->stream_res.tg->inst);
 
+	if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
+		pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
+		pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
+			pipe_ctx->stream_res.stream_enc);
+
 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
 		dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index b0c08ee6bc2c..bf4436d7aaab 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -902,6 +902,19 @@ void enc1_stream_encoder_stop_dp_info_packets(
 
 }
 
+void enc1_stream_encoder_reset_fifo(
+	struct stream_encoder *enc)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+	/* set DIG_START to 0x1 to reset FIFO */
+	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
+	udelay(100);
+
+	/* write 0 to take the FIFO out of reset */
+	REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
+}
+
 void enc1_stream_encoder_dp_blank(
 	struct dc_link *link,
 	struct stream_encoder *enc)
@@ -1587,6 +1600,8 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
 		enc1_stream_encoder_send_immediate_sdp_message,
 	.stop_dp_info_packets =
 		enc1_stream_encoder_stop_dp_info_packets,
+	.reset_fifo =
+		enc1_stream_encoder_reset_fifo,
 	.dp_blank =
 		enc1_stream_encoder_dp_blank,
 	.dp_unblank =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 687d7e4bf7ca..a146a41f68e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -626,6 +626,9 @@ void enc1_stream_encoder_send_immediate_sdp_message(
 void enc1_stream_encoder_stop_dp_info_packets(
 	struct stream_encoder *enc);
 
+void enc1_stream_encoder_reset_fifo(
+	struct stream_encoder *enc);
+
 void enc1_stream_encoder_dp_blank(
 	struct dc_link *link,
 	struct stream_encoder *enc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index aab25ca8343a..8a70f92795c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -593,6 +593,8 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
 		enc1_stream_encoder_send_immediate_sdp_message,
 	.stop_dp_info_packets =
 		enc1_stream_encoder_stop_dp_info_packets,
+	.reset_fifo =
+		enc1_stream_encoder_reset_fifo,
 	.dp_blank =
 		enc1_stream_encoder_dp_blank,
 	.dp_unblank =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index ebd9c35c914f..7aa9aaf5db4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -805,6 +805,8 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
 		enc3_stream_encoder_update_dp_info_packets,
 	.stop_dp_info_packets =
 		enc1_stream_encoder_stop_dp_info_packets,
+	.reset_fifo =
+		enc1_stream_encoder_reset_fifo,
 	.dp_blank =
 		enc1_stream_encoder_dp_blank,
 	.dp_unblank =
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index c88e113b94d1..073f8b667eff 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -164,6 +164,10 @@ struct stream_encoder_funcs {
 	void (*stop_dp_info_packets)(
 		struct stream_encoder *enc);
 
+	void (*reset_fifo)(
+		struct stream_encoder *enc
+	);
+
 	void (*dp_blank)(
 		struct dc_link *link,
 		struct stream_encoder *enc);
-- 
2.25.1


  parent reply	other threads:[~2021-11-12  0:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-12  0:54 [PATCH 00/14] DC Patches November 12, 2021 Wayne Lin
2021-11-12  0:54 ` [PATCH 01/14] drm/amd/display: Secondary display goes blank on Non DCN31 Wayne Lin
2021-11-12  0:54 ` [PATCH 02/14] drm/amd/display: Only flush delta from last command execution Wayne Lin
2021-11-12  0:54 ` [PATCH 03/14] drm/amd/display: Revert changes for MPO underflow Wayne Lin
2021-11-12  0:54 ` [PATCH 04/14] drm/amd/display: set MSA vsp/hsp to 0 for positive polarity for DP 128b/132b Wayne Lin
2021-11-12  0:54 ` [PATCH 05/14] drm/amd/display: Code change for DML isolation Wayne Lin
2021-11-12  0:54 ` Wayne Lin [this message]
2021-11-12  0:54 ` [PATCH 07/14] drm/amd/display: Enable DSC over eDP Wayne Lin
2021-11-12  0:54 ` [PATCH 08/14] drm/amd/display: Fix eDP will flash when boot to OS Wayne Lin
2021-11-12  0:54 ` [PATCH 09/14] drm/amd/display: Visual Confirm Bar Height Adjust Wayne Lin
2021-11-12  0:54 ` [PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.92 Wayne Lin
2021-11-12  0:54 ` [PATCH 11/14] drm/amd/display: [FW Promotion] Release 0.0.93 Wayne Lin
2021-11-12  0:54 ` [PATCH 12/14] drm/amd/display: fixed the DSC power off sequence during Driver PnP Wayne Lin
2021-11-12  0:54 ` [PATCH 13/14] drm/amd/display: 3.2.162 Wayne Lin
2021-11-12  0:54 ` [PATCH 14/14] drm/amd/display: Revert "retain/release stream pointer in link enc table" Wayne Lin
2021-11-15 14:35 ` [PATCH 00/14] DC Patches November 12, 2021 Wheeler, Daniel

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