* [PATCH 1/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for SMU v13.0.4
@ 2023-05-22 10:08 Tim Huang
2023-05-22 10:08 ` [PATCH 2/4] amd/pm/swsmu: reverse mclk clocks levels for SMU v13.0.5 Tim Huang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Tim Huang @ 2023-05-22 10:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan1.zhang, Tim Huang
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels that from
the DFPstateTable are given the reversed orders by PMFW. Like the
memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 0a0a7debb3ae..46a8a366f287 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -478,7 +478,7 @@ static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu,
static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
- int i, size = 0, ret = 0;
+ int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t min, max;
@@ -512,7 +512,8 @@ static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
break;
for (i = 0; i < count; i++) {
- ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, i, &value);
+ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
+ ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value);
if (ret)
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] amd/pm/swsmu: reverse mclk clocks levels for SMU v13.0.5
2023-05-22 10:08 [PATCH 1/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for SMU v13.0.4 Tim Huang
@ 2023-05-22 10:08 ` Tim Huang
2023-05-22 10:08 ` [PATCH 3/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for yellow carp Tim Huang
2023-05-22 10:08 ` [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh Tim Huang
2 siblings, 0 replies; 6+ messages in thread
From: Tim Huang @ 2023-05-22 10:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan1.zhang, Tim Huang
This patch reverses the DPM clocks levels output of pp_dpm_mclk.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels that from
the DFPstateTable are given the reversed orders by PMFW. Like the
memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 165b2470b017..7c3ac535f68a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -866,7 +866,7 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
- int i, size = 0, ret = 0;
+ int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t min = 0, max = 0;
@@ -898,7 +898,8 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
goto print_clk_out;
for (i = 0; i < count; i++) {
- ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, i, &value);
+ idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i;
+ ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);
if (ret)
goto print_clk_out;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for yellow carp
2023-05-22 10:08 [PATCH 1/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for SMU v13.0.4 Tim Huang
2023-05-22 10:08 ` [PATCH 2/4] amd/pm/swsmu: reverse mclk clocks levels for SMU v13.0.5 Tim Huang
@ 2023-05-22 10:08 ` Tim Huang
2023-05-22 10:08 ` [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh Tim Huang
2 siblings, 0 replies; 6+ messages in thread
From: Tim Huang @ 2023-05-22 10:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan1.zhang, Tim Huang
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels that from
the DFPstateTable are given the reversed orders by PMFW. Like the
memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index ac5fcca0e47f..a92da336ecec 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -1000,7 +1000,7 @@ static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
static int yellow_carp_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
- int i, size = 0, ret = 0;
+ int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
uint32_t min, max;
@@ -1033,7 +1033,8 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
goto print_clk_out;
for (i = 0; i < count; i++) {
- ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value);
+ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
+ ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value);
if (ret)
goto print_clk_out;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh
2023-05-22 10:08 [PATCH 1/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for SMU v13.0.4 Tim Huang
2023-05-22 10:08 ` [PATCH 2/4] amd/pm/swsmu: reverse mclk clocks levels for SMU v13.0.5 Tim Huang
2023-05-22 10:08 ` [PATCH 3/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for yellow carp Tim Huang
@ 2023-05-22 10:08 ` Tim Huang
2023-05-22 13:19 ` Alex Deucher
2 siblings, 1 reply; 6+ messages in thread
From: Tim Huang @ 2023-05-22 10:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan1.zhang, Tim Huang
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels that from
the DFPstateTable are given the reversed orders by PMFW. Like the
memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 7433dcaa16e0..067b4e0b026c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -582,7 +582,7 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_legacy_t metrics;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- int i, size = 0, ret = 0;
+ int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
@@ -656,7 +656,8 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
case SMU_MCLK:
case SMU_FCLK:
for (i = 0; i < count; i++) {
- ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
+ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
+ ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
if (ret)
return ret;
if (!value)
@@ -683,7 +684,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
DpmClocks_t *clk_table = smu->smu_table.clocks_table;
SmuMetrics_t metrics;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
- int i, size = 0, ret = 0;
+ int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
uint32_t min, max;
@@ -765,7 +766,8 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
case SMU_MCLK:
case SMU_FCLK:
for (i = 0; i < count; i++) {
- ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
+ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
+ ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
if (ret)
return ret;
if (!value)
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh
2023-05-22 10:08 ` [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh Tim Huang
@ 2023-05-22 13:19 ` Alex Deucher
2023-05-22 14:42 ` Huang, Tim
0 siblings, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2023-05-22 13:19 UTC (permalink / raw)
To: Tim Huang; +Cc: Alexander.Deucher, Yifan1.zhang, amd-gfx
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Does Renoir need a similar fix?
Alex
On Mon, May 22, 2023 at 6:10 AM Tim Huang <Tim.Huang@amd.com> wrote:
>
> This patch reverses the DPM clocks levels output of pp_dpm_mclk
> and pp_dpm_fclk.
>
> On dGPUs and older APUs we expose the levels from lowest clocks
> to highest clocks. But for some APUs, the clocks levels that from
> the DFPstateTable are given the reversed orders by PMFW. Like the
> memory DPM clocks that are exposed by pp_dpm_mclk.
>
> It's not intuitive that they are reversed on these APUs. All tools
> and software that talks to the driver then has to know different ways
> to interpret the data depending on the asic.
>
> So we need to reverse them to expose the clocks levels from the
> driver consistently.
>
> Signed-off-by: Tim Huang <Tim.Huang@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 7433dcaa16e0..067b4e0b026c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -582,7 +582,7 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_legacy_t metrics;
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> - int i, size = 0, ret = 0;
> + int i, idx, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
>
> @@ -656,7 +656,8 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
> case SMU_MCLK:
> case SMU_FCLK:
> for (i = 0; i < count; i++) {
> - ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
> + idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
> + ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
> if (ret)
> return ret;
> if (!value)
> @@ -683,7 +684,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> - int i, size = 0, ret = 0;
> + int i, idx, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> uint32_t min, max;
> @@ -765,7 +766,8 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> case SMU_MCLK:
> case SMU_FCLK:
> for (i = 0; i < count; i++) {
> - ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
> + idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
> + ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
> if (ret)
> return ret;
> if (!value)
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh
2023-05-22 13:19 ` Alex Deucher
@ 2023-05-22 14:42 ` Huang, Tim
0 siblings, 0 replies; 6+ messages in thread
From: Huang, Tim @ 2023-05-22 14:42 UTC (permalink / raw)
To: Alex Deucher
Cc: Deucher, Alexander, Zhang, Yifan, amd-gfx@lists.freedesktop.org
[-- Attachment #1: Type: text/plain, Size: 3976 bytes --]
[AMD Official Use Only - General]
Thanks Alex.
Renoir didn't use the DFPstateTable but it needs to reverse the clocks levels as well.
Will send out a new patch for Renoir.
Best Regards,
Tim
________________________________
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Monday, May 22, 2023 9:19 PM
To: Huang, Tim <Tim.Huang@amd.com>
Cc: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>
Subject: Re: [PATCH 4/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for vangogh
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Does Renoir need a similar fix?
Alex
On Mon, May 22, 2023 at 6:10 AM Tim Huang <Tim.Huang@amd.com> wrote:
>
> This patch reverses the DPM clocks levels output of pp_dpm_mclk
> and pp_dpm_fclk.
>
> On dGPUs and older APUs we expose the levels from lowest clocks
> to highest clocks. But for some APUs, the clocks levels that from
> the DFPstateTable are given the reversed orders by PMFW. Like the
> memory DPM clocks that are exposed by pp_dpm_mclk.
>
> It's not intuitive that they are reversed on these APUs. All tools
> and software that talks to the driver then has to know different ways
> to interpret the data depending on the asic.
>
> So we need to reverse them to expose the clocks levels from the
> driver consistently.
>
> Signed-off-by: Tim Huang <Tim.Huang@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 7433dcaa16e0..067b4e0b026c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -582,7 +582,7 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_legacy_t metrics;
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> - int i, size = 0, ret = 0;
> + int i, idx, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
>
> @@ -656,7 +656,8 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
> case SMU_MCLK:
> case SMU_FCLK:
> for (i = 0; i < count; i++) {
> - ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
> + idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
> + ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
> if (ret)
> return ret;
> if (!value)
> @@ -683,7 +684,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> DpmClocks_t *clk_table = smu->smu_table.clocks_table;
> SmuMetrics_t metrics;
> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> - int i, size = 0, ret = 0;
> + int i, idx, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> uint32_t min, max;
> @@ -765,7 +766,8 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
> case SMU_MCLK:
> case SMU_FCLK:
> for (i = 0; i < count; i++) {
> - ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
> + idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
> + ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
> if (ret)
> return ret;
> if (!value)
> --
> 2.34.1
>
[-- Attachment #2: Type: text/html, Size: 8906 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-22 14:42 UTC | newest]
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2023-05-22 10:08 [PATCH 1/4] amd/pm/swsmu: reverse mclk and fclk clocks levels for SMU v13.0.4 Tim Huang
2023-05-22 10:08 ` [PATCH 2/4] amd/pm/swsmu: reverse mclk clocks levels for SMU v13.0.5 Tim Huang
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