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From: <Roman.Li@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Daniel Wheeler <daniel.wheeler@amd.com>, <Harry.Wentland@amd.com>,
	<Sunpeng.Li@amd.com>, <Rodrigo.Siqueira@amd.com>,
	<Aurabindo.Pillai@amd.com>,  <roman.li@amd.com>,
	<wayne.lin@amd.com>, <solomon.chiu@amd.com>,
	<agustin.gutierrez@amd.com>, <hamza.mahfooz@amd.com>,
	Hersen Wu <hersenxs.wu@amd.com>
Subject: [PATCH 08/43] drm/amd/display: FEC overhead should be checked once for mst slot nums
Date: Thu, 28 Mar 2024 15:50:12 -0400	[thread overview]
Message-ID: <20240328195047.2843715-9-Roman.Li@amd.com> (raw)
In-Reply-To: <20240328195047.2843715-1-Roman.Li@amd.com>

From: Hersen Wu <hersenxs.wu@amd.com>

[Why] Mst slot nums equals to pbn / pbn_div.

Today, pbn_div refers to dm_mst_get_pbn_divider ->
dc_link_bandwidth_kbps. In dp_link_bandwidth_kbps,
which includes effect of FEC overhead already. As
result, we should not include effect of FEC overhead
again while calculating pbn by kpbs_to_peak_pbn
(stream_kbps).

[How] Include FEC overhead within dp_link_bandwidth_kbps.
Remove FEC overhead from kbps_to_peak_pbn.

Reviewed-by: Wayne Lin <wayne.lin@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 37 +++++--------------
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  3 --
 2 files changed, 10 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ad3170b72a47..0b03e659fdf3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -791,25 +791,12 @@ struct dsc_mst_fairness_params {
 	struct amdgpu_dm_connector *aconnector;
 };
 
-static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
-{
-	u8 link_coding_cap;
-	uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
-
-	link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
-	if (link_coding_cap == DP_128b_132b_ENCODING)
-		fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
-
-	return fec_overhead_multiplier_x1000;
-}
-
-static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
+static int kbps_to_peak_pbn(int kbps)
 {
 	u64 peak_kbps = kbps;
 
 	peak_kbps *= 1006;
-	peak_kbps *= fec_overhead_multiplier_x1000;
-	peak_kbps = div_u64(peak_kbps, 1000 * 1000);
+	peak_kbps = div_u64(peak_kbps, 1000);
 	return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 }
 
@@ -910,12 +897,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state,
 	int link_timeslots_used;
 	int fair_pbn_alloc;
 	int ret = 0;
-	uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
 
 	for (i = 0; i < count; i++) {
 		if (vars[i + k].dsc_enabled) {
 			initial_slack[i] =
-			kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
+			kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn;
 			bpp_increased[i] = false;
 			remaining_to_increase += 1;
 		} else {
@@ -1011,7 +997,6 @@ static int try_disable_dsc(struct drm_atomic_state *state,
 	int next_index;
 	int remaining_to_try = 0;
 	int ret;
-	uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
 
 	for (i = 0; i < count; i++) {
 		if (vars[i + k].dsc_enabled
@@ -1041,7 +1026,7 @@ static int try_disable_dsc(struct drm_atomic_state *state,
 		if (next_index == -1)
 			break;
 
-		vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
+		vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 		ret = drm_dp_atomic_find_time_slots(state,
 						    params[next_index].port->mgr,
 						    params[next_index].port,
@@ -1054,7 +1039,8 @@ static int try_disable_dsc(struct drm_atomic_state *state,
 			vars[next_index].dsc_enabled = false;
 			vars[next_index].bpp_x16 = 0;
 		} else {
-			vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000);
+			vars[next_index].pbn = kbps_to_peak_pbn(
+				params[next_index].bw_range.max_kbps);
 			ret = drm_dp_atomic_find_time_slots(state,
 							    params[next_index].port->mgr,
 							    params[next_index].port,
@@ -1083,7 +1069,6 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 	int count = 0;
 	int i, k, ret;
 	bool debugfs_overwrite = false;
-	uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
 
 	memset(params, 0, sizeof(params));
 
@@ -1148,7 +1133,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 	/* Try no compression */
 	for (i = 0; i < count; i++) {
 		vars[i + k].aconnector = params[i].aconnector;
-		vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
+		vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 		vars[i + k].dsc_enabled = false;
 		vars[i + k].bpp_x16 = 0;
 		ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
@@ -1167,7 +1152,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 	/* Try max compression */
 	for (i = 0; i < count; i++) {
 		if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
-			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
+			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 			vars[i + k].dsc_enabled = true;
 			vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 			ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
@@ -1175,7 +1160,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 			if (ret < 0)
 				return ret;
 		} else {
-			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
+			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 			vars[i + k].dsc_enabled = false;
 			vars[i + k].bpp_x16 = 0;
 			ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
@@ -1656,13 +1641,11 @@ enum dc_status dm_dp_mst_is_port_support_mode(
 		 */
 		int pbn_div, slot_num, max_slot_num;
 		enum dc_link_encoding_format link_encoding;
-		uint16_t fec_overhead_multiplier_x1000 =
-			get_fec_overhead_multiplier(stream->link);
 		uint32_t stream_kbps =
 			dc_bandwidth_in_kbps_from_timing(&stream->timing,
 				dc_link_get_highest_encoding_format(stream->link));
 
-		pbn = kbps_to_peak_pbn(stream_kbps, fec_overhead_multiplier_x1000);
+		pbn = kbps_to_peak_pbn(stream_kbps);
 		pbn_div = dm_mst_get_pbn_divider(stream->link);
 		slot_num = DIV_ROUND_UP(pbn, pbn_div);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 37c820ab0fdb..fa84d34b7373 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -46,9 +46,6 @@
 #define SYNAPTICS_CASCADED_HUB_ID  0x5A
 #define IS_SYNAPTICS_CASCADED_PANAMERA(devName, data) ((IS_SYNAPTICS_PANAMERA(devName) && ((int)data[2] == SYNAPTICS_CASCADED_HUB_ID)) ? 1 : 0)
 
-#define PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B	1031
-#define PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B	1000
-
 enum mst_msg_ready_type {
 	NONE_MSG_RDY_EVENT = 0,
 	DOWN_REP_MSG_RDY_EVENT = 1,
-- 
2.34.1


  parent reply	other threads:[~2024-03-28 19:51 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-28 19:50 [PATCH 00/43] DC Patches Apr 1, 2024 Roman.Li
2024-03-28 19:50 ` [PATCH 01/43] drm/amd/display: Fix compiler redefinition warnings for certain configs Roman.Li
2024-04-01 13:07   ` Wheeler, Daniel
2024-03-28 19:50 ` [PATCH 02/43] drm/amd/display: Add timing pixel encoding for mst mode validation Roman.Li
2024-03-28 19:50 ` [PATCH 03/43] drm/amd/display: fix underflow in some two display subvp/non-subvp configs Roman.Li
2024-03-28 19:50 ` [PATCH 04/43] drm/amd/display: optimize dml2 pipe resource allocation order Roman.Li
2024-03-28 19:50 ` [PATCH 05/43] drm/amd/display: Toggle additional RCO options in DCN35 Roman.Li
2024-03-28 19:50 ` [PATCH 06/43] drm/amd/display: Decouple dcn35 and dcn351 dmub firmware Roman.Li
2024-03-28 19:50 ` [PATCH 07/43] drm/amd/display: Expand supported Replay residency mode Roman.Li
2024-03-28 19:50 ` Roman.Li [this message]
2024-07-18  7:09   ` [PATCH 08/43] drm/amd/display: FEC overhead should be checked once for mst slot nums Jiri Slaby
2024-07-30  6:00     ` Lin, Wayne
2024-07-31  6:47       ` Jiri Slaby
2024-03-28 19:50 ` [PATCH 09/43] drm/amd/display: handle invalid connector indices Roman.Li
2024-03-28 19:50 ` [PATCH 10/43] drm/amd/display: Add dmub additional interface support for FAMS Roman.Li
2024-03-28 19:50 ` [PATCH 11/43] drm/amd/display: update pipe topology log to support subvp Roman.Li
2024-03-28 19:50 ` [PATCH 12/43] drm/amd/display: Enable DTBCLK DTO earlier in the sequence Roman.Li
2024-03-28 19:50 ` [PATCH 13/43] drm/amd/display: Add dummy interface for tracing DCN32 SMU messages Roman.Li
2024-03-28 19:50 ` [PATCH 14/43] drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35 Roman.Li
2024-03-28 19:50 ` [PATCH 15/43] drm/amd/display: Allow HPO PG for DCN35 Roman.Li
2024-03-28 19:50 ` [PATCH 16/43] drm/amd/display: Skip on writeback when it's not applicable Roman.Li
2024-03-28 19:50 ` [PATCH 17/43] drm/amd/display: Add OTG check for set AV mute Roman.Li
2024-03-28 19:50 ` [PATCH 18/43] drm/amd/display: Add extra logging for HUBP and OTG Roman.Li
2024-03-28 19:50 ` [PATCH 19/43] drm/amd/display: Disable Z8 minimum stutter period check for DCN35 Roman.Li
2024-03-28 19:50 ` [PATCH 20/43] drm/amd/display: add root clock control function pointer to fix display corruption Roman.Li
2024-03-28 19:50 ` [PATCH 21/43] drm/amd/display: Add extra DMUB logging to track message timeout Roman.Li
2024-03-28 19:50 ` [PATCH 22/43] drm/amd/display: remove context->dml2 dependency from DML21 wrapper Roman.Li
2024-03-28 19:50 ` [PATCH 23/43] drm/amd/display: Add handling for DC power mode Roman.Li
2024-03-28 19:50 ` [PATCH 24/43] drm/amd/display: move build test pattern params as part of pipe resource update for odm Roman.Li
2024-03-28 19:50 ` [PATCH 25/43] drm/amd/display: Fix compiler warnings on high compiler warning levels Roman.Li
2024-03-28 19:50 ` [PATCH 26/43] drm/amd/display: Allow RCG for Static Screen + LVP for DCN35 Roman.Li
2024-03-28 19:50 ` [PATCH 27/43] drm/amd/display: 3.2.279 Roman.Li
2024-03-28 19:50 ` [PATCH 28/43] drm/amd/display: Initialize DP ref clk with the correct clock Roman.Li
2024-03-28 19:50 ` [PATCH 29/43] drm/amd/display: Set alpha enable to 0 for some specific formats Roman.Li
2024-03-28 19:50 ` [PATCH 30/43] drm/amd/display: Enable cur_rom_en even if cursor degamma is not enabled Roman.Li
2024-04-01 13:40   ` Melissa Wen
2024-04-01 13:52     ` Harry Wentland
2024-03-28 19:50 ` [PATCH 31/43] drm/amd/display: Add some missing debug registers Roman.Li
2024-03-28 19:50 ` [PATCH 32/43] drm/amd/display: Update DSC compute parameter calculation Roman.Li
2024-03-28 19:50 ` [PATCH 33/43] drm/amd/display: Drop legacy code Roman.Li
2024-03-28 19:50 ` [PATCH 34/43] drm/amd/display: Add missing registers Roman.Li
2024-03-28 19:50 ` [PATCH 35/43] drm/amd/display: Remove redundant RESERVE0 and RESERVE1 Roman.Li
2024-03-28 19:50 ` [PATCH 36/43] drm/amd/display: Add missing SFB and OPP_SF Roman.Li
2024-03-28 19:50 ` [PATCH 37/43] drm/amd/display: Initialize debug variable data Roman.Li
2024-03-28 19:50 ` [PATCH 38/43] drm/amd/display: Fix MPCC DTN logging Roman.Li
2024-04-01 13:30   ` Melissa Wen
2024-03-28 19:50 ` [PATCH 39/43] drm/amd/display: Add WBSCL ram coefficient for writeback Roman.Li
2024-03-28 19:50 ` [PATCH 40/43] drm/amd/display: Add code comments clock and encode code Roman.Li
2024-03-28 19:50 ` [PATCH 41/43] drm/amd/display: Includes adjustments Roman.Li
2024-03-28 19:50 ` [PATCH 42/43] drm/amd/display: Add color logs for dcn20 Roman.Li
2024-03-28 19:50 ` [PATCH 43/43] drm/amd/display: Enable FGCG for DCN351 Roman.Li
2024-04-01 13:21 ` [PATCH 00/43] DC Patches Apr 1, 2024 Wheeler, Daniel

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