* [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr @ 2024-04-28 8:45 Tim Huang 2024-04-28 8:45 ` [PATCH 2/2] drm/amd/pm: fix uninitialized variable warnings for vangogh_ppt Tim Huang 2024-04-30 3:27 ` [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Huang, Tim 0 siblings, 2 replies; 4+ messages in thread From: Tim Huang @ 2024-04-28 8:45 UTC (permalink / raw) To: amd-gfx; +Cc: Alexander.Deucher, christian.koenig, Tim Huang Clear warnings that using uninitialized variable when fails to get the valid value from SMU. Signed-off-by: Tim Huang <Tim.Huang@amd.com> --- .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 46 ++++++++++++++----- .../amd/pm/powerplay/smumgr/vega10_smumgr.c | 6 ++- 2 files changed, 39 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index 9f5bd998c6bf..488ad9de4694 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -354,13 +354,13 @@ static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) return 0; } -static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) +static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = hwmgr->backend; - int i; uint32_t sub_vendor_id, hw_revision; uint32_t top32, bottom32; struct amdgpu_device *adev = hwmgr->adev; + int ret, i; vega10_initialize_power_tune_defaults(hwmgr); @@ -485,9 +485,12 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) if (data->registry_data.vr0hot_enabled) data->smu_features[GNLD_VR0HOT].supported = true; - smum_send_msg_to_smc(hwmgr, + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version); + if (ret) + return ret; + /* ACG firmware has major version 5 */ if ((hwmgr->smu_version & 0xff000000) == 0x5000000) data->smu_features[GNLD_ACG].supported = true; @@ -505,10 +508,16 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->smu_features[GNLD_PCC_LIMIT].supported = true; /* Get the SN to turn into a Unique ID */ - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); + if (ret) + return ret; + + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); + if (ret) + return ret; adev->unique_id = ((uint64_t)bottom32 << 32) | top32; + return 0; } #ifdef PPLIB_VEGA10_EVV_SUPPORT @@ -882,7 +891,9 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) vega10_set_features_platform_caps(hwmgr); - vega10_init_dpm_defaults(hwmgr); + result = vega10_init_dpm_defaults(hwmgr); + if (result) + return result; #ifdef PPLIB_VEGA10_EVV_SUPPORT /* Get leakage voltage based on leakage ID. */ @@ -3900,11 +3911,14 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) { uint32_t value; + int ret; if (!query) return -EINVAL; - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); + if (ret) + return ret; /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */ *query = value << 8; @@ -4800,14 +4814,16 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; PPTable_t *pptable = &(data->smc_state_table.pp_table); - int i, now, size = 0, count = 0; + int i, ret, now, size = 0, count = 0; switch (type) { case PP_SCLK: if (data->registry_data.sclk_dpm_key_disabled) break; - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); + if (ret) + break; if (hwmgr->pp_one_vf && (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) @@ -4823,7 +4839,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, if (data->registry_data.mclk_dpm_key_disabled) break; - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); + if (ret) + break; for (i = 0; i < mclk_table->count; i++) size += sprintf(buf + size, "%d: %uMhz %s\n", @@ -4834,7 +4852,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, if (data->registry_data.socclk_dpm_key_disabled) break; - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); + if (ret) + break; for (i = 0; i < soc_table->count; i++) size += sprintf(buf + size, "%d: %uMhz %s\n", @@ -4845,8 +4865,10 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, if (data->registry_data.dcefclk_dpm_key_disabled) break; - smum_send_msg_to_smc_with_parameter(hwmgr, + ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now); + if (ret) + break; for (i = 0; i < dcef_table->count; i++) size += sprintf(buf + size, "%d: %uMhz %s\n", diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c index a70d73896649..f9c0f117725d 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c @@ -130,13 +130,17 @@ int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr, uint64_t *features_enabled) { uint32_t enabled_features; + int ret; if (features_enabled == NULL) return -EINVAL; - smum_send_msg_to_smc(hwmgr, + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures, &enabled_features); + if (ret) + return ret; + *features_enabled = enabled_features; return 0; -- 2.39.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amd/pm: fix uninitialized variable warnings for vangogh_ppt 2024-04-28 8:45 [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Tim Huang @ 2024-04-28 8:45 ` Tim Huang 2024-04-30 3:27 ` [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Huang, Tim 1 sibling, 0 replies; 4+ messages in thread From: Tim Huang @ 2024-04-28 8:45 UTC (permalink / raw) To: amd-gfx; +Cc: Alexander.Deucher, christian.koenig, Tim Huang 1. Fix a issue that using uninitialized mask to get the ultimate frequency. 2. Check return of smu_cmn_send_smc_msg_with_param to avoid using uninitialized variable residency. Signed-off-by: Tim Huang <Tim.Huang@amd.com> --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 29295941aca9..b40cb4e255e9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -976,6 +976,18 @@ static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu, } } if (min) { + ret = vangogh_get_profiling_clk_mask(smu, + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK, + NULL, + NULL, + &mclk_mask, + &fclk_mask, + &soc_mask); + if (ret) + goto failed; + + vclk_mask = dclk_mask = 0; + switch (clk_type) { case SMU_UCLK: case SMU_MCLK: @@ -2450,6 +2462,8 @@ static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start) ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency, start, &residency); + if (ret) + return ret; if (!start) adev->gfx.gfx_off_residency = residency; -- 2.39.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr 2024-04-28 8:45 [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Tim Huang 2024-04-28 8:45 ` [PATCH 2/2] drm/amd/pm: fix uninitialized variable warnings for vangogh_ppt Tim Huang @ 2024-04-30 3:27 ` Huang, Tim 2024-04-30 4:12 ` Wang, Yang(Kevin) 1 sibling, 1 reply; 4+ messages in thread From: Huang, Tim @ 2024-04-30 3:27 UTC (permalink / raw) To: amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander, Koenig, Christian [AMD Official Use Only - General] Ping ... > -----Original Message----- > From: Huang, Tim <Tim.Huang@amd.com> > Sent: Sunday, April 28, 2024 4:45 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian > <Christian.Koenig@amd.com>; Huang, Tim <Tim.Huang@amd.com> > Subject: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for > vega10_hwmgr > > Clear warnings that using uninitialized variable when fails to get the valid value > from SMU. > > Signed-off-by: Tim Huang <Tim.Huang@amd.com> > --- > .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 46 ++++++++++++++----- > .../amd/pm/powerplay/smumgr/vega10_smumgr.c | 6 ++- > 2 files changed, 39 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > index 9f5bd998c6bf..488ad9de4694 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > @@ -354,13 +354,13 @@ static int vega10_odn_initial_default_setting(struct > pp_hwmgr *hwmgr) > return 0; > } > > -static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) > +static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) > { > struct vega10_hwmgr *data = hwmgr->backend; > - int i; > uint32_t sub_vendor_id, hw_revision; > uint32_t top32, bottom32; > struct amdgpu_device *adev = hwmgr->adev; > + int ret, i; > > vega10_initialize_power_tune_defaults(hwmgr); > > @@ -485,9 +485,12 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr > *hwmgr) > if (data->registry_data.vr0hot_enabled) > data->smu_features[GNLD_VR0HOT].supported = true; > > - smum_send_msg_to_smc(hwmgr, > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetSmuVersion, > &hwmgr->smu_version); > + if (ret) > + return ret; > + > /* ACG firmware has major version 5 */ > if ((hwmgr->smu_version & 0xff000000) == 0x5000000) > data->smu_features[GNLD_ACG].supported = true; @@ -505,10 > +508,16 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) > data->smu_features[GNLD_PCC_LIMIT].supported = true; > > /* Get the SN to turn into a Unique ID */ > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, > &top32); > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_ReadSerialNumBottom32, &bottom32); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_ReadSerialNumTop32, &top32); > + if (ret) > + return ret; > + > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_ReadSerialNumBottom32, &bottom32); > + if (ret) > + return ret; > > adev->unique_id = ((uint64_t)bottom32 << 32) | top32; > + return 0; > } > > #ifdef PPLIB_VEGA10_EVV_SUPPORT > @@ -882,7 +891,9 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr > *hwmgr) > > vega10_set_features_platform_caps(hwmgr); > > - vega10_init_dpm_defaults(hwmgr); > + result = vega10_init_dpm_defaults(hwmgr); > + if (result) > + return result; > > #ifdef PPLIB_VEGA10_EVV_SUPPORT > /* Get leakage voltage based on leakage ID. */ @@ -3900,11 +3911,14 > @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, > uint32_t *query) > { > uint32_t value; > + int ret; > > if (!query) > return -EINVAL; > > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, > &value); > + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, > &value); > + if (ret) > + return ret; > > /* SMC returning actual watts, keep consistent with legacy asics, low 8 > bit as 8 fractional bits */ > *query = value << 8; > @@ -4800,14 +4814,16 @@ static int vega10_print_clock_levels(struct > pp_hwmgr *hwmgr, > uint32_t gen_speed, lane_width, current_gen_speed, > current_lane_width; > PPTable_t *pptable = &(data->smc_state_table.pp_table); > > - int i, now, size = 0, count = 0; > + int i, ret, now, size = 0, count = 0; > > switch (type) { > case PP_SCLK: > if (data->registry_data.sclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentGfxclkIndex, &now); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentGfxclkIndex, &now); > + if (ret) > + break; > > if (hwmgr->pp_one_vf && > (hwmgr->dpm_level == > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) > @@ -4823,7 +4839,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr > *hwmgr, > if (data->registry_data.mclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentUclkIndex, &now); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentUclkIndex, &now); > + if (ret) > + break; > > for (i = 0; i < mclk_table->count; i++) > size += sprintf(buf + size, "%d: %uMhz %s\n", @@ - > 4834,7 +4852,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr > *hwmgr, > if (data->registry_data.socclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentSocclkIndex, &now); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentSocclkIndex, &now); > + if (ret) > + break; > > for (i = 0; i < soc_table->count; i++) > size += sprintf(buf + size, "%d: %uMhz %s\n", @@ - > 4845,8 +4865,10 @@ static int vega10_print_clock_levels(struct pp_hwmgr > *hwmgr, > if (data->registry_data.dcefclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc_with_parameter(hwmgr, > + ret = smum_send_msg_to_smc_with_parameter(hwmgr, > PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, > &now); > + if (ret) > + break; > > for (i = 0; i < dcef_table->count; i++) > size += sprintf(buf + size, "%d: %uMhz %s\n", diff --git > a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > index a70d73896649..f9c0f117725d 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > @@ -130,13 +130,17 @@ int vega10_get_enabled_smc_features(struct > pp_hwmgr *hwmgr, > uint64_t *features_enabled) > { > uint32_t enabled_features; > + int ret; > > if (features_enabled == NULL) > return -EINVAL; > > - smum_send_msg_to_smc(hwmgr, > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetEnabledSmuFeatures, > &enabled_features); > + if (ret) > + return ret; > + > *features_enabled = enabled_features; > > return 0; > -- > 2.39.2 ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr 2024-04-30 3:27 ` [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Huang, Tim @ 2024-04-30 4:12 ` Wang, Yang(Kevin) 0 siblings, 0 replies; 4+ messages in thread From: Wang, Yang(Kevin) @ 2024-04-30 4:12 UTC (permalink / raw) To: Huang, Tim, amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander, Koenig, Christian [AMD Official Use Only - General] Series is Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Best Regards, Kevin -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang, Tim Sent: Tuesday, April 30, 2024 11:28 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com> Subject: RE: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr [AMD Official Use Only - General] [AMD Official Use Only - General] Ping ... > -----Original Message----- > From: Huang, Tim <Tim.Huang@amd.com> > Sent: Sunday, April 28, 2024 4:45 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian > <Christian.Koenig@amd.com>; Huang, Tim <Tim.Huang@amd.com> > Subject: [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings > for vega10_hwmgr > > Clear warnings that using uninitialized variable when fails to get the > valid value from SMU. > > Signed-off-by: Tim Huang <Tim.Huang@amd.com> > --- > .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 46 ++++++++++++++----- > .../amd/pm/powerplay/smumgr/vega10_smumgr.c | 6 ++- > 2 files changed, 39 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > index 9f5bd998c6bf..488ad9de4694 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > @@ -354,13 +354,13 @@ static int > vega10_odn_initial_default_setting(struct > pp_hwmgr *hwmgr) > return 0; > } > > -static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) > +static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) > { > struct vega10_hwmgr *data = hwmgr->backend; > - int i; > uint32_t sub_vendor_id, hw_revision; > uint32_t top32, bottom32; > struct amdgpu_device *adev = hwmgr->adev; > + int ret, i; > > vega10_initialize_power_tune_defaults(hwmgr); > > @@ -485,9 +485,12 @@ static void vega10_init_dpm_defaults(struct > pp_hwmgr > *hwmgr) > if (data->registry_data.vr0hot_enabled) > data->smu_features[GNLD_VR0HOT].supported = true; > > - smum_send_msg_to_smc(hwmgr, > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetSmuVersion, > &hwmgr->smu_version); > + if (ret) > + return ret; > + > /* ACG firmware has major version 5 */ > if ((hwmgr->smu_version & 0xff000000) == 0x5000000) > data->smu_features[GNLD_ACG].supported = true; @@ > -505,10 > +508,16 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr > +*hwmgr) > data->smu_features[GNLD_PCC_LIMIT].supported = true; > > /* Get the SN to turn into a Unique ID */ > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, > &top32); > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_ReadSerialNumBottom32, &bottom32); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_ReadSerialNumTop32, &top32); > + if (ret) > + return ret; > + > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_ReadSerialNumBottom32, &bottom32); > + if (ret) > + return ret; > > adev->unique_id = ((uint64_t)bottom32 << 32) | top32; > + return 0; > } > > #ifdef PPLIB_VEGA10_EVV_SUPPORT > @@ -882,7 +891,9 @@ static int vega10_hwmgr_backend_init(struct > pp_hwmgr > *hwmgr) > > vega10_set_features_platform_caps(hwmgr); > > - vega10_init_dpm_defaults(hwmgr); > + result = vega10_init_dpm_defaults(hwmgr); > + if (result) > + return result; > > #ifdef PPLIB_VEGA10_EVV_SUPPORT > /* Get leakage voltage based on leakage ID. */ @@ -3900,11 > +3911,14 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, > uint32_t *query) > { > uint32_t value; > + int ret; > > if (!query) > return -EINVAL; > > - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, > &value); > + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, > &value); > + if (ret) > + return ret; > > /* SMC returning actual watts, keep consistent with legacy > asics, low 8 bit as 8 fractional bits */ > *query = value << 8; > @@ -4800,14 +4814,16 @@ static int vega10_print_clock_levels(struct > pp_hwmgr *hwmgr, > uint32_t gen_speed, lane_width, current_gen_speed, > current_lane_width; > PPTable_t *pptable = &(data->smc_state_table.pp_table); > > - int i, now, size = 0, count = 0; > + int i, ret, now, size = 0, count = 0; > > switch (type) { > case PP_SCLK: > if (data->registry_data.sclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentGfxclkIndex, &now); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentGfxclkIndex, &now); > + if (ret) > + break; > > if (hwmgr->pp_one_vf && > (hwmgr->dpm_level == > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) > @@ -4823,7 +4839,9 @@ static int vega10_print_clock_levels(struct > pp_hwmgr *hwmgr, > if (data->registry_data.mclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentUclkIndex, &now); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentUclkIndex, &now); > + if (ret) > + break; > > for (i = 0; i < mclk_table->count; i++) > size += sprintf(buf + size, "%d: %uMhz %s\n", @@ > - > 4834,7 +4852,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr > *hwmgr, > if (data->registry_data.socclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentSocclkIndex, &now); > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetCurrentSocclkIndex, &now); > + if (ret) > + break; > > for (i = 0; i < soc_table->count; i++) > size += sprintf(buf + size, "%d: %uMhz %s\n", @@ > - > 4845,8 +4865,10 @@ static int vega10_print_clock_levels(struct > pp_hwmgr *hwmgr, > if (data->registry_data.dcefclk_dpm_key_disabled) > break; > > - smum_send_msg_to_smc_with_parameter(hwmgr, > + ret = smum_send_msg_to_smc_with_parameter(hwmgr, > PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, > &now); > + if (ret) > + break; > > for (i = 0; i < dcef_table->count; i++) > size += sprintf(buf + size, "%d: %uMhz %s\n", > diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > index a70d73896649..f9c0f117725d 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c > @@ -130,13 +130,17 @@ int vega10_get_enabled_smc_features(struct > pp_hwmgr *hwmgr, > uint64_t *features_enabled) { > uint32_t enabled_features; > + int ret; > > if (features_enabled == NULL) > return -EINVAL; > > - smum_send_msg_to_smc(hwmgr, > + ret = smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_GetEnabledSmuFeatures, > &enabled_features); > + if (ret) > + return ret; > + > *features_enabled = enabled_features; > > return 0; > -- > 2.39.2 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-04-30 4:12 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-04-28 8:45 [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Tim Huang 2024-04-28 8:45 ` [PATCH 2/2] drm/amd/pm: fix uninitialized variable warnings for vangogh_ppt Tim Huang 2024-04-30 3:27 ` [PATCH 1/2] drm/amd/pm: fix uninitialized variable warnings for vega10_hwmgr Huang, Tim 2024-04-30 4:12 ` Wang, Yang(Kevin)
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