* [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 @ 2024-05-09 9:37 Ma Jun 2024-05-09 9:37 ` [PATCH 2/2] drm/amdgpu/pm: Check input value for CUSTOM profile mode setting on legacy SOCs Ma Jun 2024-05-09 13:01 ` [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Wang, Yang(Kevin) 0 siblings, 2 replies; 6+ messages in thread From: Ma Jun @ 2024-05-09 9:37 UTC (permalink / raw) To: amd-gfx Cc: Kenneth.Feng, Alexander.Deucher, kevinyang.wang, christian.koenig, Ma Jun Check the input value for CUSTOM profile mode setting on smu13 and smu14. Otherwise it may cause out-of-bouds read error. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++++ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 5 +++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index e8b01662e164..6c24e2306383 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2495,6 +2495,9 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 9) + return -EINVAL; + ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2526,6 +2529,8 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, activity_monitor->Fclk_PD_Data_error_coeff = input[7]; activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index e996a0a4d33e..4f98869e0284 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2450,6 +2450,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 8) + return -EINVAL; ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2478,6 +2480,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp activity_monitor->Fclk_MinActiveFreq = input[6]; activity_monitor->Fclk_BoosterFreq = input[7]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 0d5ad531c764..3f040a4d374e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1418,6 +1418,9 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 9) + return -EINVAL; + ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -1449,6 +1452,8 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, activity_monitor->Fclk_PD_Data_error_coeff = input[7]; activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amdgpu/pm: Check input value for CUSTOM profile mode setting on legacy SOCs 2024-05-09 9:37 [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Ma Jun @ 2024-05-09 9:37 ` Ma Jun 2024-05-09 13:01 ` [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Wang, Yang(Kevin) 1 sibling, 0 replies; 6+ messages in thread From: Ma Jun @ 2024-05-09 9:37 UTC (permalink / raw) To: amd-gfx Cc: Kenneth.Feng, Alexander.Deucher, kevinyang.wang, christian.koenig, Ma Jun Check the input value for CUSTOM profile mode setting on legacy SOCs. Otherwise it may cause out-of-bouds read error. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 2 +- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 8 ++++++-- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 5 +++++ drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 ++++ drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++++ 5 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 5c95eda6cbd2..52ac95f8a84f 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -5647,7 +5647,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint mode = input[size]; switch (mode) { case PP_SMC_POWER_PROFILE_CUSTOM: - if (size < 8 && size != 0) + if (size != 8 && size != 0) return -EINVAL; /* If only CUSTOM is passed in, use the saved values. Check * that we actually have a CUSTOM profile by ensuring that diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c index bf1b829f9d68..baf251fe5d82 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c @@ -4102,9 +4102,11 @@ static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); - if (size == 0 && !data->is_custom_profile_set) + + if (size != 10 && size != 0) return -EINVAL; - if (size < 10 && size != 0) + + if (size == 0 && !data->is_custom_profile_set) return -EINVAL; result = vega20_get_activity_monitor_coeff(hwmgr, @@ -4166,6 +4168,8 @@ static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui activity_monitor.Fclk_PD_Data_error_coeff = input[8]; activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; break; + default: + return -EINVAL; } result = vega20_set_activity_monitor_coeff(hwmgr, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 6d334a2aff67..623f6052f97e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -1416,6 +1416,9 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && (smu->smc_fw_version >= 0x360d00)) { + if (size != 10) + return -EINVAL; + ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -1449,6 +1452,8 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, activity_monitor.Mem_PD_Data_error_coeff = input[8]; activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index c06e0d6e3017..01039cdd456b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2021,6 +2021,8 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 10) + return -EINVAL; ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2064,6 +2066,8 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u activity_monitor.Mem_PD_Data_error_coeff = input[8]; activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index e426f457a017..d5a21d7836cc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1722,6 +1722,8 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 10) + return -EINVAL; ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -1765,6 +1767,8 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * activity_monitor->Mem_PD_Data_error_coeff = input[8]; activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 2024-05-09 9:37 [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Ma Jun 2024-05-09 9:37 ` [PATCH 2/2] drm/amdgpu/pm: Check input value for CUSTOM profile mode setting on legacy SOCs Ma Jun @ 2024-05-09 13:01 ` Wang, Yang(Kevin) 2024-05-10 1:00 ` Ma, Jun 1 sibling, 1 reply; 6+ messages in thread From: Wang, Yang(Kevin) @ 2024-05-09 13:01 UTC (permalink / raw) To: Ma, Jun, amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth, Deucher, Alexander, Koenig, Christian [AMD Official Use Only - General] please fix similar issues in other xxx_ppt.c file together? e. g: navi10_ppt.c, etc Best Regards, Kevin -----Original Message----- From: Ma, Jun <Jun.Ma2@amd.com> Sent: Thursday, May 9, 2024 5:37 PM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Ma, Jun <Jun.Ma2@amd.com> Subject: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Check the input value for CUSTOM profile mode setting on smu13 and smu14. Otherwise it may cause out-of-bouds read error. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++++ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 5 +++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index e8b01662e164..6c24e2306383 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2495,6 +2495,9 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 9) + return -EINVAL; + ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2526,6 +2529,8 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, activity_monitor->Fclk_PD_Data_error_coeff = input[7]; activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index e996a0a4d33e..4f98869e0284 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2450,6 +2450,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 8) + return -EINVAL; ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2478,6 +2480,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp activity_monitor->Fclk_MinActiveFreq = input[6]; activity_monitor->Fclk_BoosterFreq = input[7]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 0d5ad531c764..3f040a4d374e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1418,6 +1418,9 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, } if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { + if (size != 9) + return -EINVAL; + ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -1449,6 +1452,8 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, activity_monitor->Fclk_PD_Data_error_coeff = input[7]; activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; break; + default: + return -EINVAL; } ret = smu_cmn_update_table(smu, -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 2024-05-09 13:01 ` [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Wang, Yang(Kevin) @ 2024-05-10 1:00 ` Ma, Jun 2024-05-10 1:41 ` Wang, Yang(Kevin) 0 siblings, 1 reply; 6+ messages in thread From: Ma, Jun @ 2024-05-10 1:00 UTC (permalink / raw) To: Wang, Yang(Kevin), Ma, Jun, amd-gfx@lists.freedesktop.org Cc: majun, Feng, Kenneth, Deucher, Alexander, Koenig, Christian On 5/9/2024 9:01 PM, Wang, Yang(Kevin) wrote: > [AMD Official Use Only - General] > > please fix similar issues in other xxx_ppt.c file together? e. g: navi10_ppt.c, etc > Fix codes for navi10,vega20, etc. are in the patch 2 of this serial. Regards, Ma Jun > Best Regards, > Kevin > -----Original Message----- > From: Ma, Jun <Jun.Ma2@amd.com> > Sent: Thursday, May 9, 2024 5:37 PM > To: amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Ma, Jun <Jun.Ma2@amd.com> > Subject: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 > > Check the input value for CUSTOM profile mode setting on smu13 and smu14. Otherwise it may cause out-of-bouds read error. > > Signed-off-by: Ma Jun <Jun.Ma2@amd.com> > --- > drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++++ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 5 +++++ > 3 files changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > index e8b01662e164..6c24e2306383 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > @@ -2495,6 +2495,9 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, > } > > if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { > + if (size != 9) > + return -EINVAL; > + > ret = smu_cmn_update_table(smu, > SMU_TABLE_ACTIVITY_MONITOR_COEFF, > WORKLOAD_PPLIB_CUSTOM_BIT, > @@ -2526,6 +2529,8 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, > activity_monitor->Fclk_PD_Data_error_coeff = input[7]; > activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; > break; > + default: > + return -EINVAL; > } > > ret = smu_cmn_update_table(smu, > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > index e996a0a4d33e..4f98869e0284 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > @@ -2450,6 +2450,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp > } > > if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { > + if (size != 8) > + return -EINVAL; > > ret = smu_cmn_update_table(smu, > SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2478,6 +2480,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp > activity_monitor->Fclk_MinActiveFreq = input[6]; > activity_monitor->Fclk_BoosterFreq = input[7]; > break; > + default: > + return -EINVAL; > } > > ret = smu_cmn_update_table(smu, > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > index 0d5ad531c764..3f040a4d374e 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > @@ -1418,6 +1418,9 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, > } > > if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { > + if (size != 9) > + return -EINVAL; > + > ret = smu_cmn_update_table(smu, > SMU_TABLE_ACTIVITY_MONITOR_COEFF, > WORKLOAD_PPLIB_CUSTOM_BIT, > @@ -1449,6 +1452,8 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, > activity_monitor->Fclk_PD_Data_error_coeff = input[7]; > activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; > break; > + default: > + return -EINVAL; > } > > ret = smu_cmn_update_table(smu, > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 2024-05-10 1:00 ` Ma, Jun @ 2024-05-10 1:41 ` Wang, Yang(Kevin) 2024-05-10 1:53 ` Ma, Jun 0 siblings, 1 reply; 6+ messages in thread From: Wang, Yang(Kevin) @ 2024-05-10 1:41 UTC (permalink / raw) To: Ma, Jun, amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth, Deucher, Alexander, Koenig, Christian [AMD Official Use Only - General] Ok, I miss this patch #2. And please merge swsmu parts in patch#1 to patch#2. (patch #1 : powerplay, patch #2: swsmu) Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Best Regards, Kevin -----Original Message----- From: Ma, Jun <Jun.Ma2@amd.com> Sent: Friday, May 10, 2024 9:00 AM To: Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Ma, Jun <Jun.Ma2@amd.com>; amd-gfx@lists.freedesktop.org Cc: Ma, Jun <Jun.Ma2@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com> Subject: Re: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 On 5/9/2024 9:01 PM, Wang, Yang(Kevin) wrote: > [AMD Official Use Only - General] > > please fix similar issues in other xxx_ppt.c file together? e. g: > navi10_ppt.c, etc > Fix codes for navi10,vega20, etc. are in the patch 2 of this serial. Regards, Ma Jun > Best Regards, > Kevin > -----Original Message----- > From: Ma, Jun <Jun.Ma2@amd.com> > Sent: Thursday, May 9, 2024 5:37 PM > To: amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Wang, Yang(Kevin) > <KevinYang.Wang@amd.com>; Koenig, Christian > <Christian.Koenig@amd.com>; Ma, Jun <Jun.Ma2@amd.com> > Subject: [PATCH 1/2] drm/amdgpu/pm: Check input value for power > profile setting on smu13 and smu14 > > Check the input value for CUSTOM profile mode setting on smu13 and smu14. Otherwise it may cause out-of-bouds read error. > > Signed-off-by: Ma Jun <Jun.Ma2@amd.com> > --- > drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++++ > drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++++ > drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 5 +++++ > 3 files changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > index e8b01662e164..6c24e2306383 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c > @@ -2495,6 +2495,9 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, > } > > if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { > + if (size != 9) > + return -EINVAL; > + > ret = smu_cmn_update_table(smu, > SMU_TABLE_ACTIVITY_MONITOR_COEFF, > WORKLOAD_PPLIB_CUSTOM_BIT, > @@ -2526,6 +2529,8 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, > activity_monitor->Fclk_PD_Data_error_coeff = input[7]; > activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; > break; > + default: > + return -EINVAL; > } > > ret = smu_cmn_update_table(smu, diff --git > a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > index e996a0a4d33e..4f98869e0284 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c > @@ -2450,6 +2450,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp > } > > if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { > + if (size != 8) > + return -EINVAL; > > ret = smu_cmn_update_table(smu, > SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2478,6 +2480,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp > activity_monitor->Fclk_MinActiveFreq = input[6]; > activity_monitor->Fclk_BoosterFreq = input[7]; > break; > + default: > + return -EINVAL; > } > > ret = smu_cmn_update_table(smu, diff --git > a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > index 0d5ad531c764..3f040a4d374e 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c > @@ -1418,6 +1418,9 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, > } > > if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { > + if (size != 9) > + return -EINVAL; > + > ret = smu_cmn_update_table(smu, > SMU_TABLE_ACTIVITY_MONITOR_COEFF, > WORKLOAD_PPLIB_CUSTOM_BIT, > @@ -1449,6 +1452,8 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, > activity_monitor->Fclk_PD_Data_error_coeff = input[7]; > activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; > break; > + default: > + return -EINVAL; > } > > ret = smu_cmn_update_table(smu, > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 2024-05-10 1:41 ` Wang, Yang(Kevin) @ 2024-05-10 1:53 ` Ma, Jun 0 siblings, 0 replies; 6+ messages in thread From: Ma, Jun @ 2024-05-10 1:53 UTC (permalink / raw) To: Wang, Yang(Kevin), Ma, Jun, amd-gfx@lists.freedesktop.org Cc: majun, Feng, Kenneth, Deucher, Alexander, Koenig, Christian On 5/10/2024 9:41 AM, Wang, Yang(Kevin) wrote: > [AMD Official Use Only - General] > > Ok, I miss this patch #2. > > And please merge swsmu parts in patch#1 to patch#2. (patch #1 : powerplay, patch #2: swsmu) Thanks, will fix this when push. Regards, Ma Jun > > Reviewed-by: Yang Wang <kevinyang.wang@amd.com> > > Best Regards, > Kevin > > -----Original Message----- > From: Ma, Jun <Jun.Ma2@amd.com> > Sent: Friday, May 10, 2024 9:00 AM > To: Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Ma, Jun <Jun.Ma2@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Ma, Jun <Jun.Ma2@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com> > Subject: Re: [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 > > > > On 5/9/2024 9:01 PM, Wang, Yang(Kevin) wrote: >> [AMD Official Use Only - General] >> >> please fix similar issues in other xxx_ppt.c file together? e. g: >> navi10_ppt.c, etc >> > > Fix codes for navi10,vega20, etc. are in the patch 2 of this serial. > > Regards, > Ma Jun > >> Best Regards, >> Kevin >> -----Original Message----- >> From: Ma, Jun <Jun.Ma2@amd.com> >> Sent: Thursday, May 9, 2024 5:37 PM >> To: amd-gfx@lists.freedesktop.org >> Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander >> <Alexander.Deucher@amd.com>; Wang, Yang(Kevin) >> <KevinYang.Wang@amd.com>; Koenig, Christian >> <Christian.Koenig@amd.com>; Ma, Jun <Jun.Ma2@amd.com> >> Subject: [PATCH 1/2] drm/amdgpu/pm: Check input value for power >> profile setting on smu13 and smu14 >> >> Check the input value for CUSTOM profile mode setting on smu13 and smu14. Otherwise it may cause out-of-bouds read error. >> >> Signed-off-by: Ma Jun <Jun.Ma2@amd.com> >> --- >> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 5 +++++ >> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++++ >> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 5 +++++ >> 3 files changed, 14 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c >> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c >> index e8b01662e164..6c24e2306383 100644 >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c >> @@ -2495,6 +2495,9 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, >> } >> >> if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { >> + if (size != 9) >> + return -EINVAL; >> + >> ret = smu_cmn_update_table(smu, >> SMU_TABLE_ACTIVITY_MONITOR_COEFF, >> WORKLOAD_PPLIB_CUSTOM_BIT, >> @@ -2526,6 +2529,8 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, >> activity_monitor->Fclk_PD_Data_error_coeff = input[7]; >> activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; >> break; >> + default: >> + return -EINVAL; >> } >> >> ret = smu_cmn_update_table(smu, diff --git >> a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c >> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c >> index e996a0a4d33e..4f98869e0284 100644 >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c >> @@ -2450,6 +2450,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp >> } >> >> if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { >> + if (size != 8) >> + return -EINVAL; >> >> ret = smu_cmn_update_table(smu, >> SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, @@ -2478,6 +2480,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp >> activity_monitor->Fclk_MinActiveFreq = input[6]; >> activity_monitor->Fclk_BoosterFreq = input[7]; >> break; >> + default: >> + return -EINVAL; >> } >> >> ret = smu_cmn_update_table(smu, diff --git >> a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c >> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c >> index 0d5ad531c764..3f040a4d374e 100644 >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c >> @@ -1418,6 +1418,9 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, >> } >> >> if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { >> + if (size != 9) >> + return -EINVAL; >> + >> ret = smu_cmn_update_table(smu, >> SMU_TABLE_ACTIVITY_MONITOR_COEFF, >> WORKLOAD_PPLIB_CUSTOM_BIT, >> @@ -1449,6 +1452,8 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, >> activity_monitor->Fclk_PD_Data_error_coeff = input[7]; >> activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; >> break; >> + default: >> + return -EINVAL; >> } >> >> ret = smu_cmn_update_table(smu, >> -- >> 2.34.1 >> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-05-10 1:53 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-05-09 9:37 [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Ma Jun 2024-05-09 9:37 ` [PATCH 2/2] drm/amdgpu/pm: Check input value for CUSTOM profile mode setting on legacy SOCs Ma Jun 2024-05-09 13:01 ` [PATCH 1/2] drm/amdgpu/pm: Check input value for power profile setting on smu13 and smu14 Wang, Yang(Kevin) 2024-05-10 1:00 ` Ma, Jun 2024-05-10 1:41 ` Wang, Yang(Kevin) 2024-05-10 1:53 ` Ma, Jun
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