From: <boyuan.zhang@amd.com>
To: <amd-gfx@lists.freedesktop.org>, <leo.liu@amd.com>,
<christian.koenig@amd.com>, <alexander.deucher@amd.com>,
<sunil.khatri@amd.com>
Cc: Boyuan Zhang <boyuan.zhang@amd.com>
Subject: [PATCH 03/32] drm/amd/pm: add inst to smu_dpm_set_vcn_enable
Date: Tue, 8 Oct 2024 17:15:24 -0400 [thread overview]
Message-ID: <20241008211553.36264-4-boyuan.zhang@amd.com> (raw)
In-Reply-To: <20241008211553.36264-1-boyuan.zhang@amd.com>
From: Boyuan Zhang <boyuan.zhang@amd.com>
First, add an instance parameter to smu_dpm_set_vcn_enable() function,
and calling dpm_set_vcn_enable() with this given instance.
Second, modify vcn_gated to be an array, to track the gating status
for each vcn instance separately.
With these 2 changes, smu_dpm_set_vcn_enable() will check and set the
gating status for the given vcn instance ONLY.
v2: remove duplicated functions.
remove for-loop in dpm_set_vcn_enable(), and temporarily move it to
to smu_dpm_set_power_gate(), in order to keep the exact same logic as
before, until further separation in next patch.
v3: add instance number in error message.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 65 ++++++++++++-------
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
2 files changed, 41 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 410d5baedfbc..639bc6d97b27 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -233,11 +233,11 @@ static bool is_vcn_enabled(struct amdgpu_device *adev)
}
static int smu_dpm_set_vcn_enable(struct smu_context *smu,
- bool enable)
+ bool enable,
+ int inst)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
- struct amdgpu_device *adev = smu->adev;
int ret = 0;
/*
@@ -249,16 +249,12 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (!smu->ppt_funcs->dpm_set_vcn_enable)
return 0;
- if (atomic_read(&power_gate->vcn_gated) ^ enable)
+ if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
return 0;
- for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, i);
- if (ret)
- return ret;
- }
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
if (!ret)
- atomic_set(&power_gate->vcn_gated, !enable);
+ atomic_set(&power_gate->vcn_gated[inst], !enable);
return ret;
}
@@ -360,6 +356,7 @@ static int smu_dpm_set_power_gate(void *handle,
bool gate)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
@@ -376,10 +373,12 @@ static int smu_dpm_set_power_gate(void *handle,
*/
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCN:
- ret = smu_dpm_set_vcn_enable(smu, !gate);
- if (ret)
- dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
- gate ? "gate" : "ungate");
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu_dpm_set_vcn_enable(smu, !gate, i);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
+ gate ? "gate" : "ungate", i);
+ }
break;
case AMD_IP_BLOCK_TYPE_GFX:
ret = smu_gfx_off_control(smu, gate);
@@ -781,21 +780,25 @@ static int smu_set_default_dpm_table(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
- int vcn_gate, jpeg_gate;
+ int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i;
int ret = 0;
if (!smu->ppt_funcs->set_default_dpm_table)
return 0;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- vcn_gate = atomic_read(&power_gate->vcn_gated);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++)
+ vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]);
+ }
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
jpeg_gate = atomic_read(&power_gate->jpeg_gated);
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
- ret = smu_dpm_set_vcn_enable(smu, true);
- if (ret)
- return ret;
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu_dpm_set_vcn_enable(smu, true, i);
+ if (ret)
+ return ret;
+ }
}
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
@@ -812,8 +815,10 @@ static int smu_set_default_dpm_table(struct smu_context *smu)
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
err_out:
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- smu_dpm_set_vcn_enable(smu, !vcn_gate);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++)
+ smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i);
+ }
return ret;
}
@@ -1258,7 +1263,8 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
- atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
@@ -1820,7 +1826,8 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block)
ret = smu_set_gfx_imu_enable(smu);
if (ret)
return ret;
- smu_dpm_set_vcn_enable(smu, true);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ smu_dpm_set_vcn_enable(smu, true, i);
smu_dpm_set_jpeg_enable(smu, true);
smu_dpm_set_vpe_enable(smu, true);
smu_dpm_set_umsch_mm_enable(smu, true);
@@ -2023,7 +2030,8 @@ static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
- smu_dpm_set_vcn_enable(smu, false);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ smu_dpm_set_vcn_enable(smu, false, i);
smu_dpm_set_jpeg_enable(smu, false);
smu_dpm_set_vpe_enable(smu, false);
smu_dpm_set_umsch_mm_enable(smu, false);
@@ -2937,6 +2945,7 @@ static int smu_read_sensor(void *handle,
int *size_arg)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
int ret = 0;
@@ -2985,7 +2994,13 @@ static int smu_read_sensor(void *handle,
*size = 4;
break;
case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
- *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
+ *(uint32_t *)data = 0;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
+ *(uint32_t *)data = 1;
+ break;
+ }
+ }
*size = 4;
break;
case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 0f074b6c8b58..427441b469e0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -399,7 +399,7 @@ struct smu_dpm_context {
struct smu_power_gate {
bool uvd_gated;
bool vce_gated;
- atomic_t vcn_gated;
+ atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
atomic_t jpeg_gated;
atomic_t vpe_gated;
atomic_t umsch_mm_gated;
--
2.34.1
next prev parent reply other threads:[~2024-10-08 21:16 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-08 21:15 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
2024-10-08 21:15 ` [PATCH 01/32] drm/amd/pm: add inst to dpm_set_vcn_enable boyuan.zhang
2024-10-08 21:15 ` [PATCH 02/32] drm/amd/pm: power up or down vcn by instance boyuan.zhang
2024-10-09 11:37 ` Christian König
2024-10-08 21:15 ` boyuan.zhang [this message]
2024-10-08 21:15 ` [PATCH 04/32] drm/amd/pm: add inst to set_powergating_by_smu boyuan.zhang
2024-10-08 21:15 ` [PATCH 05/32] drm/amd/pm: add inst to dpm_set_powergating_by_smu boyuan.zhang
2024-10-08 21:15 ` [PATCH 06/32] add inst to amdgpu_dpm_enable_vcn boyuan.zhang
2024-10-08 21:15 ` [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
2024-10-08 21:15 ` [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state boyuan.zhang
2024-10-08 21:15 ` [PATCH 09/32] drm/amdgpu: track instances of the same IP block boyuan.zhang
2024-10-08 21:15 ` [PATCH 10/32] drm/amdgpu: move per inst variables to amdgpu_vcn_inst boyuan.zhang
2024-10-08 21:15 ` [PATCH 11/32] drm/amdgpu/vcn: separate gating state by instance boyuan.zhang
2024-10-08 21:15 ` [PATCH 12/32] drm/amdgpu: power vcn 2_5 " boyuan.zhang
2024-10-08 21:15 ` [PATCH 13/32] drm/amdgpu: power vcn 3_0 " boyuan.zhang
2024-10-08 21:15 ` [PATCH 14/32] drm/amdgpu: power vcn 4_0 " boyuan.zhang
2024-10-08 21:15 ` [PATCH 15/32] drm/amdgpu: power vcn 4_0_3 " boyuan.zhang
2024-10-08 21:15 ` [PATCH 16/32] drm/amdgpu: power vcn 4_0_5 " boyuan.zhang
2024-10-08 21:15 ` [PATCH 17/32] drm/amdgpu: power vcn 5_0_0 " boyuan.zhang
2024-10-08 21:15 ` [PATCH 18/32] drm/amdgpu/vcn: separate idle work " boyuan.zhang
2024-10-08 21:15 ` [PATCH 19/32] drm/amdgpu: set powergating state by vcn instance boyuan.zhang
2024-10-08 21:15 ` [PATCH 20/32] drm/amdgpu: early_init for each " boyuan.zhang
2024-10-08 21:15 ` [PATCH 21/32] drm/amdgpu: sw_init " boyuan.zhang
2024-10-08 21:15 ` [PATCH 22/32] drm/amdgpu: sw_fini " boyuan.zhang
2024-10-08 21:15 ` [PATCH 23/32] drm/amdgpu: hw_init " boyuan.zhang
2024-10-08 21:15 ` [PATCH 24/32] drm/amdgpu: suspend " boyuan.zhang
2024-10-08 21:15 ` [PATCH 25/32] drm/amdgpu: resume " boyuan.zhang
2024-10-08 21:15 ` [PATCH 26/32] drm/amdgpu: setup_ucode " boyuan.zhang
2024-10-08 21:15 ` [PATCH 27/32] drm/amdgpu: set funcs " boyuan.zhang
2024-10-08 21:15 ` [PATCH 28/32] drm/amdgpu: print_ip_state " boyuan.zhang
2024-10-08 21:15 ` [PATCH 29/32] drm/amdgpu: dump_ip_state " boyuan.zhang
2024-10-08 21:15 ` [PATCH 30/32] drm/amdgpu: wait_for_idle " boyuan.zhang
2024-10-08 21:15 ` [PATCH 31/32] drm/amdgpu: is_idle " boyuan.zhang
2024-10-08 21:15 ` [PATCH 32/32] drm/amdgpu: set_powergating " boyuan.zhang
-- strict thread matches above, loose matches on Subject: below --
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 03/32] drm/amd/pm: add inst to smu_dpm_set_vcn_enable boyuan.zhang
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