* [PATCH 0/2] Expand Display code documentation
@ 2024-10-17 3:34 Rodrigo Siqueira
2024-10-17 3:34 ` [PATCH 1/2] Documentation/gpu: Document how to narrow down display issues Rodrigo Siqueira
2024-10-17 3:34 ` [PATCH 2/2] Documentation/gpu/amdgpu: Add programming model for DCN Rodrigo Siqueira
0 siblings, 2 replies; 5+ messages in thread
From: Rodrigo Siqueira @ 2024-10-17 3:34 UTC (permalink / raw)
To: amd-gfx; +Cc: Rodrigo Siqueira
This patchset expands two areas of the display documentation:
1. Add more techniques for debugging the display code.
2. Introduce an explanation of the programming model used by DC.
Thanks
Rodrigo Siqueira (2):
Documentation/gpu: Document how to narrow down display issues
Documentation/gpu/amdgpu: Add programming model for DCN
.../gpu/amdgpu/display/dc-arch-overview.svg | 731 +++++++++++++++++
.../gpu/amdgpu/display/dc-components.svg | 732 ++++++++++++++++++
Documentation/gpu/amdgpu/display/dc-debug.rst | 187 +++++
.../gpu/amdgpu/display/dcn-blocks.rst | 2 +
.../gpu/amdgpu/display/dcn-overview.rst | 2 +
Documentation/gpu/amdgpu/display/index.rst | 1 +
.../amdgpu/display/programming-model-dcn.rst | 162 ++++
7 files changed, 1817 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/display/dc-arch-overview.svg
create mode 100644 Documentation/gpu/amdgpu/display/dc-components.svg
create mode 100644 Documentation/gpu/amdgpu/display/programming-model-dcn.rst
--
2.45.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] Documentation/gpu: Document how to narrow down display issues
2024-10-17 3:34 [PATCH 0/2] Expand Display code documentation Rodrigo Siqueira
@ 2024-10-17 3:34 ` Rodrigo Siqueira
2024-10-17 19:00 ` Mario Limonciello
2024-10-17 3:34 ` [PATCH 2/2] Documentation/gpu/amdgpu: Add programming model for DCN Rodrigo Siqueira
1 sibling, 1 reply; 5+ messages in thread
From: Rodrigo Siqueira @ 2024-10-17 3:34 UTC (permalink / raw)
To: amd-gfx
Cc: Rodrigo Siqueira, Leo Li, Aurabindo Pillai, Hamza Mahfooz,
Harry Wentland, Mario Limonciello, Christian Konig, Alex Deucher
The amdgpu driver is composed of multiple components, each of which can
be a source of some specific problem that the user/developer can see.
This commit introduces steps to narrow down and collect display
information.
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Christian Konig <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/dc-debug.rst | 187 ++++++++++++++++++
1 file changed, 187 insertions(+)
diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
index 817631b1dbf3..013f63b271f3 100644
--- a/Documentation/gpu/amdgpu/display/dc-debug.rst
+++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
@@ -2,6 +2,181 @@
Display Core Debug tools
========================
+In this section, you will find helpful information on debugging the amdgpu
+driver from the display perspective. This page introduces debug mechanisms and
+procedures to help you identify if some issues are related to display code.
+
+Narrow down display issues
+==========================
+
+Since the display is the driver's visual component, it is common to see users
+reporting issues as a display when another component causes the problem. This
+section equips users to determine if a specific issue was caused by the display
+component or another part of the driver.
+
+DC dmesg important messages
+---------------------------
+
+The dmesg log is the first source of information to be checked, and amdgpu
+takes advantage of this feature by logging some valuable information. When
+looking for the issues associated with amdgpu, remember that each component of
+the driver (e.g., smu, PSP, dm, etc.) is loaded one by one, and this
+information can be found in the dmesg log. In this sense, look for the part of
+the log that looks like the below log snippet::
+
+ [ 4.254295] [drm] initializing kernel modesetting (IP DISCOVERY 0x1002:0x744C 0x1002:0x0E3B 0xC8).
+ [ 4.254718] [drm] register mmio base: 0xFCB00000
+ [ 4.254918] [drm] register mmio size: 1048576
+ [ 4.260095] [drm] add ip block number 0 <soc21_common>
+ [ 4.260318] [drm] add ip block number 1 <gmc_v11_0>
+ [ 4.260510] [drm] add ip block number 2 <ih_v6_0>
+ [ 4.260696] [drm] add ip block number 3 <psp>
+ [ 4.260878] [drm] add ip block number 4 <smu>
+ [ 4.261057] [drm] add ip block number 5 <dm>
+ [ 4.261231] [drm] add ip block number 6 <gfx_v11_0>
+ [ 4.261402] [drm] add ip block number 7 <sdma_v6_0>
+ [ 4.261568] [drm] add ip block number 8 <vcn_v4_0>
+ [ 4.261729] [drm] add ip block number 9 <jpeg_v4_0>
+ [ 4.261887] [drm] add ip block number 10 <mes_v11_0>
+
+From the above example, you can see the line that reports that `<dm>`,
+(**Display Manager**), was loaded, which means that display can be part of the
+issue. If you do not see that line, something else might have failed before
+amdgpu loads the display component, indicating that we don't have a
+display issue.
+
+After you identified that the DM was loaded correctly, you can check for the
+display version of the hardware in use, which can be retrieved from the dmesg
+log with the command::
+
+ dmesg | grep -i 'display core'
+
+This command shows a message that looks like this::
+
+ [ 4.655828] [drm] Display Core v3.2.285 initialized on DCN 3.2
+
+This message has two key pieces of information:
+
+* **The DC version (e.g., v3.2.285)**: Display developers release a new DC version
+ every week, and this information can be advantageous in a situation where a
+ user/developer must find a good point versus a bad point based on a tested
+ version of the display code. Remember from page :ref:`Display Core <amdgpu-display-core>`,
+ that every week the new patches for display are heavily tested with IGT and
+ manual tests.
+* **The DCN version (e.g., DCN 3.2)**: The DCN block is associated with the
+ hardware generation, and the DCN version conveys the hardware generation that
+ the driver is currently running. This information helps to narrow down the
+ code debug area since each DCN version has its files in the DC folder per DCN
+ component (from the example, the developer might want to focus on
+ files/folders/functions/structs with the dcn32 label might be executed).
+ However, keep in mind that DC reuses code across different DCN versions; for
+ example, it is expected to have some callbacks set in one DCN that are the same
+ as those from another DCN. In summary, use the DCN version just as a guide.
+
+From the dmesg file, it is also possible to get the ATOM bios code by using::
+
+ dmesg | grep -i 'ATOM BIOS'
+
+Which generates an output that looks like this::
+
+ [ 4.274534] amdgpu: ATOM BIOS: 113-D7020100-102
+
+This type of information is useful to be reported.
+
+Avoid loading display core
+--------------------------
+
+Sometimes, it might be hard to figure out which part of the driver is causing
+the issue; if you suspect that the display is not part of the problem and your
+bug scenario is simple (e.g., some desktop configuration) you can try to remove
+the display component from the equation. First, you need to identify `dm` ID
+from the dmesg log; for example, search for the following log::
+
+ [ 4.254295] [drm] initializing kernel modesetting (IP DISCOVERY 0x1002:0x744C 0x1002:0x0E3B 0xC8).
+ [..]
+ [ 4.260095] [drm] add ip block number 0 <soc21_common>
+ [ 4.260318] [drm] add ip block number 1 <gmc_v11_0>
+ [..]
+ [ 4.261057] [drm] add ip block number 5 <dm>
+
+Notice from the above example that the `dm` id is 5 for this specific hardware.
+Next, you need to run the following binary operation to identify the IP block
+mask::
+
+ 0xffffffff & ~(1 << [DM ID])
+
+From our example the IP mask is::
+
+ 0xffffffff & ~(1 << 5) = 0xffffffdf
+
+Finally, to disable DC, you just need to set the below parameter in your
+bootloader::
+
+ amdgpu.ip_block_mask = 0xffffffdf
+
+If you can boot your system with the DC disabled and still see the issue, it
+means you can rule DC out of the equation. However, if the bug disappears, you
+still need to consider the DC part of the problem and keep narrowing down the
+issue. In some scenarios, disabling DC is impossible since it might be
+necessary to use the display component to reproduce the issue (e.g., play a
+game).
+
+**Note: This will probably lead to the absence of a display output.**
+
+Display flickering
+------------------
+
+Display flickering might have multiple causes; one is the lack of proper power
+to the GPU or problems in the DPM switches. A good first generic verification
+is to set the GPU to use high voltage::
+
+ bash -c "echo high > /sys/class/drm/card0/device/power_dpm_force_performance_level"
+
+The above command sets the GPU/APU to use the maximum power allowed which
+disables DPM switches. If forcing DPM levels high does not fix the issue, it
+is less likely that the issue is related to power management. If the issue
+disappears, there is a good chance that other components might be involved, and
+the display should not be ignored since this could be a DPM issues. From the
+display side, if the power increase fixes the issue, it is worth debugging the
+clock configuration and the pipe split police used in the specific
+configuration.
+
+Display artifacts
+-----------------
+
+Users may see some screen artifacts that can be categorized into two different
+types: localized artifacts and general artifacts. The localized artifacts
+happen in some specific areas, such as around the UI window corners; if you see
+this type of issue, there is a considerable chance that you have a userspace
+problem, likely Mesa or similar. The general artifacts usually happen on the
+entire screen. They might be caused by a misconfiguration at the driver level
+of the display parameters, but the userspace might also cause this issue. One
+way to identify the source of the problem is to take a screenshot or make a
+desktop video capture when the problem happens; after checking the
+screenshot/video recording, if you don't see any of the artifacts, it means
+that the issue is likely on the the driver side. If you can still see the
+problem in the data collected, it is an issue that probably happened during
+rendering, and the display code just got the framebuffer already corrupted.
+
+Disabling/Enabling specific features
+====================================
+
+DC has a struct named `dc_debug_options`, which is statically initialized by
+all DCE/DCN components based on the specific hardware characteristic. This
+structure usually facilitates the bring-up phase since developers can start
+with many disabled features and enable them individually. This is also an
+important debug feature since users can change it when debugging specific
+issues.
+
+For example, dGPU users sometimes see a problem where a horizontal fillet of
+flickering happens in some specific part of the screen. This could be an
+indication of Sub-Viewport issues; after the users identified the target DCN,
+they can set the `force_disable_subvp` field to true in the statically
+initialized version of `dc_debug_options` to see if the issue gets fixed. Along
+the same lines, users/developers can also try to turn off `fams2_config` and
+`enable_single_display_2to1_odm_policy`. In summary, the `dc_debug_options` is
+an interesting form for identifying the problem.
+
DC Visual Confirmation
======================
@@ -76,6 +251,18 @@ change in real-time by using something like::
When reporting a bug related to DC, consider attaching this log before and
after you reproduce the bug.
+Collect Firmware information
+============================
+
+When reporting issues, it is important to have the firmware information since
+it can be helpful for debugging purposes. To get all the firmware information,
+use the command::
+
+ cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
+
+From the display perspective, pay attention to the firmware of the DMCU and
+DMCUB.
+
DMUB Firmware Debug
===================
--
2.45.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] Documentation/gpu/amdgpu: Add programming model for DCN
2024-10-17 3:34 [PATCH 0/2] Expand Display code documentation Rodrigo Siqueira
2024-10-17 3:34 ` [PATCH 1/2] Documentation/gpu: Document how to narrow down display issues Rodrigo Siqueira
@ 2024-10-17 3:34 ` Rodrigo Siqueira
2024-10-23 18:12 ` Harry Wentland
1 sibling, 1 reply; 5+ messages in thread
From: Rodrigo Siqueira @ 2024-10-17 3:34 UTC (permalink / raw)
To: amd-gfx
Cc: Rodrigo Siqueira, Leo Li, Aurabindo Pillai, Hamza Mahfooz,
Harry Wentland, Mario Limonciello, Christian Konig, Alex Deucher
One of the challenges to contributing to the display code is the
complexity of the DC component. This commit adds a documentation page
that discusses the programming model used by DCN and an overview of how
the display code is organized.
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Christian Konig <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/amdgpu/display/dc-arch-overview.svg | 731 +++++++++++++++++
.../gpu/amdgpu/display/dc-components.svg | 732 ++++++++++++++++++
.../gpu/amdgpu/display/dcn-blocks.rst | 2 +
.../gpu/amdgpu/display/dcn-overview.rst | 2 +
Documentation/gpu/amdgpu/display/index.rst | 1 +
.../amdgpu/display/programming-model-dcn.rst | 162 ++++
6 files changed, 1630 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/display/dc-arch-overview.svg
create mode 100644 Documentation/gpu/amdgpu/display/dc-components.svg
create mode 100644 Documentation/gpu/amdgpu/display/programming-model-dcn.rst
diff --git a/Documentation/gpu/amdgpu/display/dc-arch-overview.svg b/Documentation/gpu/amdgpu/display/dc-arch-overview.svg
new file mode 100644
index 000000000000..23394931cf26
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/dc-arch-overview.svg
@@ -0,0 +1,731 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+
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diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
index 5e34366f6dbe..756957128dad 100644
--- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
@@ -1,3 +1,5 @@
+.. _dcn_blocks:
+
==========
DCN Blocks
==========
diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
index 9fea6500448b..eb54a6802e04 100644
--- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
@@ -1,3 +1,5 @@
+.. _dcn_overview:
+
=======================
Display Core Next (DCN)
=======================
diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
index f0c342e00a39..bd2d797c123e 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -90,6 +90,7 @@ table of content:
display-manager.rst
dcn-overview.rst
dcn-blocks.rst
+ programming-model-dcn.rst
mpo-overview.rst
dc-debug.rst
display-contributing.rst
diff --git a/Documentation/gpu/amdgpu/display/programming-model-dcn.rst b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst
new file mode 100644
index 000000000000..c1b48d49fb0b
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst
@@ -0,0 +1,162 @@
+====================
+DC Programming Model
+====================
+
+In the :ref:`Display Core Next (DCN) <dcn_overview>` and :ref:`DCN Block
+<dcn_blocks>` pages, you learned about the hardware components and how they
+interact with each other. On this page, the focus is shifted to the display
+code architecture. Hence, it is reasonable to remind the reader that the code
+in DC is shared with other OSes; for this reason, DC provides a set of
+abstractions and operations to connect different APIs with the hardware
+configuration. See DC as a service available for a Display Manager (amdgpu_dm)
+to access and configure DCN/DCE hardware (DCE is also part of DC, but for
+simplicity's sake, this documentation only examines DCN).
+
+.. note::
+ For this page, we will use the term GPU to refers to dGPU and APU.
+
+Overview
+========
+
+From the display hardware perspective, it is plausible to expect that if a
+problem is well-defined, it will probably be implemented at the hardware level.
+On the other hand, when there are multiple ways of achieving something without
+a very well-defined scope, the solution is usually implemented as a policy at
+the DC level. In other words, some policies are defined in the DC core
+(resource management, power optimization, image quality, etc.), and the others
+implemented in hardware are enabled via DC configuration.
+
+In terms of hardware management, DCN has multiple instances of the same block
+(e.g., HUBP, DPP, MPC, etc), and during the driver execution, it might be
+necessary to use some of these instances. The core has policies in place for
+handling those instances. Regarding resource management, the DC objective is
+quite simple: minimize the hardware shuffle when the driver performs some
+actions. When the state changes from A to B, the transition is considered
+easier to maneuver if the hardware resource is still used for the same set of
+driver objects. Usually, adding and removing a resource to a `pipe_ctx` (more
+details below) is not a problem; however, moving a resource from one `pipe_ctx`
+to another should be avoided.
+
+Another area of influence for DC is power optimization, which has a myriad of
+arrangement possibilities. In some way, just displaying an image via DCN should
+be relatively straightforward; however, showing it with the best power
+footprint is more desirable, but it has many associated challenges.
+Unfortunately, there is no straight-forward analytic way to determine if a
+configuration is the best one for the context due to the enormous variety of
+variables related to this problem (e.g., many different DCN/DCE hardware
+versions, different displays configurations, etc.) for this reason DC
+implements a dedicated library for trying some configuration and verify if it
+is possible to support it or not. This type of policy is extremely complex to
+create and maintain, and amdgpu driver relies on Display Mode Library (DML) to
+generate the best decisions.
+
+In summary, DC must deal with the complexity of handling multiple scenarios and
+determine policies to manage them. All of the above information is conveyed to
+give the reader some idea about the complexity of driving a display from the
+driver's perspective. This page hopes to allow the reader to better navigate
+over the amdgpu display code.
+
+Display Driver Architecture Overview
+====================================
+
+The diagram below provides an overview of the display driver architecture;
+notice it illustrates the software layers adopted by DC:
+
+.. kernel-figure:: dc-components.svg
+
+The first layer of the diagram is the high-level DC API represented by the
+`dc.h` file; below it are two big blocks represented by Core and Link. Next is
+the hardware configuration block; the main file describing it is
+the`hw_sequencer.h`, where the implementation of the callbacks can be found in
+the hardware sequencer folder. Almost at the end, you can see the block level
+API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
+DPP, MPC, OPTC, etc. Notice on the left side of the diagram that we have a
+different set of layers representing the interaction with the DMUB
+microcontroller.
+
+Basic Objects
+-------------
+
+The below diagram outlines the basic display objects. In particular, pay
+attention to the names in the boxes since they represent a data structure in
+the driver:
+
+.. kernel-figure:: dc-arch-overview.svg
+
+Let's start with the central block in the image, `dc`. The `dc` struct is
+initialized per GPU; for example, one GPU has one `dc` instance, two GPUs have
+two `dc` instances, and so forth. In other words we have one 'dc' per 'amdgpu'
+instance. In some ways, this object behaves like the `Singleton` pattern.
+
+After the `dc` block in the diagram, you can see the `dc_link` component, which
+is a low-level abstraction for the connector. One interesting aspect of the
+image is that connectors are not part of the DCN block; they are defined by the
+platform/board and not by the SoC. The `dc_link` struct is the high-level data
+container with information such as connected sinks, connection status, signal
+types, etc. After `dc_link`, there is the `dc_sink`, which is the object that
+represents the connected display.
+
+.. note::
+ For historical reasons, we used the name `dc_link`, which gives the
+ wrong impression that this abstraction only deals with physical connections
+ that the developer can easily manipulate. However, this also covers
+ conections like eDP or cases where the output is connected to other devices.
+
+There are two structs that are not represented in the diagram since they were
+elaborated in the DCN overview page (check the DCN block diagram :ref:`Display
+Core Next (DCN) <dcn_overview>`); still, it is worth bringing back for this
+overview which is `dc_stream` and `dc_state`. The `dc_stream` stores many
+properties associated with the data transmission, but most importantly, it
+represents the data flow from the connector to the display. Next we have
+`dc_state`, which represents the logic state within the hardware at the moment;
+`dc_state` is composed of `dc_stream` and `dc_plane`. The `dc_stream` is the DC
+version of `drm_crtc` and represents the post-blending pipeline.
+
+Speaking of the `dc_plane` data structure (first part of the diagram), you can
+think about it as an abstraction similar to `drm_plane` that represents the
+pre-blending portion of the pipeline. This image was probably processed by GFX
+and is ready to be composited under a `dc_stream`. Normally, the driver may
+have one or more `dc_plane` connected to the same `dc_stream`, which defines a
+composition at the DC level.
+
+Basic Operations
+----------------
+
+Now that we have covered the basic objects, it is time to examine some of the
+basic hardware/software operations. Let's start with the `dc_create()`
+function, which directly works with the `dc` data struct; this function behaves
+like a constructor responsible for the basic software initialization and
+preparing for enabling other parts of the API. It is important to highlight
+that this operation does not touch any hardware configuration; it is only a
+software initialization.
+
+Next, we have the `dc_hardware_init()`, which also relies on the `dc` data
+struct. Its main function is to put the hardware in a valid state. It is worth
+highlighting that the hardware might initialize in an unknown state, and it is
+a requirement to put it in a valid state; this function has multiple callbacks
+for the hardware-specific initialization, whereas `dc_hardware_init` does the
+hardware initialization and is the first point where we touch hardware.
+
+The `dc_get_link_at_index` is an operation that depends on the `dc_link` data
+structure. This function retrieves and enumerates all the `dc_links` available
+on the device; this is required since this information is not part of the SoC
+definition but depends on the board configuration. As soon as the `dc_link` is
+initialized, it is useful to figure out if any of them are already connected to
+the display by using the `dc_link_detect()` function. After the driver figures
+out if any display is connected to the device, the challenging phase starts:
+configuring the monitor to show something. Nonetheless, dealing with the ideal
+configuration is not a DC task since this is the Display Manager (`amdgpu_dm`)
+responsibility which in turn is responsible for dealing with the atomic
+commits. The only interface DC provides to the configuration phase is the
+function `dc_validate_with_context` that receives the configuration information
+and, based on that, validates whether the hardware can support it or not. It is
+important to add that even if the display supports some specific configuration,
+it does not mean the DCN hardware can support it.
+
+After the DM and DC agree upon the configuration, the stream configuration
+phase starts. This task activates one or more `dc_stream` at this phase, and in
+the best-case scenario, you might be able to turn the display on with a black
+screen (it does not show anything yet since it does not have any plane
+associated with it). The final step would be to call the
+`dc_update_planes_and_stream,` which will add or remove planes.
+
--
2.45.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] Documentation/gpu: Document how to narrow down display issues
2024-10-17 3:34 ` [PATCH 1/2] Documentation/gpu: Document how to narrow down display issues Rodrigo Siqueira
@ 2024-10-17 19:00 ` Mario Limonciello
0 siblings, 0 replies; 5+ messages in thread
From: Mario Limonciello @ 2024-10-17 19:00 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Leo Li, Aurabindo Pillai, Hamza Mahfooz, Harry Wentland,
Christian Konig, Alex Deucher
On 10/16/2024 22:34, Rodrigo Siqueira wrote:
> The amdgpu driver is composed of multiple components, each of which can
> be a source of some specific problem that the user/developer can see.
> This commit introduces steps to narrow down and collect display
> information.
>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Mario Limonciello <mario.limonciello@amd.com>
> Cc: Christian Konig <christian.koenig@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> Documentation/gpu/amdgpu/display/dc-debug.rst | 187 ++++++++++++++++++
> 1 file changed, 187 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/display/dc-debug.rst b/Documentation/gpu/amdgpu/display/dc-debug.rst
> index 817631b1dbf3..013f63b271f3 100644
> --- a/Documentation/gpu/amdgpu/display/dc-debug.rst
> +++ b/Documentation/gpu/amdgpu/display/dc-debug.rst
> @@ -2,6 +2,181 @@
> Display Core Debug tools
> ========================
>
> +In this section, you will find helpful information on debugging the amdgpu
> +driver from the display perspective. This page introduces debug mechanisms and
> +procedures to help you identify if some issues are related to display code.
> +
> +Narrow down display issues
> +==========================
> +
> +Since the display is the driver's visual component, it is common to see users
> +reporting issues as a display when another component causes the problem. This
> +section equips users to determine if a specific issue was caused by the display
> +component or another part of the driver.
> +
> +DC dmesg important messages
> +---------------------------
> +
> +The dmesg log is the first source of information to be checked, and amdgpu
> +takes advantage of this feature by logging some valuable information. When
> +looking for the issues associated with amdgpu, remember that each component of
> +the driver (e.g., smu, PSP, dm, etc.) is loaded one by one, and this
> +information can be found in the dmesg log. In this sense, look for the part of
> +the log that looks like the below log snippet::
> +
> + [ 4.254295] [drm] initializing kernel modesetting (IP DISCOVERY 0x1002:0x744C 0x1002:0x0E3B 0xC8).
> + [ 4.254718] [drm] register mmio base: 0xFCB00000
> + [ 4.254918] [drm] register mmio size: 1048576
> + [ 4.260095] [drm] add ip block number 0 <soc21_common>
> + [ 4.260318] [drm] add ip block number 1 <gmc_v11_0>
> + [ 4.260510] [drm] add ip block number 2 <ih_v6_0>
> + [ 4.260696] [drm] add ip block number 3 <psp>
> + [ 4.260878] [drm] add ip block number 4 <smu>
> + [ 4.261057] [drm] add ip block number 5 <dm>
> + [ 4.261231] [drm] add ip block number 6 <gfx_v11_0>
> + [ 4.261402] [drm] add ip block number 7 <sdma_v6_0>
> + [ 4.261568] [drm] add ip block number 8 <vcn_v4_0>
> + [ 4.261729] [drm] add ip block number 9 <jpeg_v4_0>
> + [ 4.261887] [drm] add ip block number 10 <mes_v11_0>
> +
> +From the above example, you can see the line that reports that `<dm>`,
> +(**Display Manager**), was loaded, which means that display can be part of the
> +issue. If you do not see that line, something else might have failed before
> +amdgpu loads the display component, indicating that we don't have a
> +display issue.
> +
> +After you identified that the DM was loaded correctly, you can check for the
> +display version of the hardware in use, which can be retrieved from the dmesg
> +log with the command::
> +
> + dmesg | grep -i 'display core'
> +
> +This command shows a message that looks like this::
> +
> + [ 4.655828] [drm] Display Core v3.2.285 initialized on DCN 3.2
> +
> +This message has two key pieces of information:
> +
> +* **The DC version (e.g., v3.2.285)**: Display developers release a new DC version
> + every week, and this information can be advantageous in a situation where a
> + user/developer must find a good point versus a bad point based on a tested
> + version of the display code. Remember from page :ref:`Display Core <amdgpu-display-core>`,
> + that every week the new patches for display are heavily tested with IGT and
> + manual tests.
> +* **The DCN version (e.g., DCN 3.2)**: The DCN block is associated with the
> + hardware generation, and the DCN version conveys the hardware generation that
> + the driver is currently running. This information helps to narrow down the
> + code debug area since each DCN version has its files in the DC folder per DCN
> + component (from the example, the developer might want to focus on
> + files/folders/functions/structs with the dcn32 label might be executed).
> + However, keep in mind that DC reuses code across different DCN versions; for
> + example, it is expected to have some callbacks set in one DCN that are the same
> + as those from another DCN. In summary, use the DCN version just as a guide.
> +
> +From the dmesg file, it is also possible to get the ATOM bios code by using::
> +
> + dmesg | grep -i 'ATOM BIOS'
> +
> +Which generates an output that looks like this::
> +
> + [ 4.274534] amdgpu: ATOM BIOS: 113-D7020100-102
> +
> +This type of information is useful to be reported.
> +
> +Avoid loading display core
> +--------------------------
> +
> +Sometimes, it might be hard to figure out which part of the driver is causing
> +the issue; if you suspect that the display is not part of the problem and your
> +bug scenario is simple (e.g., some desktop configuration) you can try to remove
> +the display component from the equation. First, you need to identify `dm` ID
> +from the dmesg log; for example, search for the following log::
> +
> + [ 4.254295] [drm] initializing kernel modesetting (IP DISCOVERY 0x1002:0x744C 0x1002:0x0E3B 0xC8).
> + [..]
> + [ 4.260095] [drm] add ip block number 0 <soc21_common>
> + [ 4.260318] [drm] add ip block number 1 <gmc_v11_0>
> + [..]
> + [ 4.261057] [drm] add ip block number 5 <dm>
> +
> +Notice from the above example that the `dm` id is 5 for this specific hardware.
> +Next, you need to run the following binary operation to identify the IP block
> +mask::
> +
> + 0xffffffff & ~(1 << [DM ID])
> +
> +From our example the IP mask is::
> +
> + 0xffffffff & ~(1 << 5) = 0xffffffdf
> +
> +Finally, to disable DC, you just need to set the below parameter in your
> +bootloader::
> +
> + amdgpu.ip_block_mask = 0xffffffdf
> +
> +If you can boot your system with the DC disabled and still see the issue, it
> +means you can rule DC out of the equation. However, if the bug disappears, you
> +still need to consider the DC part of the problem and keep narrowing down the
> +issue. In some scenarios, disabling DC is impossible since it might be
> +necessary to use the display component to reproduce the issue (e.g., play a
> +game).
> +
> +**Note: This will probably lead to the absence of a display output.**
> +
> +Display flickering
> +------------------
> +
> +Display flickering might have multiple causes; one is the lack of proper power
> +to the GPU or problems in the DPM switches. A good first generic verification
> +is to set the GPU to use high voltage::
> +
> + bash -c "echo high > /sys/class/drm/card0/device/power_dpm_force_performance_level"
> +
> +The above command sets the GPU/APU to use the maximum power allowed which
> +disables DPM switches. If forcing DPM levels high does not fix the issue, it
> +is less likely that the issue is related to power management. If the issue
> +disappears, there is a good chance that other components might be involved, and
> +the display should not be ignored since this could be a DPM issues. From the
> +display side, if the power increase fixes the issue, it is worth debugging the
> +clock configuration and the pipe split police used in the specific
> +configuration.
> +
> +Display artifacts
> +-----------------
> +
> +Users may see some screen artifacts that can be categorized into two different
> +types: localized artifacts and general artifacts. The localized artifacts
> +happen in some specific areas, such as around the UI window corners; if you see
> +this type of issue, there is a considerable chance that you have a userspace
> +problem, likely Mesa or similar. The general artifacts usually happen on the
> +entire screen. They might be caused by a misconfiguration at the driver level
> +of the display parameters, but the userspace might also cause this issue. One
> +way to identify the source of the problem is to take a screenshot or make a
> +desktop video capture when the problem happens; after checking the
> +screenshot/video recording, if you don't see any of the artifacts, it means
> +that the issue is likely on the the driver side. If you can still see the
> +problem in the data collected, it is an issue that probably happened during
> +rendering, and the display code just got the framebuffer already corrupted.
> +
> +Disabling/Enabling specific features
> +====================================
> +
> +DC has a struct named `dc_debug_options`, which is statically initialized by
> +all DCE/DCN components based on the specific hardware characteristic. This
> +structure usually facilitates the bring-up phase since developers can start
> +with many disabled features and enable them individually. This is also an
> +important debug feature since users can change it when debugging specific
> +issues.
> +
> +For example, dGPU users sometimes see a problem where a horizontal fillet of
> +flickering happens in some specific part of the screen. This could be an
> +indication of Sub-Viewport issues; after the users identified the target DCN,
> +they can set the `force_disable_subvp` field to true in the statically
> +initialized version of `dc_debug_options` to see if the issue gets fixed. Along
> +the same lines, users/developers can also try to turn off `fams2_config` and
> +`enable_single_display_2to1_odm_policy`. In summary, the `dc_debug_options` is
> +an interesting form for identifying the problem.
> +
> DC Visual Confirmation
> ======================
>
> @@ -76,6 +251,18 @@ change in real-time by using something like::
> When reporting a bug related to DC, consider attaching this log before and
> after you reproduce the bug.
>
> +Collect Firmware information
> +============================
> +
> +When reporting issues, it is important to have the firmware information since
> +it can be helpful for debugging purposes. To get all the firmware information,
> +use the command::
> +
> + cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
> +
> +From the display perspective, pay attention to the firmware of the DMCU and
> +DMCUB.
> +
> DMUB Firmware Debug
> ===================
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] Documentation/gpu/amdgpu: Add programming model for DCN
2024-10-17 3:34 ` [PATCH 2/2] Documentation/gpu/amdgpu: Add programming model for DCN Rodrigo Siqueira
@ 2024-10-23 18:12 ` Harry Wentland
0 siblings, 0 replies; 5+ messages in thread
From: Harry Wentland @ 2024-10-23 18:12 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Leo Li, Aurabindo Pillai, Hamza Mahfooz, Mario Limonciello,
Christian Konig, Alex Deucher
On 2024-10-16 23:34, Rodrigo Siqueira wrote:
> One of the challenges to contributing to the display code is the
> complexity of the DC component. This commit adds a documentation page
> that discusses the programming model used by DCN and an overview of how
> the display code is organized.
>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Mario Limonciello <mario.limonciello@amd.com>
> Cc: Christian Konig <christian.koenig@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Series is
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../gpu/amdgpu/display/dc-arch-overview.svg | 731 +++++++++++++++++
> .../gpu/amdgpu/display/dc-components.svg | 732 ++++++++++++++++++
> .../gpu/amdgpu/display/dcn-blocks.rst | 2 +
> .../gpu/amdgpu/display/dcn-overview.rst | 2 +
> Documentation/gpu/amdgpu/display/index.rst | 1 +
> .../amdgpu/display/programming-model-dcn.rst | 162 ++++
> 6 files changed, 1630 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/display/dc-arch-overview.svg
> create mode 100644 Documentation/gpu/amdgpu/display/dc-components.svg
> create mode 100644 Documentation/gpu/amdgpu/display/programming-model-dcn.rst
>
> diff --git a/Documentation/gpu/amdgpu/display/dc-arch-overview.svg b/Documentation/gpu/amdgpu/display/dc-arch-overview.svg
> new file mode 100644
> index 000000000000..23394931cf26
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/dc-arch-overview.svg
> @@ -0,0 +1,731 @@
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> + style="font-size:4.36501px;text-align:center;text-anchor:middle;stroke-width:0.163688"
> + id="tspan1066">(dc/dc_dmub_srv.h)</tspan></text>
> + </g>
> +</svg>
> diff --git a/Documentation/gpu/amdgpu/display/dcn-blocks.rst b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
> index 5e34366f6dbe..756957128dad 100644
> --- a/Documentation/gpu/amdgpu/display/dcn-blocks.rst
> +++ b/Documentation/gpu/amdgpu/display/dcn-blocks.rst
> @@ -1,3 +1,5 @@
> +.. _dcn_blocks:
> +
> ==========
> DCN Blocks
> ==========
> diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> index 9fea6500448b..eb54a6802e04 100644
> --- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
> +++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
> @@ -1,3 +1,5 @@
> +.. _dcn_overview:
> +
> =======================
> Display Core Next (DCN)
> =======================
> diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
> index f0c342e00a39..bd2d797c123e 100644
> --- a/Documentation/gpu/amdgpu/display/index.rst
> +++ b/Documentation/gpu/amdgpu/display/index.rst
> @@ -90,6 +90,7 @@ table of content:
> display-manager.rst
> dcn-overview.rst
> dcn-blocks.rst
> + programming-model-dcn.rst
> mpo-overview.rst
> dc-debug.rst
> display-contributing.rst
> diff --git a/Documentation/gpu/amdgpu/display/programming-model-dcn.rst b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst
> new file mode 100644
> index 000000000000..c1b48d49fb0b
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst
> @@ -0,0 +1,162 @@
> +====================
> +DC Programming Model
> +====================
> +
> +In the :ref:`Display Core Next (DCN) <dcn_overview>` and :ref:`DCN Block
> +<dcn_blocks>` pages, you learned about the hardware components and how they
> +interact with each other. On this page, the focus is shifted to the display
> +code architecture. Hence, it is reasonable to remind the reader that the code
> +in DC is shared with other OSes; for this reason, DC provides a set of
> +abstractions and operations to connect different APIs with the hardware
> +configuration. See DC as a service available for a Display Manager (amdgpu_dm)
> +to access and configure DCN/DCE hardware (DCE is also part of DC, but for
> +simplicity's sake, this documentation only examines DCN).
> +
> +.. note::
> + For this page, we will use the term GPU to refers to dGPU and APU.
> +
> +Overview
> +========
> +
> +From the display hardware perspective, it is plausible to expect that if a
> +problem is well-defined, it will probably be implemented at the hardware level.
> +On the other hand, when there are multiple ways of achieving something without
> +a very well-defined scope, the solution is usually implemented as a policy at
> +the DC level. In other words, some policies are defined in the DC core
> +(resource management, power optimization, image quality, etc.), and the others
> +implemented in hardware are enabled via DC configuration.
> +
> +In terms of hardware management, DCN has multiple instances of the same block
> +(e.g., HUBP, DPP, MPC, etc), and during the driver execution, it might be
> +necessary to use some of these instances. The core has policies in place for
> +handling those instances. Regarding resource management, the DC objective is
> +quite simple: minimize the hardware shuffle when the driver performs some
> +actions. When the state changes from A to B, the transition is considered
> +easier to maneuver if the hardware resource is still used for the same set of
> +driver objects. Usually, adding and removing a resource to a `pipe_ctx` (more
> +details below) is not a problem; however, moving a resource from one `pipe_ctx`
> +to another should be avoided.
> +
> +Another area of influence for DC is power optimization, which has a myriad of
> +arrangement possibilities. In some way, just displaying an image via DCN should
> +be relatively straightforward; however, showing it with the best power
> +footprint is more desirable, but it has many associated challenges.
> +Unfortunately, there is no straight-forward analytic way to determine if a
> +configuration is the best one for the context due to the enormous variety of
> +variables related to this problem (e.g., many different DCN/DCE hardware
> +versions, different displays configurations, etc.) for this reason DC
> +implements a dedicated library for trying some configuration and verify if it
> +is possible to support it or not. This type of policy is extremely complex to
> +create and maintain, and amdgpu driver relies on Display Mode Library (DML) to
> +generate the best decisions.
> +
> +In summary, DC must deal with the complexity of handling multiple scenarios and
> +determine policies to manage them. All of the above information is conveyed to
> +give the reader some idea about the complexity of driving a display from the
> +driver's perspective. This page hopes to allow the reader to better navigate
> +over the amdgpu display code.
> +
> +Display Driver Architecture Overview
> +====================================
> +
> +The diagram below provides an overview of the display driver architecture;
> +notice it illustrates the software layers adopted by DC:
> +
> +.. kernel-figure:: dc-components.svg
> +
> +The first layer of the diagram is the high-level DC API represented by the
> +`dc.h` file; below it are two big blocks represented by Core and Link. Next is
> +the hardware configuration block; the main file describing it is
> +the`hw_sequencer.h`, where the implementation of the callbacks can be found in
> +the hardware sequencer folder. Almost at the end, you can see the block level
> +API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
> +DPP, MPC, OPTC, etc. Notice on the left side of the diagram that we have a
> +different set of layers representing the interaction with the DMUB
> +microcontroller.
> +
> +Basic Objects
> +-------------
> +
> +The below diagram outlines the basic display objects. In particular, pay
> +attention to the names in the boxes since they represent a data structure in
> +the driver:
> +
> +.. kernel-figure:: dc-arch-overview.svg
> +
> +Let's start with the central block in the image, `dc`. The `dc` struct is
> +initialized per GPU; for example, one GPU has one `dc` instance, two GPUs have
> +two `dc` instances, and so forth. In other words we have one 'dc' per 'amdgpu'
> +instance. In some ways, this object behaves like the `Singleton` pattern.
> +
> +After the `dc` block in the diagram, you can see the `dc_link` component, which
> +is a low-level abstraction for the connector. One interesting aspect of the
> +image is that connectors are not part of the DCN block; they are defined by the
> +platform/board and not by the SoC. The `dc_link` struct is the high-level data
> +container with information such as connected sinks, connection status, signal
> +types, etc. After `dc_link`, there is the `dc_sink`, which is the object that
> +represents the connected display.
> +
> +.. note::
> + For historical reasons, we used the name `dc_link`, which gives the
> + wrong impression that this abstraction only deals with physical connections
> + that the developer can easily manipulate. However, this also covers
> + conections like eDP or cases where the output is connected to other devices.
> +
> +There are two structs that are not represented in the diagram since they were
> +elaborated in the DCN overview page (check the DCN block diagram :ref:`Display
> +Core Next (DCN) <dcn_overview>`); still, it is worth bringing back for this
> +overview which is `dc_stream` and `dc_state`. The `dc_stream` stores many
> +properties associated with the data transmission, but most importantly, it
> +represents the data flow from the connector to the display. Next we have
> +`dc_state`, which represents the logic state within the hardware at the moment;
> +`dc_state` is composed of `dc_stream` and `dc_plane`. The `dc_stream` is the DC
> +version of `drm_crtc` and represents the post-blending pipeline.
> +
> +Speaking of the `dc_plane` data structure (first part of the diagram), you can
> +think about it as an abstraction similar to `drm_plane` that represents the
> +pre-blending portion of the pipeline. This image was probably processed by GFX
> +and is ready to be composited under a `dc_stream`. Normally, the driver may
> +have one or more `dc_plane` connected to the same `dc_stream`, which defines a
> +composition at the DC level.
> +
> +Basic Operations
> +----------------
> +
> +Now that we have covered the basic objects, it is time to examine some of the
> +basic hardware/software operations. Let's start with the `dc_create()`
> +function, which directly works with the `dc` data struct; this function behaves
> +like a constructor responsible for the basic software initialization and
> +preparing for enabling other parts of the API. It is important to highlight
> +that this operation does not touch any hardware configuration; it is only a
> +software initialization.
> +
> +Next, we have the `dc_hardware_init()`, which also relies on the `dc` data
> +struct. Its main function is to put the hardware in a valid state. It is worth
> +highlighting that the hardware might initialize in an unknown state, and it is
> +a requirement to put it in a valid state; this function has multiple callbacks
> +for the hardware-specific initialization, whereas `dc_hardware_init` does the
> +hardware initialization and is the first point where we touch hardware.
> +
> +The `dc_get_link_at_index` is an operation that depends on the `dc_link` data
> +structure. This function retrieves and enumerates all the `dc_links` available
> +on the device; this is required since this information is not part of the SoC
> +definition but depends on the board configuration. As soon as the `dc_link` is
> +initialized, it is useful to figure out if any of them are already connected to
> +the display by using the `dc_link_detect()` function. After the driver figures
> +out if any display is connected to the device, the challenging phase starts:
> +configuring the monitor to show something. Nonetheless, dealing with the ideal
> +configuration is not a DC task since this is the Display Manager (`amdgpu_dm`)
> +responsibility which in turn is responsible for dealing with the atomic
> +commits. The only interface DC provides to the configuration phase is the
> +function `dc_validate_with_context` that receives the configuration information
> +and, based on that, validates whether the hardware can support it or not. It is
> +important to add that even if the display supports some specific configuration,
> +it does not mean the DCN hardware can support it.
> +
> +After the DM and DC agree upon the configuration, the stream configuration
> +phase starts. This task activates one or more `dc_stream` at this phase, and in
> +the best-case scenario, you might be able to turn the display on with a black
> +screen (it does not show anything yet since it does not have any plane
> +associated with it). The final step would be to call the
> +`dc_update_planes_and_stream,` which will add or remove planes.
> +
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2024-10-17 3:34 [PATCH 0/2] Expand Display code documentation Rodrigo Siqueira
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2024-10-17 19:00 ` Mario Limonciello
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