* [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size
@ 2025-02-28 13:24 David Rosca
2025-02-28 13:24 ` [PATCH 2/4] drm/amdgpu: Fix JPEG video caps max size for navi1x and raven David Rosca
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: David Rosca @ 2025-02-28 13:24 UTC (permalink / raw)
To: amd-gfx; +Cc: David Rosca
1920x1088 is the maximum supported resolution.
Signed-off-by: David Rosca <david.rosca@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 18 ++++++++---------
drivers/gpu/drm/amd/amdgpu/vi.c | 36 ++++++++++++++++-----------------
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 8068f384f56c..a18e6fb9fa3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -78,10 +78,10 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = {
/* Navi1x */
static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
@@ -104,10 +104,10 @@ static const struct amdgpu_video_codecs sc_video_codecs_encode = {
};
static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
@@ -115,10 +115,10 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[]
};
static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 3bbbb75242d9..9b3510e53112 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -167,16 +167,16 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
{
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 3,
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 5,
},
{
@@ -188,9 +188,9 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 4,
},
};
@@ -206,16 +206,16 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
{
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 3,
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 5,
},
{
@@ -227,9 +227,9 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
},
{
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
+ .max_width = 1920,
+ .max_height = 1088,
+ .max_pixels_per_frame = 1920 * 1088,
.max_level = 4,
},
{
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] drm/amdgpu: Fix JPEG video caps max size for navi1x and raven
2025-02-28 13:24 [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size David Rosca
@ 2025-02-28 13:24 ` David Rosca
2025-02-28 13:24 ` [PATCH 3/4] drm/amdgpu: Remove JPEG from vega and carrizo video caps David Rosca
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: David Rosca @ 2025-02-28 13:24 UTC (permalink / raw)
To: amd-gfx; +Cc: David Rosca
8192x8192 is the maximum supported resolution.
Signed-off-by: David Rosca <david.rosca@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a18e6fb9fa3f..32b824c3658f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -83,7 +83,7 @@ static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8732f766947e..f01176da8b3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -124,7 +124,7 @@ static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
};
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] drm/amdgpu: Remove JPEG from vega and carrizo video caps
2025-02-28 13:24 [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size David Rosca
2025-02-28 13:24 ` [PATCH 2/4] drm/amdgpu: Fix JPEG video caps max size for navi1x and raven David Rosca
@ 2025-02-28 13:24 ` David Rosca
2025-02-28 13:24 ` [PATCH 4/4] drm/amdgpu: Update SRIOV video codec caps David Rosca
2025-02-28 14:21 ` [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size Alex Deucher
3 siblings, 0 replies; 7+ messages in thread
From: David Rosca @ 2025-02-28 13:24 UTC (permalink / raw)
To: amd-gfx; +Cc: David Rosca
JPEG is only supported for VCN1+.
Signed-off-by: David Rosca <david.rosca@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 -
drivers/gpu/drm/amd/amdgpu/vi.c | 7 -------
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f01176da8b3e..d5d3f9e945c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -107,7 +107,6 @@ static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
};
static const struct amdgpu_video_codecs vega_video_codecs_decode =
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9b3510e53112..86d8bc10d90a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -239,13 +239,6 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
.max_pixels_per_frame = 4096 * 4096,
.max_level = 186,
},
- {
- .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
- .max_width = 4096,
- .max_height = 4096,
- .max_pixels_per_frame = 4096 * 4096,
- .max_level = 0,
- },
};
static const struct amdgpu_video_codecs cz_video_codecs_decode =
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] drm/amdgpu: Update SRIOV video codec caps
2025-02-28 13:24 [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size David Rosca
2025-02-28 13:24 ` [PATCH 2/4] drm/amdgpu: Fix JPEG video caps max size for navi1x and raven David Rosca
2025-02-28 13:24 ` [PATCH 3/4] drm/amdgpu: Remove JPEG from vega and carrizo video caps David Rosca
@ 2025-02-28 13:24 ` David Rosca
2025-02-28 14:21 ` [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size Alex Deucher
3 siblings, 0 replies; 7+ messages in thread
From: David Rosca @ 2025-02-28 13:24 UTC (permalink / raw)
To: amd-gfx; +Cc: David Rosca
There have been multiple fixes to the video caps that are missing for
SRIOV. Update the SRIOV caps with correct values.
Signed-off-by: David Rosca <david.rosca@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 16 ++++++++--------
drivers/gpu/drm/amd/amdgpu/soc21.c | 10 ++--------
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 32b824c3658f..50e77d9b30af 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -141,23 +141,23 @@ static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
};
static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};
static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index dd5d04c068f9..ad36c96478a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -117,23 +117,17 @@ static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
};
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
};
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size
2025-02-28 13:24 [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size David Rosca
` (2 preceding siblings ...)
2025-02-28 13:24 ` [PATCH 4/4] drm/amdgpu: Update SRIOV video codec caps David Rosca
@ 2025-02-28 14:21 ` Alex Deucher
2025-02-28 15:09 ` David Rosca
3 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2025-02-28 14:21 UTC (permalink / raw)
To: David Rosca; +Cc: amd-gfx
On Fri, Feb 28, 2025 at 8:34 AM David Rosca <david.rosca@amd.com> wrote:
>
> 1920x1088 is the maximum supported resolution.
>
> Signed-off-by: David Rosca <david.rosca@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 18 ++++++++---------
> drivers/gpu/drm/amd/amdgpu/vi.c | 36 ++++++++++++++++-----------------
I think soc15.c needs similar fixes? Also, I think we need to bump
the driver version so mesa knows what kernel version has the proper
limits.
Alex
> 2 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 8068f384f56c..a18e6fb9fa3f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -78,10 +78,10 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = {
>
> /* Navi1x */
> static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
> @@ -104,10 +104,10 @@ static const struct amdgpu_video_codecs sc_video_codecs_encode = {
> };
>
> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
> @@ -115,10 +115,10 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[]
> };
>
> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 3bbbb75242d9..9b3510e53112 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -167,16 +167,16 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
> {
> {
> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
> - .max_width = 4096,
> - .max_height = 4096,
> - .max_pixels_per_frame = 4096 * 4096,
> + .max_width = 1920,
> + .max_height = 1088,
> + .max_pixels_per_frame = 1920 * 1088,
> .max_level = 3,
> },
> {
> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
> - .max_width = 4096,
> - .max_height = 4096,
> - .max_pixels_per_frame = 4096 * 4096,
> + .max_width = 1920,
> + .max_height = 1088,
> + .max_pixels_per_frame = 1920 * 1088,
> .max_level = 5,
> },
> {
> @@ -188,9 +188,9 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
> },
> {
> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
> - .max_width = 4096,
> - .max_height = 4096,
> - .max_pixels_per_frame = 4096 * 4096,
> + .max_width = 1920,
> + .max_height = 1088,
> + .max_pixels_per_frame = 1920 * 1088,
> .max_level = 4,
> },
> };
> @@ -206,16 +206,16 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
> {
> {
> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
> - .max_width = 4096,
> - .max_height = 4096,
> - .max_pixels_per_frame = 4096 * 4096,
> + .max_width = 1920,
> + .max_height = 1088,
> + .max_pixels_per_frame = 1920 * 1088,
> .max_level = 3,
> },
> {
> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
> - .max_width = 4096,
> - .max_height = 4096,
> - .max_pixels_per_frame = 4096 * 4096,
> + .max_width = 1920,
> + .max_height = 1088,
> + .max_pixels_per_frame = 1920 * 1088,
> .max_level = 5,
> },
> {
> @@ -227,9 +227,9 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
> },
> {
> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
> - .max_width = 4096,
> - .max_height = 4096,
> - .max_pixels_per_frame = 4096 * 4096,
> + .max_width = 1920,
> + .max_height = 1088,
> + .max_pixels_per_frame = 1920 * 1088,
> .max_level = 4,
> },
> {
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size
2025-02-28 14:21 ` [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size Alex Deucher
@ 2025-02-28 15:09 ` David Rosca
2025-03-07 15:57 ` Dong, Ruijing
0 siblings, 1 reply; 7+ messages in thread
From: David Rosca @ 2025-02-28 15:09 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx
On 28. 02. 25 15:21, Alex Deucher wrote:
> On Fri, Feb 28, 2025 at 8:34 AM David Rosca <david.rosca@amd.com> wrote:
>> 1920x1088 is the maximum supported resolution.
>>
>> Signed-off-by: David Rosca <david.rosca@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/nv.c | 18 ++++++++---------
>> drivers/gpu/drm/amd/amdgpu/vi.c | 36 ++++++++++++++++-----------------
> I think soc15.c needs similar fixes?
Fixed in v2.
> Also, I think we need to bump
> the driver version so mesa knows what kernel version has the proper
> limits.
I think for now we can ignore the kernel caps in Mesa for these codecs
as the maximum size is the same for all asics. We can later switch to
kernel caps again, no need to bump the version just for this.
David
>
> Alex
>
>> 2 files changed, 27 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
>> index 8068f384f56c..a18e6fb9fa3f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -78,10 +78,10 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = {
>>
>> /* Navi1x */
>> static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
>> @@ -104,10 +104,10 @@ static const struct amdgpu_video_codecs sc_video_codecs_encode = {
>> };
>>
>> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
>> @@ -115,10 +115,10 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[]
>> };
>>
>> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
>> index 3bbbb75242d9..9b3510e53112 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
>> @@ -167,16 +167,16 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
>> {
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 3,
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 5,
>> },
>> {
>> @@ -188,9 +188,9 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 4,
>> },
>> };
>> @@ -206,16 +206,16 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
>> {
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 3,
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 5,
>> },
>> {
>> @@ -227,9 +227,9 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 4,
>> },
>> {
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size
2025-02-28 15:09 ` David Rosca
@ 2025-03-07 15:57 ` Dong, Ruijing
0 siblings, 0 replies; 7+ messages in thread
From: Dong, Ruijing @ 2025-03-07 15:57 UTC (permalink / raw)
To: Rosca, David, Alex Deucher; +Cc: amd-gfx@lists.freedesktop.org
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of David Rosca
Sent: Friday, February 28, 2025 10:10 AM
To: Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size
On 28. 02. 25 15:21, Alex Deucher wrote:
> On Fri, Feb 28, 2025 at 8:34 AM David Rosca <david.rosca@amd.com> wrote:
>> 1920x1088 is the maximum supported resolution.
>>
>> Signed-off-by: David Rosca <david.rosca@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/nv.c | 18 ++++++++---------
>> drivers/gpu/drm/amd/amdgpu/vi.c | 36
>> ++++++++++++++++-----------------
> I think soc15.c needs similar fixes?
Fixed in v2.
> Also, I think we need to bump
> the driver version so mesa knows what kernel version has the proper
> limits.
I think for now we can ignore the kernel caps in Mesa for these codecs as the maximum size is the same for all asics. We can later switch to kernel caps again, no need to bump the version just for this.
David
>
> Alex
>
>> 2 files changed, 27 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> b/drivers/gpu/drm/amd/amdgpu/nv.c index 8068f384f56c..a18e6fb9fa3f
>> 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -78,10 +78,10 @@ static const struct amdgpu_video_codecs
>> nv_video_codecs_encode = {
>>
>> /* Navi1x */
>> static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> + 1920, 1088, 5)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920,
>> + 1088, 4)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
>> 8192, 4352, 0)}, @@ -104,10 +104,10 @@ static const struct amdgpu_video_codecs sc_video_codecs_encode = {
>> };
>>
>> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> + 1920, 1088, 5)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920,
>> + 1088, 4)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
>> 8192, 4352, 0)}, @@ -115,10 +115,10 @@ static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[]
>> };
>>
>> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> + 1920, 1088, 5)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
>> - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
>> + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920,
>> + 1088, 4)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
>> {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
>> 8192, 4352, 0)}, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
>> b/drivers/gpu/drm/amd/amdgpu/vi.c index 3bbbb75242d9..9b3510e53112
>> 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
>> @@ -167,16 +167,16 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
>> {
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 3,
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 5,
>> },
>> {
>> @@ -188,9 +188,9 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 4,
>> },
>> };
>> @@ -206,16 +206,16 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
>> {
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 3,
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 5,
>> },
>> {
>> @@ -227,9 +227,9 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
>> },
>> {
>> .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
>> - .max_width = 4096,
>> - .max_height = 4096,
>> - .max_pixels_per_frame = 4096 * 4096,
>> + .max_width = 1920,
>> + .max_height = 1088,
>> + .max_pixels_per_frame = 1920 * 1088,
>> .max_level = 4,
>> },
>> {
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-03-07 15:57 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2025-02-28 13:24 [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size David Rosca
2025-02-28 13:24 ` [PATCH 2/4] drm/amdgpu: Fix JPEG video caps max size for navi1x and raven David Rosca
2025-02-28 13:24 ` [PATCH 3/4] drm/amdgpu: Remove JPEG from vega and carrizo video caps David Rosca
2025-02-28 13:24 ` [PATCH 4/4] drm/amdgpu: Update SRIOV video codec caps David Rosca
2025-02-28 14:21 ` [PATCH 1/4] drm/amdgpu: Fix MPEG2, MPEG4 and VC1 video caps max size Alex Deucher
2025-02-28 15:09 ` David Rosca
2025-03-07 15:57 ` Dong, Ruijing
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