From: Alexandre Demers <alexandre.f.demers@gmail.com>
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 18/18] drm/amdgpu: continue cleaning up sid.h and si_enums.h
Date: Fri, 21 Mar 2025 21:47:00 -0400 [thread overview]
Message-ID: <20250322014700.62356-19-alexandre.f.demers@gmail.com> (raw)
In-Reply-To: <20250322014700.62356-1-alexandre.f.demers@gmail.com>
Remove more duplicated defines and move some in sid.h for coherence with
CIK.
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/si_enums.h | 90 +--------------------------
drivers/gpu/drm/amd/amdgpu/sid.h | 16 ++++-
2 files changed, 14 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
index aee3036be30e..6da65778292b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -23,96 +23,15 @@
#ifndef SI_ENUMS_H
#define SI_ENUMS_H
-#define VBLANK_ACK (1 << 4)
-#define VLINE_ACK (1 << 4)
-
-#define CURSOR_WIDTH 64
-#define CURSOR_HEIGHT 64
-
#define PRIORITY_MARK_MASK 0x7fff
#define PRIORITY_OFF (1 << 16)
#define PRIORITY_ALWAYS_ON (1 << 20)
-#define GRPH_ENDIAN_NONE 0
-#define GRPH_ENDIAN_8IN16 1
-#define GRPH_ENDIAN_8IN32 2
-#define GRPH_ENDIAN_8IN64 3
-#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
-#define GRPH_RED_SEL_R 0
-#define GRPH_RED_SEL_G 1
-#define GRPH_RED_SEL_B 2
-#define GRPH_RED_SEL_A 3
-#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
-#define GRPH_GREEN_SEL_G 0
-#define GRPH_GREEN_SEL_B 1
-#define GRPH_GREEN_SEL_A 2
-#define GRPH_GREEN_SEL_R 3
-#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
-#define GRPH_BLUE_SEL_B 0
-#define GRPH_BLUE_SEL_A 1
-#define GRPH_BLUE_SEL_R 2
-#define GRPH_BLUE_SEL_G 3
-#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
-#define GRPH_ALPHA_SEL_A 0
-#define GRPH_ALPHA_SEL_R 1
-#define GRPH_ALPHA_SEL_G 2
-#define GRPH_ALPHA_SEL_B 3
-
-#define GRPH_DEPTH_8BPP 0
-#define GRPH_DEPTH_16BPP 1
-#define GRPH_DEPTH_32BPP 2
-
-#define GRPH_FORMAT_INDEXED 0
-#define GRPH_FORMAT_ARGB1555 0
-#define GRPH_FORMAT_ARGB565 1
-#define GRPH_FORMAT_ARGB4444 2
-#define GRPH_FORMAT_AI88 3
-#define GRPH_FORMAT_MONO16 4
-#define GRPH_FORMAT_BGRA5551 5
-#define GRPH_FORMAT_ARGB8888 0
-#define GRPH_FORMAT_ARGB2101010 1
-#define GRPH_FORMAT_32BPP_DIG 2
-#define GRPH_FORMAT_8B_ARGB2101010 3
-#define GRPH_FORMAT_BGRA1010102 4
-#define GRPH_FORMAT_8B_BGRA1010102 5
-#define GRPH_FORMAT_RGB111110 6
-#define GRPH_FORMAT_BGR101111 7
-
-#define GRPH_ARRAY_LINEAR_GENERAL 0
-#define GRPH_ARRAY_LINEAR_ALIGNED 1
-#define GRPH_ARRAY_1D_TILED_THIN1 2
-#define GRPH_ARRAY_2D_TILED_THIN1 4
-
-#define CURSOR_EN (1 << 0)
-#define CURSOR_MODE(x) (((x) & 0x3) << 8)
-#define CURSOR_MONO 0
-#define CURSOR_24_1 1
-#define CURSOR_24_8_PRE_MULT 2
-#define CURSOR_24_8_UNPRE_MULT 3
-#define CURSOR_2X_MAGNIFY (1 << 16)
-#define CURSOR_FORCE_MC_ON (1 << 20)
-#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
-#define CURSOR_URGENT_ALWAYS 0
-#define CURSOR_URGENT_1_8 1
-#define CURSOR_URGENT_1_4 2
-#define CURSOR_URGENT_3_8 3
-#define CURSOR_URGENT_1_2 4
-#define CURSOR_UPDATE_PENDING (1 << 0)
-#define CURSOR_UPDATE_TAKEN (1 << 1)
-#define CURSOR_UPDATE_LOCK (1 << 16)
-#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
-
-
-#define ES_AND_GS_AUTO 3
-#define RADEON_PACKET_TYPE3 3
-#define CE_PARTITION_BASE 3
-#define BUF_SWAP_32BIT (2 << 16)
-
#define GFX_POWER_STATUS (1 << 1)
#define GFX_CLOCK_STATUS (1 << 2)
#define GFX_LS_STATUS (1 << 3)
-#define RLC_BUSY_STATUS (1 << 0)
+#define RLC_BUSY_STATUS (1 << 0)
#define RLC_PUD(x) ((x) << 0)
#define RLC_PUD_MASK (0xff << 0)
#define RLC_PDD(x) ((x) << 8)
@@ -121,13 +40,6 @@
#define RLC_TTPD_MASK (0xff << 16)
#define RLC_MSD(x) ((x) << 24)
#define RLC_MSD_MASK (0xff << 24)
-#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
-#define WRITE_DATA_DST_SEL(x) ((x) << 8)
-#define EVENT_TYPE(x) ((x) << 0)
-#define EVENT_INDEX(x) ((x) << 8)
-#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
-#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
-#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index 6c6bf2154ce8..494c8ca74e6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -586,6 +586,7 @@
#define DMA_PACKET_POLL_REG_MEM 0xe
#define DMA_PACKET_NOP 0xf
+/* VCE */
#define VCE_STATUS 0x20004
#define VCE_VCPU_CNTL 0x20014
#define VCE_CLK_EN (1 << 0)
@@ -705,9 +706,10 @@
#define GRPH_FORMAT_RGB111110 6
#define GRPH_FORMAT_BGR101111 7
-#define ES_AND_GS_AUTO 3
-#define BUF_SWAP_32BIT (2 << 16)
-
+#define GRPH_ENDIAN_NONE 0
+#define GRPH_ENDIAN_8IN16 1
+#define GRPH_ENDIAN_8IN32 2
+#define GRPH_ENDIAN_8IN64 3
#define GRPH_RED_SEL_R 0
#define GRPH_RED_SEL_G 1
#define GRPH_RED_SEL_B 2
@@ -725,6 +727,14 @@
#define GRPH_ALPHA_SEL_G 2
#define GRPH_ALPHA_SEL_B 3
+#define GRPH_ARRAY_LINEAR_GENERAL 0
+#define GRPH_ARRAY_LINEAR_ALIGNED 1
+#define GRPH_ARRAY_1D_TILED_THIN1 2
+#define GRPH_ARRAY_2D_TILED_THIN1 4
+
+#define ES_AND_GS_AUTO 3
+#define BUF_SWAP_32BIT (2 << 16)
+
/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
// #define CUR_CONTROL 0x1a66
--
2.48.1
next prev parent reply other threads:[~2025-03-22 1:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-22 1:46 [PATCH 00/18] Properly wire defines, shifts and masks in SI and cleanup Alexandre Demers
2025-03-22 1:46 ` [PATCH 01/18] drm/amdgpu: move GFX6 defines into gfx_v6_0.c Alexandre Demers
2025-03-22 1:46 ` [PATCH 02/18] drm/amdgpu: wire up defines, shifts and masks through SI code Alexandre Demers
2025-03-22 1:46 ` [PATCH 03/18] drm/amdgpu: use proper defines, shifts and masks in DCE6 code Alexandre Demers
2025-03-22 1:46 ` [PATCH 04/18] drm/amdgpu: remove PACKET3 duplicated defines from si_enums.h Alexandre Demers
2025-03-22 1:46 ` [PATCH 05/18] drm/admgpu: move si_ih.c away from sid.h defines Alexandre Demers
2025-03-22 1:46 ` [PATCH 06/18] drm/amdgpu: use GRPH_SECONDARY_SURFACE_ADDRESS_MASK with GRPH_SECONDARY_SURFACE_ADDRESS in DCE6 Alexandre Demers
2025-03-22 1:46 ` [PATCH 07/18] drm/amdgpu: move DCE6 away from sid.h and si_enums.h defines Alexandre Demers
2025-03-22 1:46 ` [PATCH 08/18] drm/amdgpu: add missing DMA defines, shifts and masks Alexandre Demers
2025-03-22 1:46 ` [PATCH 09/18] drm/amdgpu: add missing GFX6 defines Alexandre Demers
2025-03-22 1:46 ` [PATCH 10/18] drm/amdgpu: add missing SMU6 defines, shifts and masks Alexandre Demers
2025-03-24 19:03 ` Alex Deucher
2025-03-27 4:21 ` Alexandre Demers
2025-03-22 1:46 ` [PATCH 11/18] drm/pm/legacy-dpm: move SI away from sid.h and si_enums.h Alexandre Demers
2025-03-22 1:46 ` [PATCH 12/18] drm/amdgpu: make GFX6 easier to read Alexandre Demers
2025-03-22 1:46 ` [PATCH 13/18] drm/amdgpu: move si.c away from sid.h Alexandre Demers
2025-03-22 1:46 ` [PATCH 14/18] drm/amdgpu: move si_dma.c away from sid.h and si_enums.h Alexandre Demers
2025-03-22 1:46 ` [PATCH 15/18] drm/amdgpu: huge sid.h cleanup, drop substituted defines Alexandre Demers
2025-03-22 1:46 ` [PATCH 16/18] drm/amdgpu: keep removing sid.h dependency from si_dma.c Alexandre Demers
2025-03-22 1:46 ` [PATCH 17/18] drm/amdgpu: cleanup DCE6 a bit more Alexandre Demers
2025-03-22 1:47 ` Alexandre Demers [this message]
2025-03-22 16:16 ` [PATCH v2 00/18] Properly wire defines, shifts and masks in SI and cleanup Alexandre Demers
2025-03-24 19:26 ` [PATCH " Alex Deucher
-- strict thread matches above, loose matches on Subject: below --
2025-03-17 6:06 Alexandre Demers
2025-03-17 6:07 ` [PATCH 18/18] drm/amdgpu: continue cleaning up sid.h and si_enums.h Alexandre Demers
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