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From: Sasha Levin <sashal@kernel.org>
To: patches@lists.linux.dev, stable@vger.kernel.org
Cc: Alex Deucher <alexander.deucher@amd.com>,
	Rodrigo Siqueira <siqueira@igalia.com>,
	Sasha Levin <sashal@kernel.org>,
	christian.koenig@amd.com, airlied@gmail.com, simona@ffwll.ch,
	sunil.khatri@amd.com, alexandre.f.demers@gmail.com,
	boyuan.zhang@amd.com, kevinyang.wang@amd.com,
	amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH AUTOSEL 6.15 003/110] drm/amdgpu/gfx6: fix CSIB handling
Date: Sun,  1 Jun 2025 19:22:45 -0400	[thread overview]
Message-ID: <20250601232435.3507697-3-sashal@kernel.org> (raw)
In-Reply-To: <20250601232435.3507697-1-sashal@kernel.org>

From: Alex Deucher <alexander.deucher@amd.com>

[ Upstream commit 8307ebc15c1ea98a8a0b7837af1faa6c01514577 ]

We shouldn't return after the last section.
We need to update the rest of the CSIB.

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

Now let me understand what the bug is. Looking at the original code:
```c for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
for (ext = sect->section; ext->extent != NULL; ++ext) { if (sect->id ==
SECT_CONTEXT) { // process SECT_CONTEXT sections } else { return; //
BUG: This returns early, skipping remaining code } } } // Important code
that should always run: buffer[count++] =
cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); buffer[count++] =
cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); //
... more important buffer initialization ``` The fix removes the early
return so that all sections are processed and the important buffer
initialization at the end always runs. **YES** This commit should be
backported to stable kernel trees for the following reasons: 1. **Clear
Bug Fix**: The commit fixes a clear logic error where an early return
statement prevents critical buffer initialization code from executing.
The original code would return immediately when encountering a non-
SECT_CONTEXT section, skipping the important packet commands that should
always be written to the buffer (PACKET3_SET_CONTEXT_REG,
PACKET3_PREAMBLE_END_CLEAR_STATE, PACKET3_CLEAR_STATE). 2. **Functional
Impact**: This bug affects the Clear State Indirect Buffer (CSIB)
handling in AMD GPU driver for GFX6 hardware. The incomplete buffer
initialization could lead to: - Incorrect GPU state during graphics
operations - Potential rendering issues or GPU hangs - Inconsistent
hardware behavior 3. **Small and Contained Fix**: The fix is minimal -
it simply removes two lines (the else block with return statement). This
is a low-risk change that doesn't introduce new functionality or alter
the architecture. 4. **Hardware-Specific Bug**: This affects real users
with GFX6 AMD GPUs. The bug prevents proper initialization of the GPU's
clear state buffer, which is essential for correct GPU operation. 5.
**Similar to Historical Backports**: Looking at commit 4 in the similar
commits (marked as YES for backporting), which also fixed preamble
handling issues in the AMD GPU driver, this follows a similar pattern of
fixing command buffer handling bugs. The commit message clearly
indicates this is a bug fix ("We shouldn't return after the last
section. We need to update the rest of the CSIB"), and the code change
confirms that critical buffer initialization was being skipped due to
the premature return.

 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 13fbee46417af..cee2cf47112c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2874,8 +2874,6 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
 				buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
 				for (i = 0; i < ext->reg_count; i++)
 					buffer[count++] = cpu_to_le32(ext->extent[i]);
-			} else {
-				return;
 			}
 		}
 	}
-- 
2.39.5


  reply	other threads:[~2025-06-01 23:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-01 23:22 [PATCH AUTOSEL 6.15 001/110] drm/amd/display: disable DPP RCG before DPP CLK enable Sasha Levin
2025-06-01 23:22 ` Sasha Levin [this message]
2025-06-01 23:22 ` [PATCH AUTOSEL 6.15 008/110] drm/amdgpu: Fix API status offset for MES queue reset Sasha Levin
2025-06-01 23:22 ` [PATCH AUTOSEL 6.15 009/110] drm/amd/display: DCN32 null data check Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 020/110] drm/amdkfd: Drop workaround for GC v9.4.3 revID 0 Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 021/110] drm/amdgpu/gfx11: fix CSIB handling Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 025/110] drm/amd/display: Avoid divide by zero by initializing dummy pitch to 1 Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 029/110] drm/amd/display: Add NULL pointer checks in dm_force_atomic_commit() Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 031/110] drm/amd/display: Skip to enable dsc if it has been off Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 032/110] drm/amdgpu: Add basic validation for RAS header Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 035/110] drm/amd/display: Do Not Consider DSC if Valid Config Not Found Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 037/110] drm/amdgpu/gfx10: fix CSIB handling Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 041/110] drm/amd/display: fix zero value for APU watermark_c Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 043/110] drm/amdgpu/gfx7: fix CSIB handling Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 049/110] drm/amd/display: Update IPS sequential_ono requirement checks Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 050/110] drm/amd/display: Correct SSC enable detection for DCN351 Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 051/110] drm/amd/display: Fix Vertical Interrupt definitions for dcn32, dcn401 Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 055/110] drm/amdgpu: fix MES GFX mask Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 056/110] drm/amdgpu: Disallow partition query during reset Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 059/110] drm/amdgpu/gfx8: fix CSIB handling Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 060/110] drm/amd/display: disable EASF narrow filter sharpening Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 061/110] drm/amdgpu/gfx9: fix CSIB handling Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 062/110] drm/amd/display: Fix VUpdate offset calculations for dcn401 Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 064/110] drm/amd/pm: Reset SMU v13.0.x custom settings Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 065/110] drm/amd/display: Correct prefetch calculation Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 066/110] drm/amd/display: Restructure DMI quirks Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 069/110] drm/amdkfd: Set SDMA_RLCx_IB_CNTL/SWITCH_INSIDE_IB Sasha Levin
2025-06-01 23:23 ` [PATCH AUTOSEL 6.15 076/110] drm/amdgpu: Add indirect L1_TLB_CNTL reg programming for VFs Sasha Levin

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