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From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org, amd-gfx@lists.freedesktop.org
Cc: harry.wentland@amd.com, jani.nikula@linux.intel.com,
	louis.chauvet@bootlin.com, mwen@igalia.com, contact@emersion.fr,
	alex.hung@amd.com, daniels@collabora.com, uma.shankar@intel.com,
	suraj.kandpal@intel.com, nfraprado@collabora.com,
	ville.syrjala@linux.intel.com, matthew.d.roper@intel.com
Subject: [PATCH 13/13] drm/i915/color: Add failure handling in plane color pipeline init
Date: Fri, 19 Dec 2025 12:26:14 +0530	[thread overview]
Message-ID: <20251219065614.190834-14-chaitanya.kumar.borah@intel.com> (raw)
In-Reply-To: <20251219065614.190834-1-chaitanya.kumar.borah@intel.com>

The plane color pipeline initialization built up multiple colorop blocks
inline, but did not reliably clean up partially constructed pipelines
when an intermediate step failed. This could lead to leaked colorop
objects and fragile error handling as the pipeline grows.

Refactor the pipeline construction to use a common helper for adding
colorop blocks. This centralizes allocation, initialization, and
teardown logic, allowing the caller to reliably unwind all previously
created colorops on failure.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 .../drm/i915/display/intel_color_pipeline.c   | 142 ++++++++++++------
 1 file changed, 100 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
index 8fecc53540ba..035ec3f022cd 100644
--- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
+++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
@@ -2,6 +2,8 @@
 /*
  * Copyright © 2025 Intel Corporation
  */
+#include <drm/drm_print.h>
+
 #include "intel_color.h"
 #include "intel_colorop.h"
 #include "intel_color_pipeline.h"
@@ -10,6 +12,7 @@
 #include "skl_universal_plane.h"
 
 #define MAX_COLOR_PIPELINES 1
+#define MAX_COLOROP 4
 #define PLANE_DEGAMMA_SIZE 128
 #define PLANE_GAMMA_SIZE 32
 
@@ -18,69 +21,124 @@ static const struct drm_colorop_funcs intel_colorop_funcs = {
 };
 
 static
-int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list,
-				     enum pipe pipe)
+struct intel_colorop *intel_color_pipeline_plane_add_colorop(struct drm_plane *plane,
+							     struct intel_colorop *prev,
+							     enum intel_color_block id)
 {
 	struct drm_device *dev = plane->dev;
-	struct intel_display *display = to_intel_display(dev);
-	struct drm_colorop *prev_op;
 	struct intel_colorop *colorop;
 	int ret;
 
-	colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
-
-	ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane, &intel_colorop_funcs,
-						  PLANE_DEGAMMA_SIZE,
-						  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
-						  DRM_COLOROP_FLAG_ALLOW_BYPASS);
+	colorop = intel_colorop_create(id);
+
+	if (IS_ERR(colorop))
+		return colorop;
+
+	switch (id) {
+	case INTEL_PLANE_CB_PRE_CSC_LUT:
+		ret = drm_plane_colorop_curve_1d_lut_init(dev,
+							  &colorop->base, plane,
+							  &intel_colorop_funcs,
+							  PLANE_DEGAMMA_SIZE,
+							  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+							  DRM_COLOROP_FLAG_ALLOW_BYPASS);
+		break;
+	case INTEL_PLANE_CB_CSC:
+		ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
+						     &intel_colorop_funcs,
+						     DRM_COLOROP_FLAG_ALLOW_BYPASS);
+		break;
+	case INTEL_PLANE_CB_3DLUT:
+		ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane,
+						   &intel_colorop_funcs, 17,
+						   DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
+						   true);
+		break;
+	case INTEL_PLANE_CB_POST_CSC_LUT:
+		ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
+							  &intel_colorop_funcs,
+							  PLANE_GAMMA_SIZE,
+							  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+							  DRM_COLOROP_FLAG_ALLOW_BYPASS);
+		break;
+	default:
+		drm_err(plane->dev, "Invalid colorop id [%d]", id);
+		ret = -EINVAL;
+	}
 
 	if (ret)
-		return ret;
+		goto cleanup;
 
-	list->type = colorop->base.base.id;
+	if (prev)
+		drm_colorop_set_next_property(&prev->base, &colorop->base);
 
-	/* TODO: handle failures and clean up */
-	prev_op = &colorop->base;
+	return colorop;
 
-	colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
-	ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane, &intel_colorop_funcs,
-					     DRM_COLOROP_FLAG_ALLOW_BYPASS);
-	if (ret)
-		return ret;
+cleanup:
+	intel_colorop_destroy(&colorop->base);
+	return ERR_PTR(ret);
+}
 
-	drm_colorop_set_next_property(prev_op, &colorop->base);
-	prev_op = &colorop->base;
+static
+int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list,
+				     enum pipe pipe)
+{
+	struct drm_device *dev = plane->dev;
+	struct intel_display *display = to_intel_display(dev);
+	struct intel_colorop *colorop[MAX_COLOROP];
+	int ret = 0;
+	int i = 0;
 
-	if (DISPLAY_VER(display) >= 35 &&
-	    intel_color_crtc_has_3dlut(display, pipe) &&
-	    plane->type == DRM_PLANE_TYPE_PRIMARY) {
-		colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
+	colorop[i] = intel_color_pipeline_plane_add_colorop(plane, NULL,
+							    INTEL_PLANE_CB_PRE_CSC_LUT);
+
+	if (IS_ERR(colorop[i])) {
+		ret = PTR_ERR(colorop[i]);
+		goto cleanup;
+	}
+	i++;
 
-		ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane,
-						   &intel_colorop_funcs, 17,
-						   DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
-						   true);
-		if (ret)
-			return ret;
 
-		drm_colorop_set_next_property(prev_op, &colorop->base);
+	colorop[i] = intel_color_pipeline_plane_add_colorop(plane, colorop[i - 1],
+							    INTEL_PLANE_CB_CSC);
 
-		prev_op = &colorop->base;
+	if (IS_ERR(colorop[i])) {
+		ret = PTR_ERR(colorop[i]);
+		goto cleanup;
 	}
 
-	colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
-	ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane, &intel_colorop_funcs,
-						  PLANE_GAMMA_SIZE,
-						  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
-						  DRM_COLOROP_FLAG_ALLOW_BYPASS);
-	if (ret)
-		return ret;
+	i++;
 
-	drm_colorop_set_next_property(prev_op, &colorop->base);
+	if (DISPLAY_VER(display) >= 35 &&
+	    intel_color_crtc_has_3dlut(display, pipe) &&
+	    plane->type == DRM_PLANE_TYPE_PRIMARY) {
+		colorop[i] = intel_color_pipeline_plane_add_colorop(plane, colorop[i - 1],
+								    INTEL_PLANE_CB_3DLUT);
+
+		if (IS_ERR(colorop[i])) {
+			ret = PTR_ERR(colorop[i]);
+			goto cleanup;
+		}
+		i++;
+	}
 
-	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", list->type);
+	colorop[i] = intel_color_pipeline_plane_add_colorop(plane, colorop[i - 1],
+							    INTEL_PLANE_CB_POST_CSC_LUT);
+	if (IS_ERR(colorop[i])) {
+		ret = PTR_ERR(colorop[i]);
+		goto cleanup;
+	}
+	i++;
+
+	list->type = colorop[0]->base.base.id;
+	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", colorop[0]->base.base.id);
 
 	return 0;
+
+cleanup:
+	while (--i >= 0)
+		intel_colorop_destroy(&colorop[i]->base);
+	return ret;
 }
 
 int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
-- 
2.25.1


  parent reply	other threads:[~2025-12-19  7:13 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-19  6:56 [PATCH 00/13] drm: Color pipeline teardown and follow-up fixes/improvements Chaitanya Kumar Borah
2025-12-19  6:56 ` [PATCH 01/13] drm/i915/color: Place 3D LUT after CSC in plane color pipeline Chaitanya Kumar Borah
2026-01-05  8:33   ` Kandpal, Suraj
2026-01-06  9:48   ` Shankar, Uma
2025-12-19  6:56 ` [PATCH 02/13] drm/amd/display: Fix color pipeline enum name leak Chaitanya Kumar Borah
2026-01-06 10:55   ` Shankar, Uma
2026-01-06 23:50   ` Alex Hung
2025-12-19  6:56 ` [PATCH 03/13] drm/vkms: " Chaitanya Kumar Borah
2026-01-06 10:57   ` Shankar, Uma
2026-01-06 23:50   ` Alex Hung
2025-12-19  6:56 ` [PATCH 04/13] drm/i915/display: " Chaitanya Kumar Borah
2026-01-05  9:04   ` Kandpal, Suraj
2026-01-06 10:59   ` Shankar, Uma
2025-12-19  6:56 ` [PATCH 05/13] drm: Allow driver-managed destruction of colorop objects Chaitanya Kumar Borah
2026-01-05  9:14   ` Kandpal, Suraj
2026-01-06 11:05   ` Shankar, Uma
2026-01-07  0:02   ` Alex Hung
2026-01-08 14:11     ` Borah, Chaitanya Kumar
2026-01-08 17:15       ` Alex Hung
2025-12-19  6:56 ` [PATCH 06/13] drm/colorop: Add destroy helper for " Chaitanya Kumar Borah
2026-01-05  9:16   ` Kandpal, Suraj
2026-01-06 11:07   ` Shankar, Uma
2026-01-07  0:02   ` Alex Hung
2025-12-19  6:56 ` [PATCH 07/13] drm/amd/display: Hook up colorop destroy helper for plane pipelines Chaitanya Kumar Borah
2026-01-06 11:10   ` Shankar, Uma
2026-01-07  0:03   ` Alex Hung
2025-12-19  6:56 ` [PATCH 08/13] drm/vkms: " Chaitanya Kumar Borah
2026-01-06 11:11   ` Shankar, Uma
2026-01-07  0:04   ` Alex Hung
2025-12-19  6:56 ` [PATCH 09/13] drm/i915/display: Hook up intel_colorop_destroy Chaitanya Kumar Borah
2026-01-05  9:18   ` Kandpal, Suraj
2026-01-06 11:16   ` Shankar, Uma
2025-12-19  6:56 ` [PATCH 10/13] drm: Clean up colorop objects during mode_config cleanup Chaitanya Kumar Borah
2026-01-05  9:20   ` Kandpal, Suraj
2026-01-06 11:20   ` Shankar, Uma
2026-01-07  0:04   ` Alex Hung
2025-12-19  6:56 ` [PATCH 11/13] drm/vkms: Remove drm_colorop_pipeline_destroy() from vkms_destroy() Chaitanya Kumar Borah
2026-01-06 11:21   ` Shankar, Uma
2025-12-19  6:56 ` [PATCH 12/13] drm/colorop: Use destroy callback for color pipeline teardown Chaitanya Kumar Borah
2026-01-05  9:27   ` Kandpal, Suraj
2026-01-06 11:23   ` Shankar, Uma
2026-01-07  0:05   ` Alex Hung
2025-12-19  6:56 ` Chaitanya Kumar Borah [this message]
2026-01-06  3:55   ` [PATCH 13/13] drm/i915/color: Add failure handling in plane color pipeline init Kandpal, Suraj
2026-01-06 11:57     ` Shankar, Uma
2026-01-09  8:49     ` Borah, Chaitanya Kumar

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