* [PATCH v1 0/3] Move gfx9.4.3 and gfx 9.5.0 MQD to HBM
@ 2026-01-07 19:23 Philip Yang
2026-01-07 19:23 ` [PATCH v1 1/3] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Philip Yang @ 2026-01-07 19:23 UTC (permalink / raw)
To: amd-gfx
Cc: Felix.Kuehling, christian.koenig, david.yatsin, kent.russell,
jay.cornwall, Philip Yang
To reduce multiple queues switch latency, move user queues MQD to HBM,
and map on GART with mtype RW.
v1:
- patch 2 add HDP flush after MQD updated
Start new patch series v1 because two patches in previous patch series
merged in already for general fix and helper function.
624bf8ab05ff drm/amdgpu: Add helper to alloc GART entries
d33a6691b65b drm/amdgpu: Fix gfx9 update PTE mtype flag
Philip Yang (3):
drm/amdkfd: Add domain parameter to alloc kernel BO
drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM
drm/amdkfd: Map VRAM MQD on GART
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 13 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 6 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 74 +++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 +-
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 3 +-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 ++--
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 7 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 16 ++--
.../drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 4 +-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 42 ++++++++++-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +-
.../amd/amdkfd/kfd_process_queue_manager.c | 12 +--
14 files changed, 161 insertions(+), 42 deletions(-)
--
2.50.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 1/3] drm/amdkfd: Add domain parameter to alloc kernel BO
2026-01-07 19:23 [PATCH v1 0/3] Move gfx9.4.3 and gfx 9.5.0 MQD to HBM Philip Yang
@ 2026-01-07 19:23 ` Philip Yang
2026-01-07 19:23 ` [PATCH v1 2/3] drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM Philip Yang
2026-01-07 19:23 ` [PATCH v1 3/3] drm/amdkfd: Map VRAM MQD on GART Philip Yang
2 siblings, 0 replies; 6+ messages in thread
From: Philip Yang @ 2026-01-07 19:23 UTC (permalink / raw)
To: amd-gfx
Cc: Felix.Kuehling, christian.koenig, david.yatsin, kent.russell,
jay.cornwall, Philip Yang
To allocate kernel BO from VRAM domain for MQD in the following patch.
No functional change because kernel BO allocate all from GTT domain.
Rename amdgpu_amdkfd_alloc_gtt_mem to amdgpu_amdkfd_alloc_kernel_mem
Rename amdgpu_amdkfd_free_gtt_mem to amdgpu_amdkfd_free_kernel_mem
Rename mem_kfd_mem_obj gtt_mem to mem
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 +++++++------
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 7 ++++---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 14 +++++++-------
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 9 +++++----
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +-
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 12 +++++++-----
12 files changed, 45 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 67a01c4f3885..39c0b5a385c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -316,8 +316,8 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
&adev->kfd.reset_work);
}
-int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
- void **mem_obj, uint64_t *gpu_addr,
+int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size,
+ u32 domain, void **mem_obj, uint64_t *gpu_addr,
void **cpu_ptr, bool cp_mqd_gfx9)
{
struct amdgpu_bo *bo = NULL;
@@ -328,7 +328,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
memset(&bp, 0, sizeof(bp));
bp.size = size;
bp.byte_align = PAGE_SIZE;
- bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+ bp.domain = domain;
bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
@@ -351,7 +351,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
goto allocate_mem_reserve_bo_failed;
}
- r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
+ r = amdgpu_bo_pin(bo, domain);
if (r) {
dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
goto allocate_mem_pin_bo_failed;
@@ -388,7 +388,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
return r;
}
-void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj)
+void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj)
{
struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index da4575676335..274a99eb6d44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -240,10 +240,10 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
}
#endif
/* Shared API */
-int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
- void **mem_obj, uint64_t *gpu_addr,
+int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size,
+ u32 domain, void **mem_obj, uint64_t *gpu_addr,
void **cpu_ptr, bool mqd_gfx9);
-void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj);
+void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj);
int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
void **mem_obj);
void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 88fc430b9425..768998c82b43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2215,7 +2215,7 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
* @bo_gart: Return bo reference
*
* Before return, bo reference count is incremented. To release the reference and unpin/
- * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
+ * unmap the BO, call amdgpu_amdkfd_free_kernel_mem.
*/
int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart)
{
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index cd5a0b58c7d1..27176b2dc714 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -357,8 +357,9 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
return 0;
if (!pdd->proc_ctx_cpu_ptr) {
- r = amdgpu_amdkfd_alloc_gtt_mem(adev,
+ r = amdgpu_amdkfd_alloc_kernel_mem(adev,
AMDGPU_MES_PROC_CTX_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
&pdd->proc_ctx_bo,
&pdd->proc_ctx_gpu_addr,
&pdd->proc_ctx_cpu_ptr,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index db37c2949d19..6814316ef220 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -820,12 +820,13 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
/* add another 512KB for all other allocations on gart (HPD, fences) */
size += 512 * 1024;
- if (amdgpu_amdkfd_alloc_gtt_mem(
- kfd->adev, size, &kfd->gtt_mem,
+ if (amdgpu_amdkfd_alloc_kernel_mem(
+ kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT,
+ &kfd->gtt_mem,
&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
false)) {
dev_err(kfd_device, "Could not allocate %d bytes\n", size);
- goto alloc_gtt_mem_failure;
+ goto alloc_kernel_mem_failure;
}
dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
@@ -951,8 +952,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
kfd_doorbell_error:
kfd_gtt_sa_fini(kfd);
kfd_gtt_sa_init_error:
- amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
-alloc_gtt_mem_failure:
+ amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem);
+alloc_kernel_mem_failure:
dev_err(kfd_device,
"device %x:%x NOT added due to errors\n",
kfd->adev->pdev->vendor, kfd->adev->pdev->device);
@@ -969,7 +970,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)
kfd_doorbell_fini(kfd);
ida_destroy(&kfd->doorbell_ida);
kfd_gtt_sa_fini(kfd);
- amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
+ amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem);
}
kfree(kfd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 9bc80f8ba7dc..23889f84086c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2909,8 +2909,9 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
(dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
NUM_XCC(dqm->dev->xcc_mask));
- retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
- &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
+ retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, size,
+ AMDGPU_GEM_DOMAIN_GTT,
+ &(mem_obj->mem), &(mem_obj->gpu_addr),
(void *)&(mem_obj->cpu_ptr), false);
return retval;
@@ -3051,7 +3052,7 @@ static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,
{
WARN(!mqd, "No hiq sdma mqd trunk to free");
- amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem);
+ amdgpu_amdkfd_free_kernel_mem(dev->adev, &mqd->mem);
}
void device_queue_manager_uninit(struct device_queue_manager *dqm)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index d9ae854b6908..f78b249e1a41 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -54,7 +54,7 @@ struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properti
if (!mqd_mem_obj)
return NULL;
- mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem;
+ mqd_mem_obj->mem = dev->dqm->hiq_sdma_mqd.mem;
mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr;
@@ -79,7 +79,7 @@ struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev,
offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
NUM_XCC(dev->xcc_mask);
- mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem
+ mqd_mem_obj->mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.mem
+ offset);
mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t)
@@ -91,7 +91,7 @@ struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev,
void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
struct kfd_mem_obj *mqd_mem_obj)
{
- WARN_ON(!mqd_mem_obj->gtt_mem);
+ WARN_ON(!mqd_mem_obj->mem);
kfree(mqd_mem_obj);
}
@@ -224,8 +224,8 @@ int kfd_destroy_mqd_cp(struct mqd_manager *mm, void *mqd,
void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd,
struct kfd_mem_obj *mqd_mem_obj)
{
- if (mqd_mem_obj->gtt_mem) {
- amdgpu_amdkfd_free_gtt_mem(mm->dev->adev, &mqd_mem_obj->gtt_mem);
+ if (mqd_mem_obj->mem) {
+ amdgpu_amdkfd_free_kernel_mem(mm->dev->adev, &mqd_mem_obj->mem);
kfree(mqd_mem_obj);
} else {
kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
@@ -280,8 +280,8 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj,
offset = kfd_hiq_mqd_stride(dev) * virtual_xcc_id;
- mqd_mem_obj->gtt_mem = (virtual_xcc_id == 0) ?
- dev->dqm->hiq_sdma_mqd.gtt_mem : NULL;
+ mqd_mem_obj->mem = (virtual_xcc_id == 0) ?
+ dev->dqm->hiq_sdma_mqd.mem : NULL;
mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)
dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
index a06b4e89af8a..558216395a4d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
@@ -454,8 +454,8 @@ static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj,
struct kfd_mem_obj *xcc_mqd_mem_obj,
uint64_t offset)
{
- xcc_mqd_mem_obj->gtt_mem = (offset == 0) ?
- mqd_mem_obj->gtt_mem : NULL;
+ xcc_mqd_mem_obj->mem = (offset == 0) ?
+ mqd_mem_obj->mem : NULL;
xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset;
xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr
+ offset);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 2e9b6bcf2704..d234db138182 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -135,11 +135,12 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
if (!mqd_mem_obj)
return NULL;
- retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev,
+ retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev,
(ALIGN(q->ctl_stack_size, PAGE_SIZE) +
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
NUM_XCC(node->xcc_mask),
- &(mqd_mem_obj->gtt_mem),
+ AMDGPU_GEM_DOMAIN_GTT,
+ &(mqd_mem_obj->mem),
&(mqd_mem_obj->gpu_addr),
(void *)&(mqd_mem_obj->cpu_ptr), true);
@@ -665,8 +666,8 @@ static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj,
struct kfd_mem_obj *xcc_mqd_mem_obj,
uint64_t offset)
{
- xcc_mqd_mem_obj->gtt_mem = (offset == 0) ?
- mqd_mem_obj->gtt_mem : NULL;
+ xcc_mqd_mem_obj->mem = (offset == 0) ?
+ mqd_mem_obj->mem : NULL;
xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset;
xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr
+ offset);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index d798baa7e52e..042b8e747b5b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -252,7 +252,7 @@ struct kfd_mem_obj {
uint32_t range_end;
uint64_t gpu_addr;
uint32_t *cpu_ptr;
- void *gtt_mem;
+ void *mem;
};
struct kfd_vmid_info {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 82109f939c13..33153760d48e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1131,7 +1131,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
if (pdd->dev->kfd->shared_resources.enable_mes &&
pdd->proc_ctx_cpu_ptr)
- amdgpu_amdkfd_free_gtt_mem(pdd->dev->adev,
+ amdgpu_amdkfd_free_kernel_mem(pdd->dev->adev,
&pdd->proc_ctx_bo);
/*
* before destroying pdd, make sure to report availability
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index a399770aa411..449be58e884c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -210,8 +210,8 @@ static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
}
if (dev->kfd->shared_resources.enable_mes) {
- amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo);
- amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart);
+ amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo);
+ amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart);
}
}
@@ -265,8 +265,9 @@ static int init_user_queue(struct process_queue_manager *pqm,
(*q)->process = pqm->process;
if (dev->kfd->shared_resources.enable_mes) {
- retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
+ retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev,
AMDGPU_MES_GANG_CTX_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
&(*q)->gang_ctx_bo,
&(*q)->gang_ctx_gpu_addr,
&(*q)->gang_ctx_cpu_ptr,
@@ -298,7 +299,7 @@ static int init_user_queue(struct process_queue_manager *pqm,
return 0;
free_gang_ctx_bo:
- amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo);
+ amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo);
cleanup:
uninit_queue(*q);
*q = NULL;
@@ -368,8 +369,9 @@ int pqm_create_queue(struct process_queue_manager *pqm,
/* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */
if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) {
- retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
+ retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev,
AMDGPU_MES_PROC_CTX_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
&pdd->proc_ctx_bo,
&pdd->proc_ctx_gpu_addr,
&pdd->proc_ctx_cpu_ptr,
--
2.50.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 2/3] drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM
2026-01-07 19:23 [PATCH v1 0/3] Move gfx9.4.3 and gfx 9.5.0 MQD to HBM Philip Yang
2026-01-07 19:23 ` [PATCH v1 1/3] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
@ 2026-01-07 19:23 ` Philip Yang
2026-01-09 23:19 ` Kuehling, Felix
2026-01-07 19:23 ` [PATCH v1 3/3] drm/amdkfd: Map VRAM MQD on GART Philip Yang
2 siblings, 1 reply; 6+ messages in thread
From: Philip Yang @ 2026-01-07 19:23 UTC (permalink / raw)
To: amd-gfx
Cc: Felix.Kuehling, christian.koenig, david.yatsin, kent.russell,
jay.cornwall, Philip Yang
To reduce queue switch latency further, move MQD to VRAM domain, CP
access MQD and control stack via FB aperture, this requires contiguous
pages.
After MQD is initialized, updated or restored, flush HDP to guarantee
the data is written to HBM and GPU cache is invalidated, then CP will
read the new MQD.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 23 ++++++++++++++++++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 39c0b5a385c9..c1ffae9e96d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size,
bp.size = size;
bp.byte_align = PAGE_SIZE;
bp.domain = domain;
- bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index d234db138182..d867dccae675 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -109,6 +109,17 @@ static void set_priority(struct v9_mqd *m, struct queue_properties *q)
m->cp_hqd_queue_priority = q->priority;
}
+static bool mqd_on_vram(struct amdgpu_device *adev)
+{
+ switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+ case IP_VERSION(9, 4, 3):
+ case IP_VERSION(9, 5, 0):
+ return true;
+ default:
+ return false;
+ }
+}
+
static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
struct queue_properties *q)
{
@@ -139,7 +150,8 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
(ALIGN(q->ctl_stack_size, PAGE_SIZE) +
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
NUM_XCC(node->xcc_mask),
- AMDGPU_GEM_DOMAIN_GTT,
+ mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM :
+ AMDGPU_GEM_DOMAIN_GTT,
&(mqd_mem_obj->mem),
&(mqd_mem_obj->gpu_addr),
(void *)&(mqd_mem_obj->cpu_ptr), true);
@@ -739,6 +751,9 @@ static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
*gart_addr = xcc_gart_addr;
}
}
+
+ if (mqd_on_vram(mm->dev->adev))
+ amdgpu_device_flush_hdp(mm->dev->adev, NULL);
}
static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
@@ -775,6 +790,9 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
m->pm4_target_xcc_in_xcp = q->pm4_target_xcc;
}
}
+
+ if (mqd_on_vram(mm->dev->adev))
+ amdgpu_device_flush_hdp(mm->dev->adev, NULL);
}
static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
@@ -813,6 +831,9 @@ static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
(uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size,
mqd_ctl_stack_size);
}
+
+ if (mqd_on_vram(mm->dev->adev))
+ amdgpu_device_flush_hdp(mm->dev->adev, NULL);
}
static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
enum kfd_preempt_type type, unsigned int timeout,
--
2.50.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 3/3] drm/amdkfd: Map VRAM MQD on GART
2026-01-07 19:23 [PATCH v1 0/3] Move gfx9.4.3 and gfx 9.5.0 MQD to HBM Philip Yang
2026-01-07 19:23 ` [PATCH v1 1/3] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
2026-01-07 19:23 ` [PATCH v1 2/3] drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM Philip Yang
@ 2026-01-07 19:23 ` Philip Yang
2026-01-08 13:24 ` Christian König
2 siblings, 1 reply; 6+ messages in thread
From: Philip Yang @ 2026-01-07 19:23 UTC (permalink / raw)
To: amd-gfx
Cc: Felix.Kuehling, christian.koenig, david.yatsin, kent.russell,
jay.cornwall, Philip Yang
To reduce queue switch latency, alloc GART entries and map MQD with
MTYPE_RW and control stack with MTYPE_NC on GART. Before invoking
get_wave_state, debugger unmaps the runlist and at that time CP writes
back TC, so debugger will read the updated state.
Add GART mm_node to kfd mem obj to free the GART entries after MQD mem
obj is freed.
Use resource cursor to handle VRAM resource which maybe on multiple
blocks and use cursor_gart to handle GART entries.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 74 +++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 2 +
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 12 +++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 +
5 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f27ffe64aafa..92a21af789ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -875,6 +875,80 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
}
}
+/*
+ * Same function and MQD description from amdgpu_ttm_gart_bind_gfx9_mqd,
+ * except this is for MQD on VRAM BO and use dynamic alloc GART entries.
+ */
+int amdgpu_ttm_gart_bind_gfx9_mqd_vram(struct amdgpu_device *adev,
+ struct amdgpu_bo *abo,
+ struct drm_mm_node *mm_node,
+ u64 *gpu_addr)
+{
+ struct ttm_buffer_object *bo = &abo->tbo;
+ int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
+ u64 page_idx, pages_per_xcc;
+ struct amdgpu_res_cursor cursor_gart;
+ struct amdgpu_res_cursor cursor;
+ u64 ctrl_flags;
+ u64 total_pages;
+ u64 flags;
+ int i, r;
+
+ r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, mm_node,
+ amdgpu_bo_ngpu_pages(abo), 0);
+ if (r)
+ return r;
+
+ /* compute PTE flags for this buffer object */
+ flags = amdgpu_ttm_tt_pte_flags(adev, NULL, bo->resource);
+ ctrl_flags = flags;
+ amdgpu_gmc_get_vm_pte(adev, NULL, NULL, AMDGPU_VM_MTYPE_RW, &flags);
+ amdgpu_gmc_get_vm_pte(adev, NULL, NULL, AMDGPU_VM_MTYPE_NC, &ctrl_flags);
+
+ total_pages = bo->base.size >> PAGE_SHIFT;
+ pages_per_xcc = total_pages;
+ do_div(pages_per_xcc, num_xcc);
+
+ amdgpu_res_first(NULL, mm_node->start, total_pages, &cursor_gart);
+ amdgpu_res_first(bo->resource, 0, bo->resource->size, &cursor);
+
+ for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
+ u64 start_page;
+ u64 npages, n;
+ u64 pa;
+
+ /* MQD page: use flags MTYPE_RW */
+ start_page = cursor_gart.start;
+ pa = cursor.start + adev->vm_manager.vram_base_offset;
+ n = 1;
+ amdgpu_gart_map_vram_range(adev, pa, start_page, n,
+ flags, NULL);
+
+ /* Ctrl stack pages: modify the memory type to NC */
+ npages = pages_per_xcc - 1;
+ while (npages) {
+ amdgpu_res_next(&cursor_gart, n);
+ amdgpu_res_next(&cursor, n * PAGE_SIZE);
+
+ start_page = cursor_gart.start;
+ pa = cursor.start + adev->vm_manager.vram_base_offset;
+ n = min3(cursor.size / PAGE_SIZE, cursor_gart.size, npages);
+
+ amdgpu_gart_map_vram_range(adev, pa, start_page, n,
+ ctrl_flags, NULL);
+
+ npages -= n;
+ }
+
+ amdgpu_res_next(&cursor_gart, n);
+ amdgpu_res_next(&cursor, n * PAGE_SIZE);
+ }
+
+ amdgpu_gart_invalidate_tlb(adev);
+ *gpu_addr = mm_node->start << PAGE_SHIFT;
+ return 0;
+}
+
static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
struct ttm_buffer_object *tbo,
uint64_t flags)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 143201ecea3f..3751f010f14a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -140,7 +140,6 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
-
int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr,
struct drm_mm_node *mm_node,
u64 num_pages,
@@ -189,8 +188,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
struct dma_resv *resv,
struct dma_fence **f,
u64 k_job_id);
-
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
+int amdgpu_ttm_gart_bind_gfx9_mqd_vram(struct amdgpu_device *adev,
+ struct amdgpu_bo *abo,
+ struct drm_mm_node *mm_node,
+ u64 *gpu_addr);
void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index f78b249e1a41..edb72f4ef82d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -225,6 +225,8 @@ void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd,
struct kfd_mem_obj *mqd_mem_obj)
{
if (mqd_mem_obj->mem) {
+ amdgpu_gtt_mgr_free_entries(&mm->dev->adev->mman.gtt_mgr,
+ &mqd_mem_obj->mm_node);
amdgpu_amdkfd_free_kernel_mem(mm->dev->adev, &mqd_mem_obj->mem);
kfree(mqd_mem_obj);
} else {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index d867dccae675..1893dabb823a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -160,6 +160,18 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
kfree(mqd_mem_obj);
return NULL;
}
+
+ if (mqd_on_vram(node->adev)) {
+ retval = amdgpu_ttm_gart_bind_gfx9_mqd_vram(node->adev,
+ mqd_mem_obj->mem,
+ &(mqd_mem_obj->mm_node),
+ &(mqd_mem_obj->gpu_addr));
+ if (retval) {
+ amdgpu_amdkfd_free_kernel_mem(node->adev, &(mqd_mem_obj->mem));
+ kfree(mqd_mem_obj);
+ return NULL;
+ }
+ }
} else {
retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
&mqd_mem_obj);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 042b8e747b5b..7c95cc9e2f0d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -253,6 +253,7 @@ struct kfd_mem_obj {
uint64_t gpu_addr;
uint32_t *cpu_ptr;
void *mem;
+ struct drm_mm_node mm_node;
};
struct kfd_vmid_info {
--
2.50.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 3/3] drm/amdkfd: Map VRAM MQD on GART
2026-01-07 19:23 ` [PATCH v1 3/3] drm/amdkfd: Map VRAM MQD on GART Philip Yang
@ 2026-01-08 13:24 ` Christian König
0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2026-01-08 13:24 UTC (permalink / raw)
To: Philip Yang, amd-gfx
Cc: Felix.Kuehling, david.yatsin, kent.russell, jay.cornwall
On 1/7/26 20:23, Philip Yang wrote:
> To reduce queue switch latency, alloc GART entries and map MQD with
> MTYPE_RW and control stack with MTYPE_NC on GART. Before invoking
> get_wave_state, debugger unmaps the runlist and at that time CP writes
> back TC, so debugger will read the updated state.
>
> Add GART mm_node to kfd mem obj to free the GART entries after MQD mem
> obj is freed.
>
> Use resource cursor to handle VRAM resource which maybe on multiple
> blocks and use cursor_gart to handle GART entries.
After the discussion I don't think mapping the MQD to GART is necessary any more.
The default NC caching should be sufficient for both parts on modern HW. If it isn't then we should not move the MQD to VRAM in the first place.
Regards,
Christian.
>
> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 74 +++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 +-
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 2 +
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 12 +++
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 +
> 5 files changed, 93 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index f27ffe64aafa..92a21af789ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -875,6 +875,80 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
> }
> }
>
> +/*
> + * Same function and MQD description from amdgpu_ttm_gart_bind_gfx9_mqd,
> + * except this is for MQD on VRAM BO and use dynamic alloc GART entries.
> + */
> +int amdgpu_ttm_gart_bind_gfx9_mqd_vram(struct amdgpu_device *adev,
> + struct amdgpu_bo *abo,
> + struct drm_mm_node *mm_node,
> + u64 *gpu_addr)
> +{
> + struct ttm_buffer_object *bo = &abo->tbo;
> + int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
> + u64 page_idx, pages_per_xcc;
> + struct amdgpu_res_cursor cursor_gart;
> + struct amdgpu_res_cursor cursor;
> + u64 ctrl_flags;
> + u64 total_pages;
> + u64 flags;
> + int i, r;
> +
> + r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, mm_node,
> + amdgpu_bo_ngpu_pages(abo), 0);
> + if (r)
> + return r;
> +
> + /* compute PTE flags for this buffer object */
> + flags = amdgpu_ttm_tt_pte_flags(adev, NULL, bo->resource);
> + ctrl_flags = flags;
> + amdgpu_gmc_get_vm_pte(adev, NULL, NULL, AMDGPU_VM_MTYPE_RW, &flags);
> + amdgpu_gmc_get_vm_pte(adev, NULL, NULL, AMDGPU_VM_MTYPE_NC, &ctrl_flags);
> +
> + total_pages = bo->base.size >> PAGE_SHIFT;
> + pages_per_xcc = total_pages;
> + do_div(pages_per_xcc, num_xcc);
> +
> + amdgpu_res_first(NULL, mm_node->start, total_pages, &cursor_gart);
> + amdgpu_res_first(bo->resource, 0, bo->resource->size, &cursor);
> +
> + for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
> + u64 start_page;
> + u64 npages, n;
> + u64 pa;
> +
> + /* MQD page: use flags MTYPE_RW */
> + start_page = cursor_gart.start;
> + pa = cursor.start + adev->vm_manager.vram_base_offset;
> + n = 1;
> + amdgpu_gart_map_vram_range(adev, pa, start_page, n,
> + flags, NULL);
> +
> + /* Ctrl stack pages: modify the memory type to NC */
> + npages = pages_per_xcc - 1;
> + while (npages) {
> + amdgpu_res_next(&cursor_gart, n);
> + amdgpu_res_next(&cursor, n * PAGE_SIZE);
> +
> + start_page = cursor_gart.start;
> + pa = cursor.start + adev->vm_manager.vram_base_offset;
> + n = min3(cursor.size / PAGE_SIZE, cursor_gart.size, npages);
> +
> + amdgpu_gart_map_vram_range(adev, pa, start_page, n,
> + ctrl_flags, NULL);
> +
> + npages -= n;
> + }
> +
> + amdgpu_res_next(&cursor_gart, n);
> + amdgpu_res_next(&cursor, n * PAGE_SIZE);
> + }
> +
> + amdgpu_gart_invalidate_tlb(adev);
> + *gpu_addr = mm_node->start << PAGE_SHIFT;
> + return 0;
> +}
> +
> static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
> struct ttm_buffer_object *tbo,
> uint64_t flags)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 143201ecea3f..3751f010f14a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -140,7 +140,6 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
>
> bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
> void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
> -
> int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr,
> struct drm_mm_node *mm_node,
> u64 num_pages,
> @@ -189,8 +188,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
> struct dma_resv *resv,
> struct dma_fence **f,
> u64 k_job_id);
> -
> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
> +int amdgpu_ttm_gart_bind_gfx9_mqd_vram(struct amdgpu_device *adev,
> + struct amdgpu_bo *abo,
> + struct drm_mm_node *mm_node,
> + u64 *gpu_addr);
> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
> uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> index f78b249e1a41..edb72f4ef82d 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> @@ -225,6 +225,8 @@ void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd,
> struct kfd_mem_obj *mqd_mem_obj)
> {
> if (mqd_mem_obj->mem) {
> + amdgpu_gtt_mgr_free_entries(&mm->dev->adev->mman.gtt_mgr,
> + &mqd_mem_obj->mm_node);
> amdgpu_amdkfd_free_kernel_mem(mm->dev->adev, &mqd_mem_obj->mem);
> kfree(mqd_mem_obj);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index d867dccae675..1893dabb823a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -160,6 +160,18 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
> kfree(mqd_mem_obj);
> return NULL;
> }
> +
> + if (mqd_on_vram(node->adev)) {
> + retval = amdgpu_ttm_gart_bind_gfx9_mqd_vram(node->adev,
> + mqd_mem_obj->mem,
> + &(mqd_mem_obj->mm_node),
> + &(mqd_mem_obj->gpu_addr));
> + if (retval) {
> + amdgpu_amdkfd_free_kernel_mem(node->adev, &(mqd_mem_obj->mem));
> + kfree(mqd_mem_obj);
> + return NULL;
> + }
> + }
> } else {
> retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
> &mqd_mem_obj);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index 042b8e747b5b..7c95cc9e2f0d 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -253,6 +253,7 @@ struct kfd_mem_obj {
> uint64_t gpu_addr;
> uint32_t *cpu_ptr;
> void *mem;
> + struct drm_mm_node mm_node;
> };
>
> struct kfd_vmid_info {
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 2/3] drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM
2026-01-07 19:23 ` [PATCH v1 2/3] drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM Philip Yang
@ 2026-01-09 23:19 ` Kuehling, Felix
0 siblings, 0 replies; 6+ messages in thread
From: Kuehling, Felix @ 2026-01-09 23:19 UTC (permalink / raw)
To: Philip Yang, amd-gfx
Cc: christian.koenig, david.yatsin, kent.russell, jay.cornwall
On 2026-01-07 14:23, Philip Yang wrote:
> To reduce queue switch latency further, move MQD to VRAM domain, CP
> access MQD and control stack via FB aperture, this requires contiguous
> pages.
>
> After MQD is initialized, updated or restored, flush HDP to guarantee
> the data is written to HBM and GPU cache is invalidated, then CP will
> read the new MQD.
>
> Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Patches 1 and 2 are
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 3 ++-
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 23 ++++++++++++++++++-
> 2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index 39c0b5a385c9..c1ffae9e96d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -329,7 +329,8 @@ int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size,
> bp.size = size;
> bp.byte_align = PAGE_SIZE;
> bp.domain = domain;
> - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> + AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> bp.type = ttm_bo_type_kernel;
> bp.resv = NULL;
> bp.bo_ptr_size = sizeof(struct amdgpu_bo);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index d234db138182..d867dccae675 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -109,6 +109,17 @@ static void set_priority(struct v9_mqd *m, struct queue_properties *q)
> m->cp_hqd_queue_priority = q->priority;
> }
>
> +static bool mqd_on_vram(struct amdgpu_device *adev)
> +{
> + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
> + case IP_VERSION(9, 4, 3):
> + case IP_VERSION(9, 5, 0):
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
> struct queue_properties *q)
> {
> @@ -139,7 +150,8 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
> (ALIGN(q->ctl_stack_size, PAGE_SIZE) +
> ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
> NUM_XCC(node->xcc_mask),
> - AMDGPU_GEM_DOMAIN_GTT,
> + mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM :
> + AMDGPU_GEM_DOMAIN_GTT,
> &(mqd_mem_obj->mem),
> &(mqd_mem_obj->gpu_addr),
> (void *)&(mqd_mem_obj->cpu_ptr), true);
> @@ -739,6 +751,9 @@ static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
> *gart_addr = xcc_gart_addr;
> }
> }
> +
> + if (mqd_on_vram(mm->dev->adev))
> + amdgpu_device_flush_hdp(mm->dev->adev, NULL);
> }
>
> static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
> @@ -775,6 +790,9 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
> m->pm4_target_xcc_in_xcp = q->pm4_target_xcc;
> }
> }
> +
> + if (mqd_on_vram(mm->dev->adev))
> + amdgpu_device_flush_hdp(mm->dev->adev, NULL);
> }
>
> static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
> @@ -813,6 +831,9 @@ static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
> (uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size,
> mqd_ctl_stack_size);
> }
> +
> + if (mqd_on_vram(mm->dev->adev))
> + amdgpu_device_flush_hdp(mm->dev->adev, NULL);
> }
> static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
> enum kfd_preempt_type type, unsigned int timeout,
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-01-09 23:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-07 19:23 [PATCH v1 0/3] Move gfx9.4.3 and gfx 9.5.0 MQD to HBM Philip Yang
2026-01-07 19:23 ` [PATCH v1 1/3] drm/amdkfd: Add domain parameter to alloc kernel BO Philip Yang
2026-01-07 19:23 ` [PATCH v1 2/3] drm/amdkfd: Move gfx9.4.3 and gfx 9.5 MQD to HBM Philip Yang
2026-01-09 23:19 ` Kuehling, Felix
2026-01-07 19:23 ` [PATCH v1 3/3] drm/amdkfd: Map VRAM MQD on GART Philip Yang
2026-01-08 13:24 ` Christian König
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