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From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 09/42] drm/amdgpu/gfx9.4.2: switch to using job for IBs
Date: Thu, 8 Jan 2026 09:48:10 -0500	[thread overview]
Message-ID: <20260108144843.493816-10-alexander.deucher@amd.com> (raw)
In-Reply-To: <20260108144843.493816-1-alexander.deucher@amd.com>

Switch to using a job structure for IBs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 26 ++++++++-----------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index 8058ea91ecafd..424b05b84ea74 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -345,12 +345,13 @@ const struct soc15_reg_entry sgpr64_init_regs_aldebaran[] = {
 
 static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
 				 struct amdgpu_ring *ring,
-				 struct amdgpu_ib *ib,
 				 const u32 *shader_ptr, u32 shader_size,
 				 const struct soc15_reg_entry *init_regs, u32 regs_size,
 				 u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,
 				 struct dma_fence **fence_ptr)
 {
+	struct amdgpu_job *job;
+	struct amdgpu_ib *ib;
 	int r, i;
 	uint32_t total_size, shader_offset;
 	u64 gpu_addr;
@@ -360,10 +361,9 @@ static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
 	shader_offset = total_size;
 	total_size += ALIGN(shader_size, 256);
 
-	/* allocate an indirect buffer to put the commands in */
-	memset(ib, 0, sizeof(*ib));
-	r = amdgpu_ib_get(adev, NULL, total_size,
-					AMDGPU_IB_POOL_DIRECT, ib);
+	r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, total_size,
+				     AMDGPU_IB_POOL_DIRECT, &job,
+				     AMDGPU_KERNEL_JOB_ID_RUN_SHADER);
 	if (r) {
 		dev_err(adev->dev, "failed to get ib (%d).\n", r);
 		return r;
@@ -408,11 +408,11 @@ static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
 	ib->ptr[ib->length_dw++] =
 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
 
-	/* shedule the ib on the ring */
-	r = amdgpu_ib_schedule(ring, 1, ib, NULL, fence_ptr);
+	/* schedule the ib on the ring */
+	r = amdgpu_job_submit_direct(job, ring, fence_ptr);
 	if (r) {
 		dev_err(adev->dev, "ib submit failed (%d).\n", r);
-		amdgpu_ib_free(ib, NULL);
+		amdgpu_job_free(job);
 	}
 	return r;
 }
@@ -493,7 +493,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
 	int wb_size = adev->gfx.config.max_shader_engines *
 			 CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
 	struct amdgpu_ib wb_ib;
-	struct amdgpu_ib disp_ibs[3];
 	struct dma_fence *fences[3];
 	u32 pattern[3] = { 0x1, 0x5, 0xa };
 
@@ -514,7 +513,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
 
 	r = gfx_v9_4_2_run_shader(adev,
 			&adev->gfx.compute_ring[0],
-			&disp_ibs[0],
 			sgpr112_init_compute_shader_aldebaran,
 			sizeof(sgpr112_init_compute_shader_aldebaran),
 			sgpr112_init_regs_aldebaran,
@@ -539,7 +537,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
 
 	r = gfx_v9_4_2_run_shader(adev,
 			&adev->gfx.compute_ring[1],
-			&disp_ibs[1],
 			sgpr96_init_compute_shader_aldebaran,
 			sizeof(sgpr96_init_compute_shader_aldebaran),
 			sgpr96_init_regs_aldebaran,
@@ -579,7 +576,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
 	memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
 	r = gfx_v9_4_2_run_shader(adev,
 			&adev->gfx.compute_ring[0],
-			&disp_ibs[2],
 			sgpr64_init_compute_shader_aldebaran,
 			sizeof(sgpr64_init_compute_shader_aldebaran),
 			sgpr64_init_regs_aldebaran,
@@ -611,13 +607,10 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
 	}
 
 disp2_failed:
-	amdgpu_ib_free(&disp_ibs[2], NULL);
 	dma_fence_put(fences[2]);
 disp1_failed:
-	amdgpu_ib_free(&disp_ibs[1], NULL);
 	dma_fence_put(fences[1]);
 disp0_failed:
-	amdgpu_ib_free(&disp_ibs[0], NULL);
 	dma_fence_put(fences[0]);
 pro_end:
 	amdgpu_ib_free(&wb_ib, NULL);
@@ -637,7 +630,6 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
 	int wb_size = adev->gfx.config.max_shader_engines *
 			 CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
 	struct amdgpu_ib wb_ib;
-	struct amdgpu_ib disp_ib;
 	struct dma_fence *fence;
 	u32 pattern = 0xa;
 
@@ -657,7 +649,6 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
 
 	r = gfx_v9_4_2_run_shader(adev,
 			&adev->gfx.compute_ring[0],
-			&disp_ib,
 			vgpr_init_compute_shader_aldebaran,
 			sizeof(vgpr_init_compute_shader_aldebaran),
 			vgpr_init_regs_aldebaran,
@@ -687,7 +678,6 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
 	}
 
 disp_failed:
-	amdgpu_ib_free(&disp_ib, NULL);
 	dma_fence_put(fence);
 pro_end:
 	amdgpu_ib_free(&wb_ib, NULL);
-- 
2.52.0


  parent reply	other threads:[~2026-01-08 14:49 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-08 14:48 [PATCH 00/42] Improvements for IB handling Alex Deucher
2026-01-08 14:48 ` [PATCH 01/42] drm/amdgpu/jpeg4.0.3: remove redundant sr-iov check Alex Deucher
2026-01-08 14:48 ` [PATCH 02/42] drm/amdgpu: fix error handling in ib_schedule() Alex Deucher
2026-01-08 14:48 ` [PATCH 03/42] drm/amdgpu: add new job ids Alex Deucher
2026-01-08 14:48 ` [PATCH 04/42] drm/amdgpu/vpe: switch to using job for IBs Alex Deucher
2026-01-08 14:48 ` [PATCH 05/42] drm/amdgpu/gfx6: " Alex Deucher
2026-01-08 14:48 ` [PATCH 06/42] drm/amdgpu/gfx7: " Alex Deucher
2026-01-08 14:48 ` [PATCH 07/42] drm/amdgpu/gfx8: " Alex Deucher
2026-01-08 14:48 ` [PATCH 08/42] drm/amdgpu/gfx9: " Alex Deucher
2026-01-08 14:48 ` Alex Deucher [this message]
2026-01-08 14:48 ` [PATCH 10/42] drm/amdgpu/gfx9.4.3: " Alex Deucher
2026-01-08 14:48 ` [PATCH 11/42] drm/amdgpu/gfx10: " Alex Deucher
2026-01-08 14:48 ` [PATCH 12/42] drm/amdgpu/gfx11: " Alex Deucher
2026-01-08 14:48 ` [PATCH 13/42] drm/amdgpu/gfx12: " Alex Deucher
2026-01-08 14:48 ` [PATCH 14/42] drm/amdgpu/gfx12.1: " Alex Deucher
2026-01-08 14:48 ` [PATCH 15/42] drm/amdgpu/si_dma: " Alex Deucher
2026-01-08 14:48 ` [PATCH 16/42] drm/amdgpu/cik_sdma: " Alex Deucher
2026-01-08 14:48 ` [PATCH 17/42] drm/amdgpu/sdma2.4: " Alex Deucher
2026-01-08 14:48 ` [PATCH 18/42] drm/amdgpu/sdma3: " Alex Deucher
2026-01-08 14:48 ` [PATCH 19/42] drm/amdgpu/sdma4: " Alex Deucher
2026-01-08 14:48 ` [PATCH 20/42] drm/amdgpu/sdma4.4.2: " Alex Deucher
2026-01-08 14:48 ` [PATCH 21/42] drm/amdgpu/sdma5: " Alex Deucher
2026-01-08 14:48 ` [PATCH 22/42] drm/amdgpu/sdma5.2: " Alex Deucher
2026-01-08 14:48 ` [PATCH 23/42] drm/amdgpu/sdma6: " Alex Deucher
2026-01-08 14:48 ` [PATCH 24/42] drm/amdgpu/sdma7: " Alex Deucher
2026-01-08 14:48 ` [PATCH 25/42] drm/amdgpu/sdma7.1: " Alex Deucher
2026-01-08 14:48 ` [PATCH 26/42] drm/amdgpu: require a job to schedule an IB Alex Deucher
2026-01-08 14:48 ` [PATCH 27/42] drm/amdgpu: mark fences with errors before ring reset Alex Deucher
2026-01-13 13:12   ` Christian König
2026-01-13 15:39     ` Alex Deucher
2026-01-13 21:23       ` Alex Deucher
2026-01-08 14:48 ` [PATCH 28/42] drm/amdgpu: rename amdgpu_fence_driver_guilty_force_completion() Alex Deucher
2026-01-08 14:48 ` [PATCH 29/42] drm/amdgpu: don't call drm_sched_stop/start() in asic reset Alex Deucher
2026-01-13 13:17   ` Christian König
2026-01-13 13:34     ` Philipp Stanner
2026-01-13 14:37       ` Christian König
2026-01-13 15:16         ` Philipp Stanner
2026-01-13 16:46         ` Alex Deucher
2026-01-08 14:48 ` [PATCH 30/42] drm/amdgpu: drop drm_sched_increase_karma() Alex Deucher
2026-01-13 13:22   ` Christian König
2026-01-13 21:27     ` Alex Deucher
2026-01-13 21:45       ` Alex Deucher
2026-01-08 14:48 ` [PATCH 31/42] drm/amdgpu: plumb timedout fence through to force completion Alex Deucher
2026-01-08 14:48 ` [PATCH 32/42] drm/amdgpu: change function signature for emit_pipeline_sync() Alex Deucher
2026-01-08 14:48 ` [PATCH 33/42] drm/amdgpu: drop extra parameter for vm_flush Alex Deucher
2026-01-08 14:48 ` [PATCH 34/42] drm/amdgpu: move need_ctx_switch into amdgpu_job Alex Deucher
2026-01-08 14:48 ` [PATCH 35/42] drm/amdgpu: store vm flush state in amdgpu_job Alex Deucher
2026-01-08 14:48 ` [PATCH 36/42] drm/amdgpu: split fence init and emit logic Alex Deucher
2026-01-08 14:48 ` [PATCH 37/42] drm/amdgpu: split vm flush and vm flush " Alex Deucher
2026-01-08 14:48 ` [PATCH 38/42] drm/amdgpu: split ib schedule and ib " Alex Deucher
2026-01-08 14:48 ` [PATCH 39/42] drm/amdgpu: move drm sched stop/start into amdgpu_job_timedout() Alex Deucher
2026-01-08 14:48 ` [PATCH 40/42] drm/amdgpu: add an all_instance_rings_reset ring flag Alex Deucher
2026-01-08 14:48 ` [PATCH 41/42] drm/amdgpu: rework reset reemit handling Alex Deucher
2026-01-08 14:48 ` [PATCH 42/42] drm/amdgpu: simplify per queue reset code Alex Deucher
2026-01-13 13:31 ` [PATCH 00/42] Improvements for IB handling Christian König
2026-01-13 14:10   ` Alex Deucher
2026-01-13 14:47     ` Christian König
2026-01-13 15:34       ` Alex Deucher
2026-01-13 22:36         ` Alex Deucher
2026-01-14 10:45           ` Christian König
2026-01-14 16:36             ` Alex Deucher
2026-01-15  9:07               ` Christian König
2026-01-15 14:08                 ` Alex Deucher
2026-01-15 14:54                   ` Christian König
2026-01-13 21:17   ` Alex Deucher
2026-01-14 10:35     ` Christian König

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