* [PATCH 2/4] drm/amdgpu: Use AMDGPU_MQD_SIZE_ALIGN in KGD
2026-01-26 10:25 [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Lang Yu
@ 2026-01-26 10:25 ` Lang Yu
2026-01-26 10:25 ` [PATCH 3/4] drm/amdkfd: Adjust parameter of allocate_mqd Lang Yu
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Lang Yu @ 2026-01-26 10:25 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang, Alex Deucher, Mukul Joshi, David Belanger, Lang Yu
Use AMDGPU_MQD_SIZE_ALIGN for both kernel and user queue.
Signed-off-by: Lang Yu <lang.yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 18 ++++++++++--------
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 3 ++-
3 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 6abe5103a78d..4fede701beb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -385,6 +385,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
struct amdgpu_ring *ring = &kiq->ring;
u32 domain = AMDGPU_GEM_DOMAIN_GTT;
+ u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size);
+ u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size);
#if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
/* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
@@ -424,17 +426,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
if (!ring->mqd_obj) {
- r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
- domain, &ring->mqd_obj,
+ r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size),
+ PAGE_SIZE, domain, &ring->mqd_obj,
&ring->mqd_gpu_addr, &ring->mqd_ptr);
if (r) {
dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
return r;
}
- ring->mqd_size = mqd_size;
+ ring->mqd_size = gfx_mqd_size;
/* prepare MQD backup */
- adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL);
+ adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL);
if (!adev->gfx.me.mqd_backup[i]) {
dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
return -ENOMEM;
@@ -448,17 +450,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
j = i + xcc_id * adev->gfx.num_compute_rings;
ring = &adev->gfx.compute_ring[j];
if (!ring->mqd_obj) {
- r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
- domain, &ring->mqd_obj,
+ r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size),
+ PAGE_SIZE, domain, &ring->mqd_obj,
&ring->mqd_gpu_addr, &ring->mqd_ptr);
if (r) {
dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
return r;
}
- ring->mqd_size = mqd_size;
+ ring->mqd_size = compute_mqd_size;
/* prepare MQD backup */
- adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL);
+ adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL);
if (!adev->gfx.mec.mqd_backup[j]) {
dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 86cc90a66296..4dabcd7c9f5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -2235,7 +2235,7 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size :
- sizeof(struct v12_1_compute_mqd);
+ AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size);
mqd->cp_hqd_active = prop->hqd_active;
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index f2309d72bbe6..0319c40c7f7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
@@ -289,7 +289,8 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue,
return -ENOMEM;
}
- r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size);
+ r = amdgpu_userq_create_object(uq_mgr, &queue->mqd,
+ AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size));
if (r) {
DRM_ERROR("Failed to create MQD object for userqueue\n");
goto free_props;
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/4] drm/amdkfd: Adjust parameter of allocate_mqd
2026-01-26 10:25 [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Lang Yu
2026-01-26 10:25 ` [PATCH 2/4] drm/amdgpu: Use AMDGPU_MQD_SIZE_ALIGN in KGD Lang Yu
@ 2026-01-26 10:25 ` Lang Yu
2026-01-26 10:25 ` [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager Lang Yu
2026-01-27 16:26 ` [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Joshi, Mukul
3 siblings, 0 replies; 9+ messages in thread
From: Lang Yu @ 2026-01-26 10:25 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang, Alex Deucher, Mukul Joshi, David Belanger, Lang Yu
Make allocate_mqd consistent with other callbacks.
Prepare for next patch to use mqd_manager->mqd_size.
Signed-off-by: Lang Yu <lang.yu@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 6 ++++--
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 6 +++---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 3 ++-
11 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index b542de9d50d1..804851632c4c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -676,7 +676,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm,
/* Temporarily release dqm lock to avoid a circular lock dependency */
dqm_unlock(dqm);
- q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
+ q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties);
dqm_lock(dqm);
if (!q->mqd_mem_obj) {
@@ -2002,7 +2002,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
q->properties.tba_addr = qpd->tba_addr;
q->properties.tma_addr = qpd->tma_addr;
- q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
+ q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties);
if (!q->mqd_mem_obj) {
retval = -ENOMEM;
goto out_deallocate_doorbell;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 961a4b84e974..d987ff7ccfc9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -130,7 +130,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev,
kq->queue->device = dev;
- kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr->dev,
+ kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr,
&kq->queue->properties);
if (!kq->queue->mqd_mem_obj)
goto err_allocate_mqd;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index f78b249e1a41..ceb6566ff3e1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -46,9 +46,10 @@ int pipe_priority_map[] = {
KFD_PIPE_PRIORITY_CS_HIGH
};
-struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properties *q)
+struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q)
{
struct kfd_mem_obj *mqd_mem_obj;
+ struct kfd_node *dev = mm->dev;
mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
if (!mqd_mem_obj)
@@ -61,10 +62,11 @@ struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properti
return mqd_mem_obj;
}
-struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev,
+struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
struct kfd_mem_obj *mqd_mem_obj;
+ struct kfd_node *dev = mm->dev;
uint64_t offset;
mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
index 17cc1f25c8d0..2429d278ef0e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
@@ -68,7 +68,7 @@
*/
extern int pipe_priority_map[];
struct mqd_manager {
- struct kfd_mem_obj* (*allocate_mqd)(struct kfd_node *kfd,
+ struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm,
struct queue_properties *q);
void (*init_mqd)(struct mqd_manager *mm, void **mqd,
@@ -153,10 +153,10 @@ struct mqd_user_context_save_area_header {
uint32_t wave_state_size;
};
-struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev,
+struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm,
struct queue_properties *q);
-struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev,
+struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm,
struct queue_properties *q);
void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd,
struct kfd_mem_obj *mqd_mem_obj);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 05f3ac2eaef9..90ac3a30e81d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -73,9 +73,10 @@ static void set_priority(struct cik_mqd *m, struct queue_properties *q)
m->cp_hqd_queue_priority = q->priority;
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ struct kfd_node *kfd = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd),
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 1695dd78ede8..97055f808d4a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -73,9 +73,10 @@ static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
m->cp_hqd_queue_priority = q->priority;
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ struct kfd_node *kfd = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 3c0ae28c5923..5c44d0987737 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -99,9 +99,10 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q)
m->cp_hqd_queue_priority = q->priority;
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
int size;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
index 729df66ebfb3..b7ac2dea8775 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
@@ -80,9 +80,10 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q)
m->cp_hqd_queue_priority = q->priority;
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
/*
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
index 558216395a4d..0b0d802a0917 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
@@ -145,9 +145,10 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q
m->cp_hqd_queue_priority = q->priority;
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
unsigned int size;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index d867dccae675..dcf4bbfa641b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -120,10 +120,11 @@ static bool mqd_on_vram(struct amdgpu_device *adev)
}
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
int retval;
+ struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj = NULL;
/* For V9 only, due to a HW bug, the control stack of a user mode
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index c1fafc502515..09483f0862d4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -76,9 +76,10 @@ static void set_priority(struct vi_mqd *m, struct queue_properties *q)
m->cp_hqd_queue_priority = q->priority;
}
-static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd,
+static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ struct kfd_node *kfd = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager
2026-01-26 10:25 [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Lang Yu
2026-01-26 10:25 ` [PATCH 2/4] drm/amdgpu: Use AMDGPU_MQD_SIZE_ALIGN in KGD Lang Yu
2026-01-26 10:25 ` [PATCH 3/4] drm/amdkfd: Adjust parameter of allocate_mqd Lang Yu
@ 2026-01-26 10:25 ` Lang Yu
2026-01-27 15:16 ` Belanger, David
2026-01-27 16:22 ` Joshi, Mukul
2026-01-27 16:26 ` [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Joshi, Mukul
3 siblings, 2 replies; 9+ messages in thread
From: Lang Yu @ 2026-01-26 10:25 UTC (permalink / raw)
To: amd-gfx; +Cc: Hawking Zhang, Alex Deucher, Mukul Joshi, David Belanger, Lang Yu
MES is enabled by default from gfx11+.
Signed-off-by: Lang Yu <lang.yu@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 3 ++
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 22 +++-----------
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 10 +++----
.../drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 29 ++++---------------
4 files changed, 17 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index ceb6566ff3e1..d88d0de58edd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -292,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj,
uint64_t kfd_mqd_stride(struct mqd_manager *mm,
struct queue_properties *q)
{
+ if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0))
+ return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
+
return mm->mqd_size;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 5c44d0987737..7e5a7ab6d0c0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -102,20 +102,11 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q)
static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
- int size;
-
- /*
- * MES write to areas beyond MQD size. So allocate
- * 1 PAGE_SIZE memory for MQD is MES is enabled.
- */
- if (node->kfd->shared_resources.enable_mes)
- size = PAGE_SIZE;
- else
- size = sizeof(struct v11_compute_mqd);
- if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
+ if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
return NULL;
return mqd_mem_obj;
@@ -127,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
{
uint64_t addr;
struct v11_compute_mqd *m;
- int size;
+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
addr = mqd_mem_obj->gpu_addr;
- if (mm->dev->kfd->shared_resources.enable_mes)
- size = PAGE_SIZE;
- else
- size = sizeof(struct v11_compute_mqd);
-
- memset(m, 0, size);
+ memset(m, 0, mqd_size);
m->header = 0xC0310800;
m->compute_pipelinestat_enable = 1;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
index b7ac2dea8775..a51f217329db 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
@@ -83,14 +83,11 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q)
static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
- /*
- * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond
- * struct MQD size.
- */
- if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj))
+ if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
return NULL;
return mqd_mem_obj;
@@ -102,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
{
uint64_t addr;
struct v12_compute_mqd *m;
+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr;
addr = mqd_mem_obj->gpu_addr;
- memset(m, 0, PAGE_SIZE);
+ memset(m, 0, mqd_size);
m->header = 0xC0310800;
m->compute_pipelinestat_enable = 1;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
index 0b0d802a0917..d0776ba2cc99 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
@@ -32,17 +32,6 @@
#include "amdgpu_amdkfd.h"
#include "kfd_device_queue_manager.h"
-#define MQD_SIZE (2 * PAGE_SIZE)
-
-static uint64_t mqd_stride_v12_1(struct mqd_manager *mm,
- struct queue_properties *q)
-{
- if (q->type == KFD_QUEUE_TYPE_COMPUTE)
- return MQD_SIZE;
- else
- return PAGE_SIZE;
-}
-
static inline struct v12_1_compute_mqd *get_mqd(void *mqd)
{
return (struct v12_1_compute_mqd *)mqd;
@@ -148,21 +137,14 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q
static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
struct queue_properties *q)
{
+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
struct kfd_node *node = mm->dev;
struct kfd_mem_obj *mqd_mem_obj;
- unsigned int size;
- /*
- * Allocate two PAGE_SIZE memory for Compute MQD as MES writes to areas beyond
- * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE.
- * For SDMA MQD, we allocate 1 Page_size.
- */
if (q->type == KFD_QUEUE_TYPE_COMPUTE)
- size = MQD_SIZE * NUM_XCC(node->xcc_mask);
- else
- size = PAGE_SIZE;
+ mqd_size *= NUM_XCC(node->xcc_mask);
- if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
+ if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
return NULL;
return mqd_mem_obj;
@@ -174,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
{
uint64_t addr;
struct v12_1_compute_mqd *m;
+ u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr;
addr = mqd_mem_obj->gpu_addr;
- memset(m, 0, MQD_SIZE);
+ memset(m, 0, mqd_size);
m->header = 0xC0310800;
m->compute_pipelinestat_enable = 1;
@@ -681,7 +664,7 @@ struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type,
mqd->is_occupied = kfd_is_occupied_cp;
mqd->mqd_size = sizeof(struct v12_1_compute_mqd);
mqd->get_wave_state = get_wave_state_v12_1;
- mqd->mqd_stride = mqd_stride_v12_1;
+ mqd->mqd_stride = kfd_mqd_stride;
#if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd;
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager
2026-01-26 10:25 ` [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager Lang Yu
@ 2026-01-27 15:16 ` Belanger, David
2026-01-27 16:22 ` Joshi, Mukul
1 sibling, 0 replies; 9+ messages in thread
From: Belanger, David @ 2026-01-27 15:16 UTC (permalink / raw)
To: Lang Yu, amd-gfx; +Cc: Hawking Zhang, Alex Deucher, Mukul Joshi
Full set reviewed.
Reviewed-by: David Belanger <david.belanger@amd.com>
On 1/26/2026 5:25 AM, Lang Yu wrote:
> MES is enabled by default from gfx11+.
>
> Signed-off-by: Lang Yu <lang.yu@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 3 ++
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 22 +++-----------
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 10 +++----
> .../drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 29 ++++---------------
> 4 files changed, 17 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> index ceb6566ff3e1..d88d0de58edd 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> @@ -292,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj,
> uint64_t kfd_mqd_stride(struct mqd_manager *mm,
> struct queue_properties *q)
> {
> + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0))
> + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> +
> return mm->mqd_size;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> index 5c44d0987737..7e5a7ab6d0c0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> @@ -102,20 +102,11 @@ static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q)
> static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
> struct queue_properties *q)
> {
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> struct kfd_node *node = mm->dev;
> struct kfd_mem_obj *mqd_mem_obj;
> - int size;
> -
> - /*
> - * MES write to areas beyond MQD size. So allocate
> - * 1 PAGE_SIZE memory for MQD is MES is enabled.
> - */
> - if (node->kfd->shared_resources.enable_mes)
> - size = PAGE_SIZE;
> - else
> - size = sizeof(struct v11_compute_mqd);
>
> - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
> return NULL;
>
> return mqd_mem_obj;
> @@ -127,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
> {
> uint64_t addr;
> struct v11_compute_mqd *m;
> - int size;
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
>
> m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
> addr = mqd_mem_obj->gpu_addr;
>
> - if (mm->dev->kfd->shared_resources.enable_mes)
> - size = PAGE_SIZE;
> - else
> - size = sizeof(struct v11_compute_mqd);
> -
> - memset(m, 0, size);
> + memset(m, 0, mqd_size);
>
> m->header = 0xC0310800;
> m->compute_pipelinestat_enable = 1;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> index b7ac2dea8775..a51f217329db 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> @@ -83,14 +83,11 @@ static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q)
> static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
> struct queue_properties *q)
> {
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> struct kfd_node *node = mm->dev;
> struct kfd_mem_obj *mqd_mem_obj;
>
> - /*
> - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond
> - * struct MQD size.
> - */
> - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj))
> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
> return NULL;
>
> return mqd_mem_obj;
> @@ -102,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
> {
> uint64_t addr;
> struct v12_compute_mqd *m;
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>
> m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr;
> addr = mqd_mem_obj->gpu_addr;
>
> - memset(m, 0, PAGE_SIZE);
> + memset(m, 0, mqd_size);
>
> m->header = 0xC0310800;
> m->compute_pipelinestat_enable = 1;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> index 0b0d802a0917..d0776ba2cc99 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> @@ -32,17 +32,6 @@
> #include "amdgpu_amdkfd.h"
> #include "kfd_device_queue_manager.h"
>
> -#define MQD_SIZE (2 * PAGE_SIZE)
> -
> -static uint64_t mqd_stride_v12_1(struct mqd_manager *mm,
> - struct queue_properties *q)
> -{
> - if (q->type == KFD_QUEUE_TYPE_COMPUTE)
> - return MQD_SIZE;
> - else
> - return PAGE_SIZE;
> -}
> -
> static inline struct v12_1_compute_mqd *get_mqd(void *mqd)
> {
> return (struct v12_1_compute_mqd *)mqd;
> @@ -148,21 +137,14 @@ static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q
> static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
> struct queue_properties *q)
> {
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> struct kfd_node *node = mm->dev;
> struct kfd_mem_obj *mqd_mem_obj;
> - unsigned int size;
>
> - /*
> - * Allocate two PAGE_SIZE memory for Compute MQD as MES writes to areas beyond
> - * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE.
> - * For SDMA MQD, we allocate 1 Page_size.
> - */
> if (q->type == KFD_QUEUE_TYPE_COMPUTE)
> - size = MQD_SIZE * NUM_XCC(node->xcc_mask);
> - else
> - size = PAGE_SIZE;
> + mqd_size *= NUM_XCC(node->xcc_mask);
>
> - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
> return NULL;
>
> return mqd_mem_obj;
> @@ -174,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
> {
> uint64_t addr;
> struct v12_1_compute_mqd *m;
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>
> m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr;
> addr = mqd_mem_obj->gpu_addr;
>
> - memset(m, 0, MQD_SIZE);
> + memset(m, 0, mqd_size);
>
> m->header = 0xC0310800;
> m->compute_pipelinestat_enable = 1;
> @@ -681,7 +664,7 @@ struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type,
> mqd->is_occupied = kfd_is_occupied_cp;
> mqd->mqd_size = sizeof(struct v12_1_compute_mqd);
> mqd->get_wave_state = get_wave_state_v12_1;
> - mqd->mqd_stride = mqd_stride_v12_1;
> + mqd->mqd_stride = kfd_mqd_stride;
> #if defined(CONFIG_DEBUG_FS)
> mqd->debugfs_show_mqd = debugfs_show_mqd;
> #endif
^ permalink raw reply [flat|nested] 9+ messages in thread* RE: [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager
2026-01-26 10:25 ` [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager Lang Yu
2026-01-27 15:16 ` Belanger, David
@ 2026-01-27 16:22 ` Joshi, Mukul
2026-01-28 0:45 ` Yu, Lang
1 sibling, 1 reply; 9+ messages in thread
From: Joshi, Mukul @ 2026-01-27 16:22 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking, Deucher, Alexander, Belanger, David
[AMD Official Use Only - AMD Internal Distribution Only]
> -----Original Message-----
> From: Yu, Lang <Lang.Yu@amd.com>
> Sent: Monday, January 26, 2026 5:25 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Joshi, Mukul <Mukul.Joshi@amd.com>;
> Belanger, David <David.Belanger@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> Subject: [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+
> kfd mqd manager
>
> MES is enabled by default from gfx11+.
>
> Signed-off-by: Lang Yu <lang.yu@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 3 ++
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 22 +++-----------
> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 10 +++----
> .../drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 29 ++++---------------
> 4 files changed, 17 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> index ceb6566ff3e1..d88d0de58edd 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
> @@ -292,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev,
> struct kfd_mem_obj *mqd_mem_obj, uint64_t kfd_mqd_stride(struct
> mqd_manager *mm,
> struct queue_properties *q)
> {
> + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0))
> + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> +
> return mm->mqd_size;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> index 5c44d0987737..7e5a7ab6d0c0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
> @@ -102,20 +102,11 @@ static void set_priority(struct v11_compute_mqd
> *m, struct queue_properties *q) static struct kfd_mem_obj
> *allocate_mqd(struct mqd_manager *mm,
> struct queue_properties *q)
> {
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> struct kfd_node *node = mm->dev;
> struct kfd_mem_obj *mqd_mem_obj;
> - int size;
> -
> - /*
> - * MES write to areas beyond MQD size. So allocate
> - * 1 PAGE_SIZE memory for MQD is MES is enabled.
> - */
> - if (node->kfd->shared_resources.enable_mes)
> - size = PAGE_SIZE;
> - else
> - size = sizeof(struct v11_compute_mqd);
>
> - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
> return NULL;
>
> return mqd_mem_obj;
> @@ -127,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm,
> void **mqd, {
> uint64_t addr;
> struct v11_compute_mqd *m;
> - int size;
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
>
> m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
> addr = mqd_mem_obj->gpu_addr;
>
> - if (mm->dev->kfd->shared_resources.enable_mes)
> - size = PAGE_SIZE;
> - else
> - size = sizeof(struct v11_compute_mqd);
> -
> - memset(m, 0, size);
> + memset(m, 0, mqd_size);
>
> m->header = 0xC0310800;
> m->compute_pipelinestat_enable = 1;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> index b7ac2dea8775..a51f217329db 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
> @@ -83,14 +83,11 @@ static void set_priority(struct v12_compute_mqd *m,
> struct queue_properties *q) static struct kfd_mem_obj *allocate_mqd(struct
> mqd_manager *mm,
> struct queue_properties *q)
> {
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> struct kfd_node *node = mm->dev;
> struct kfd_mem_obj *mqd_mem_obj;
>
> - /*
> - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas
> beyond
> - * struct MQD size.
> - */
> - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj))
> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
> return NULL;
>
> return mqd_mem_obj;
> @@ -102,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void
> **mqd, {
> uint64_t addr;
> struct v12_compute_mqd *m;
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>
> m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr;
> addr = mqd_mem_obj->gpu_addr;
>
> - memset(m, 0, PAGE_SIZE);
> + memset(m, 0, mqd_size);
>
> m->header = 0xC0310800;
> m->compute_pipelinestat_enable = 1;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> index 0b0d802a0917..d0776ba2cc99 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
> @@ -32,17 +32,6 @@
> #include "amdgpu_amdkfd.h"
> #include "kfd_device_queue_manager.h"
>
> -#define MQD_SIZE (2 * PAGE_SIZE)
> -
> -static uint64_t mqd_stride_v12_1(struct mqd_manager *mm,
> - struct queue_properties *q)
> -{
> - if (q->type == KFD_QUEUE_TYPE_COMPUTE)
> - return MQD_SIZE;
> - else
> - return PAGE_SIZE;
> -}
> -
> static inline struct v12_1_compute_mqd *get_mqd(void *mqd) {
> return (struct v12_1_compute_mqd *)mqd; @@ -148,21 +137,14 @@
> static void set_priority(struct v12_1_compute_mqd *m, struct
> queue_properties *q static struct kfd_mem_obj *allocate_mqd(struct
> mqd_manager *mm,
> struct queue_properties *q)
> {
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
> struct kfd_node *node = mm->dev;
> struct kfd_mem_obj *mqd_mem_obj;
> - unsigned int size;
>
> - /*
> - * Allocate two PAGE_SIZE memory for Compute MQD as MES writes
> to areas beyond
> - * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE.
> - * For SDMA MQD, we allocate 1 Page_size.
> - */
> if (q->type == KFD_QUEUE_TYPE_COMPUTE)
> - size = MQD_SIZE * NUM_XCC(node->xcc_mask);
> - else
> - size = PAGE_SIZE;
> + mqd_size *= NUM_XCC(node->xcc_mask);
>
SDMA MQD allocation is not per XCC in the partition. This wastes a ton of memory for SDMA queues.
Regards,
Mukul
> - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
> return NULL;
>
> return mqd_mem_obj;
> @@ -174,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm,
> void **mqd, {
> uint64_t addr;
> struct v12_1_compute_mqd *m;
> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>
> m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr;
> addr = mqd_mem_obj->gpu_addr;
>
> - memset(m, 0, MQD_SIZE);
> + memset(m, 0, mqd_size);
>
> m->header = 0xC0310800;
> m->compute_pipelinestat_enable = 1;
> @@ -681,7 +664,7 @@ struct mqd_manager
> *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type,
> mqd->is_occupied = kfd_is_occupied_cp;
> mqd->mqd_size = sizeof(struct v12_1_compute_mqd);
> mqd->get_wave_state = get_wave_state_v12_1;
> - mqd->mqd_stride = mqd_stride_v12_1;
> + mqd->mqd_stride = kfd_mqd_stride;
> #if defined(CONFIG_DEBUG_FS)
> mqd->debugfs_show_mqd = debugfs_show_mqd; #endif
> --
> 2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* RE: [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager
2026-01-27 16:22 ` Joshi, Mukul
@ 2026-01-28 0:45 ` Yu, Lang
0 siblings, 0 replies; 9+ messages in thread
From: Yu, Lang @ 2026-01-28 0:45 UTC (permalink / raw)
To: Joshi, Mukul, amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking, Deucher, Alexander, Belanger, David
[Public]
>-----Original Message-----
>From: Joshi, Mukul <Mukul.Joshi@amd.com>
>Sent: Wednesday, January 28, 2026 12:23 AM
>To: Yu, Lang <Lang.Yu@amd.com>; amd-gfx@lists.freedesktop.org
>Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander
><Alexander.Deucher@amd.com>; Belanger, David <David.Belanger@amd.com>
>Subject: RE: [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+
>kfd mqd manager
>
>[AMD Official Use Only - AMD Internal Distribution Only]
>
>> -----Original Message-----
>> From: Yu, Lang <Lang.Yu@amd.com>
>> Sent: Monday, January 26, 2026 5:25 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander
>> <Alexander.Deucher@amd.com>; Joshi, Mukul <Mukul.Joshi@amd.com>;
>> Belanger, David <David.Belanger@amd.com>; Yu, Lang <Lang.Yu@amd.com>
>> Subject: [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+
>> kfd mqd manager
>>
>> MES is enabled by default from gfx11+.
>>
>> Signed-off-by: Lang Yu <lang.yu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 3 ++
>> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 22 +++-----------
>> .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 10 +++----
>> .../drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 29 ++++---------------
>> 4 files changed, 17 insertions(+), 47 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
>> index ceb6566ff3e1..d88d0de58edd 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
>> @@ -292,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev,
>> struct kfd_mem_obj *mqd_mem_obj, uint64_t kfd_mqd_stride(struct
>> mqd_manager *mm,
>> struct queue_properties *q) {
>> + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0))
>> + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>> +
>> return mm->mqd_size;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
>> index 5c44d0987737..7e5a7ab6d0c0 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
>> @@ -102,20 +102,11 @@ static void set_priority(struct v11_compute_mqd
>> *m, struct queue_properties *q) static struct kfd_mem_obj
>> *allocate_mqd(struct mqd_manager *mm,
>> struct queue_properties *q) {
>> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>> struct kfd_node *node = mm->dev;
>> struct kfd_mem_obj *mqd_mem_obj;
>> - int size;
>> -
>> - /*
>> - * MES write to areas beyond MQD size. So allocate
>> - * 1 PAGE_SIZE memory for MQD is MES is enabled.
>> - */
>> - if (node->kfd->shared_resources.enable_mes)
>> - size = PAGE_SIZE;
>> - else
>> - size = sizeof(struct v11_compute_mqd);
>>
>> - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
>> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
>> return NULL;
>>
>> return mqd_mem_obj;
>> @@ -127,18 +118,13 @@ static void init_mqd(struct mqd_manager *mm,
>> void **mqd, {
>> uint64_t addr;
>> struct v11_compute_mqd *m;
>> - int size;
>> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>> uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff;
>>
>> m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
>> addr = mqd_mem_obj->gpu_addr;
>>
>> - if (mm->dev->kfd->shared_resources.enable_mes)
>> - size = PAGE_SIZE;
>> - else
>> - size = sizeof(struct v11_compute_mqd);
>> -
>> - memset(m, 0, size);
>> + memset(m, 0, mqd_size);
>>
>> m->header = 0xC0310800;
>> m->compute_pipelinestat_enable = 1; diff --git
>> a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
>> index b7ac2dea8775..a51f217329db 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
>> @@ -83,14 +83,11 @@ static void set_priority(struct v12_compute_mqd
>> *m, struct queue_properties *q) static struct kfd_mem_obj
>> *allocate_mqd(struct mqd_manager *mm,
>> struct queue_properties *q) {
>> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>> struct kfd_node *node = mm->dev;
>> struct kfd_mem_obj *mqd_mem_obj;
>>
>> - /*
>> - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas
>> beyond
>> - * struct MQD size.
>> - */
>> - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj))
>> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
>> return NULL;
>>
>> return mqd_mem_obj;
>> @@ -102,11 +99,12 @@ static void init_mqd(struct mqd_manager *mm, void
>> **mqd, {
>> uint64_t addr;
>> struct v12_compute_mqd *m;
>> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>>
>> m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr;
>> addr = mqd_mem_obj->gpu_addr;
>>
>> - memset(m, 0, PAGE_SIZE);
>> + memset(m, 0, mqd_size);
>>
>> m->header = 0xC0310800;
>> m->compute_pipelinestat_enable = 1; diff --git
>> a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
>> index 0b0d802a0917..d0776ba2cc99 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
>> @@ -32,17 +32,6 @@
>> #include "amdgpu_amdkfd.h"
>> #include "kfd_device_queue_manager.h"
>>
>> -#define MQD_SIZE (2 * PAGE_SIZE)
>> -
>> -static uint64_t mqd_stride_v12_1(struct mqd_manager *mm,
>> - struct queue_properties *q)
>> -{
>> - if (q->type == KFD_QUEUE_TYPE_COMPUTE)
>> - return MQD_SIZE;
>> - else
>> - return PAGE_SIZE;
>> -}
>> -
>> static inline struct v12_1_compute_mqd *get_mqd(void *mqd) {
>> return (struct v12_1_compute_mqd *)mqd; @@ -148,21 +137,14 @@
>> static void set_priority(struct v12_1_compute_mqd *m, struct
>> queue_properties *q static struct kfd_mem_obj *allocate_mqd(struct
>> mqd_manager *mm,
>> struct queue_properties *q) {
>> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>> struct kfd_node *node = mm->dev;
>> struct kfd_mem_obj *mqd_mem_obj;
>> - unsigned int size;
>>
>> - /*
>> - * Allocate two PAGE_SIZE memory for Compute MQD as MES writes
>> to areas beyond
>> - * struct MQD size. Size of the Compute MQD is 1 PAGE_SIZE.
>> - * For SDMA MQD, we allocate 1 Page_size.
>> - */
>> if (q->type == KFD_QUEUE_TYPE_COMPUTE)
>> - size = MQD_SIZE * NUM_XCC(node->xcc_mask);
>> - else
>> - size = PAGE_SIZE;
>> + mqd_size *= NUM_XCC(node->xcc_mask);
>>
>
>SDMA MQD allocation is not per XCC in the partition. This wastes a ton of memory for
>SDMA queues.
Look carefully. " if (q->type == KFD_QUEUE_TYPE_COMPUTE)" is still there.
Only compute queue will be applied.
Regards,
Lang
>Regards,
>Mukul
>
>> - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj))
>> + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
>> return NULL;
>>
>> return mqd_mem_obj;
>> @@ -174,11 +156,12 @@ static void init_mqd(struct mqd_manager *mm,
>> void **mqd, {
>> uint64_t addr;
>> struct v12_1_compute_mqd *m;
>> + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
>>
>> m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr;
>> addr = mqd_mem_obj->gpu_addr;
>>
>> - memset(m, 0, MQD_SIZE);
>> + memset(m, 0, mqd_size);
>>
>> m->header = 0xC0310800;
>> m->compute_pipelinestat_enable = 1; @@ -681,7 +664,7 @@ struct
>> mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type,
>> mqd->is_occupied = kfd_is_occupied_cp;
>> mqd->mqd_size = sizeof(struct v12_1_compute_mqd);
>> mqd->get_wave_state = get_wave_state_v12_1;
>> - mqd->mqd_stride = mqd_stride_v12_1;
>> + mqd->mqd_stride = kfd_mqd_stride;
>> #if defined(CONFIG_DEBUG_FS)
>> mqd->debugfs_show_mqd = debugfs_show_mqd; #endif
>> --
>> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size
2026-01-26 10:25 [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Lang Yu
` (2 preceding siblings ...)
2026-01-26 10:25 ` [PATCH 4/4] drm/amdkfd: Use AMDGPU_MQD_SIZE_ALIGN in gfx11+ kfd mqd manager Lang Yu
@ 2026-01-27 16:26 ` Joshi, Mukul
2026-01-28 0:41 ` Yu, Lang
3 siblings, 1 reply; 9+ messages in thread
From: Joshi, Mukul @ 2026-01-27 16:26 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking, Deucher, Alexander, Belanger, David
[AMD Official Use Only - AMD Internal Distribution Only]
> -----Original Message-----
> From: Yu, Lang <Lang.Yu@amd.com>
> Sent: Monday, January 26, 2026 5:25 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Joshi, Mukul <Mukul.Joshi@amd.com>;
> Belanger, David <David.Belanger@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> Subject: [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size
>
> MES FW uses addr(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) as
> fence address and writes a 32 bit fence value to this address.
>
> Driver needs to allocate some extra memory(at least 4 DWs) in addition to
> sizeof(struct mqd) as mqd memory.
>
> For gfx11/12, sizeof(struct mqd) < PAGE_SIZE, allocate mqd memory with
> PAGE_SIZE aligned works. For gfx12.1, sizeof(struct mqd) == PAGE_SIZE, it
> doesn't work.
>
> KFD mqd manager hardcodes mqd size to PAGE_SIZE/MQD_SIZE.
>
> Let's use AMDGPU_MQD_SIZE_ALIGN to avoid hardcoding in differnet place
> and across different IP version. It is used in two place.
> 1. mqd memory alloction
> 2. mqd stride initialization
>
> Signed-off-by: Lang Yu <lang.yu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 9c11535c44c6..41f32ed39113 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1239,6 +1239,11 @@ struct amdgpu_device {
> struct amdgpu_kfd_dev kfd;
> };
>
> +/*
> + * MES will use memory beyond struct MQD size, 5 DWs currently */
> +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) ALIGN(((mqd_size) + 20),
> +PAGE_SIZE)
Should we be using GPU Page size instead of CPU page size here?
Maybe this should be AMDGPU_GPU_PAGE_SIZE instead of PAGE_SIZE or you can use
AMDGPU_GPU_PAGE_ALIGN macro instead of ALIGN here.
Regards,
Mukul
> +
> static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
> uint8_t ip, uint8_t inst)
> {
> --
> 2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* RE: [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size
2026-01-27 16:26 ` [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size Joshi, Mukul
@ 2026-01-28 0:41 ` Yu, Lang
0 siblings, 0 replies; 9+ messages in thread
From: Yu, Lang @ 2026-01-28 0:41 UTC (permalink / raw)
To: Joshi, Mukul, amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking, Deucher, Alexander, Belanger, David
[Public]
>-----Original Message-----
>From: Joshi, Mukul <Mukul.Joshi@amd.com>
>Sent: Wednesday, January 28, 2026 12:26 AM
>To: Yu, Lang <Lang.Yu@amd.com>; amd-gfx@lists.freedesktop.org
>Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander
><Alexander.Deucher@amd.com>; Belanger, David <David.Belanger@amd.com>
>Subject: RE: [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size
>
>[AMD Official Use Only - AMD Internal Distribution Only]
>
>> -----Original Message-----
>> From: Yu, Lang <Lang.Yu@amd.com>
>> Sent: Monday, January 26, 2026 5:25 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander
>> <Alexander.Deucher@amd.com>; Joshi, Mukul <Mukul.Joshi@amd.com>;
>> Belanger, David <David.Belanger@amd.com>; Yu, Lang <Lang.Yu@amd.com>
>> Subject: [PATCH 1/4] drm/amdgpu: Add a helper macro to align mqd size
>>
>> MES FW uses addr(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t))
>> as fence address and writes a 32 bit fence value to this address.
>>
>> Driver needs to allocate some extra memory(at least 4 DWs) in addition
>> to sizeof(struct mqd) as mqd memory.
>>
>> For gfx11/12, sizeof(struct mqd) < PAGE_SIZE, allocate mqd memory with
>> PAGE_SIZE aligned works. For gfx12.1, sizeof(struct mqd) == PAGE_SIZE,
>> it doesn't work.
>>
>> KFD mqd manager hardcodes mqd size to PAGE_SIZE/MQD_SIZE.
>>
>> Let's use AMDGPU_MQD_SIZE_ALIGN to avoid hardcoding in differnet place
>> and across different IP version. It is used in two place.
>> 1. mqd memory alloction
>> 2. mqd stride initialization
>>
>> Signed-off-by: Lang Yu <lang.yu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 9c11535c44c6..41f32ed39113 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -1239,6 +1239,11 @@ struct amdgpu_device {
>> struct amdgpu_kfd_dev kfd;
>> };
>>
>> +/*
>> + * MES will use memory beyond struct MQD size, 5 DWs currently */
>> +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) ALIGN(((mqd_size) + 20),
>> +PAGE_SIZE)
>
>Should we be using GPU Page size instead of CPU page size here?
>Maybe this should be AMDGPU_GPU_PAGE_SIZE instead of PAGE_SIZE or you can
>use AMDGPU_GPU_PAGE_ALIGN macro instead of ALIGN here.
Make sense. Thanks.
Regards,
Lang
>Regards,
>Mukul
>> +
>> static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
>> uint8_t ip, uint8_t inst) {
>> --
>> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread