[PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[Timur Kristóf]

Some GPUs use external DP bridge encoders NUTMEG and TRAVIS
to implement analog and/or LVDS connections. Typically found in
CIK APU based laptops or on FM2 motherboards that have analog
connectors. These were necessary at the time because Kaveri
didn't have a built-in DAC nor LVDS support.

These devices sadly don't work transparently and need to be
controlled by the driver. This series implements that.

The first half of the series contains some minor fixes and
refactoring necessary for these external encoders to work.
The second half then adds the actual external encoder support.

When we query connector information from the VBIOS and
discover a connector using such an encoder, let's find the
real DisplayPort encoder and use that. Set the connector
signal type to DP, so the pre-existing DP code paths can
work with it without refactoring every signal type check
in the DC code base.

With that, we can now enable DC by default on CIK APUs too.
DC brings proper support for DP/HDMI audio, DP MST, VRR,
10-bit colors, some HDR features, atomic modesetting, etc.
without any loss of functionality.

Timur Kristóf (14):
  drm/amd/display: Use DCE 6 link encoder for DCE 6 analog connectors
  drm/amd/display: Only use analog link encoder with analog engine
  drm/amd/display: Only use analog stream encoder with analog engine
  drm/amd/display: Add color depth helper function to BIOS parser
  drm/amd/display: Refactor DAC load detection, move to HWSS
  drm/amd/display: Implement BIOS parser external encoder control
  drm/amd/display: Implement DDC probe over AUX channel
  drm/amd/display: Add ability for HWSS to prepare the DDC before use
  drm/amd/display: Use preferred DP link rate if specified
  drm/amd/display: Add DCE HWSS support for external DP bridge encoders
  drm/amd/display: Link detection for external DP bridge encoders
  drm/amd/display: Use external DP bridge encoders
  drm/amd/display: Implement DAC load detection on external DP bridge
    encoders
  drm/amdgpu: Use DC by default on CIK APUs

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  11 --
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   9 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |   3 +
 .../gpu/drm/amd/display/dc/bios/bios_parser.c |  46 +++++--
 .../drm/amd/display/dc/bios/command_table.c   | 124 ++++++------------
 drivers/gpu/drm/amd/display/dc/dc.h           |   4 +
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |   6 +-
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c |  67 ++++++++++
 .../drm/amd/display/dc/hwss/hw_sequencer.h    |   2 +
 .../drm/amd/display/dc/link/link_detection.c  |  56 ++++----
 .../drm/amd/display/dc/link/link_factory.c    |  29 +++-
 .../dc/link/protocols/link_dp_capability.c    |   2 +
 .../link/protocols/link_edp_panel_control.c   |   8 +-
 .../dc/resource/dce100/dce100_resource.c      |   8 +-
 .../dc/resource/dce60/dce60_resource.c        |   5 +-
 .../dc/resource/dce80/dce80_resource.c        |   3 +-
 .../amd/display/include/bios_parser_types.h   |   2 +
 17 files changed, 228 insertions(+), 157 deletions(-)

-- 
2.52.0

[PATCH 01/14] drm/amd/display: Use DCE 6 link encoder for DCE 6 analog connectors

[Timur Kristóf]

DCE 6 should use the DCE 6 specific link encoder.
This was a copy paste mistake.

Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
index f0152933bee2..068fb1df8d88 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
@@ -734,7 +734,7 @@ static struct link_encoder *dce60_link_encoder_create(
 		return NULL;
 
 	if (enc_init_data->connector.id == CONNECTOR_ID_VGA) {
-		dce110_link_encoder_construct(enc110,
+		dce60_link_encoder_construct(enc110,
 			enc_init_data,
 			&link_enc_feature,
 			&link_enc_regs[ENGINE_ID_DACA],
-- 
2.52.0

[PATCH 02/14] drm/amd/display: Only use analog link encoder with analog engine

[Timur Kristóf]

Some GPUs have analog connectors that work with a DP bridge chip
and don't actually have an internal DAC: Those should not use
the analog link encoder code path.

Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index d40d91ec2035..a916872db7bd 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -638,7 +638,8 @@ static struct link_encoder *dce100_link_encoder_create(
 	if (!enc110)
 		return NULL;
 
-	if (enc_init_data->connector.id == CONNECTOR_ID_VGA) {
+	if (enc_init_data->connector.id == CONNECTOR_ID_VGA &&
+	    enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) {
 		dce110_link_encoder_construct(enc110,
 			enc_init_data,
 			&link_enc_feature,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
index 068fb1df8d88..90d826237cf0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
@@ -733,7 +733,8 @@ static struct link_encoder *dce60_link_encoder_create(
 	if (!enc110)
 		return NULL;
 
-	if (enc_init_data->connector.id == CONNECTOR_ID_VGA) {
+	if (enc_init_data->connector.id == CONNECTOR_ID_VGA &&
+	    enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) {
 		dce60_link_encoder_construct(enc110,
 			enc_init_data,
 			&link_enc_feature,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index 8687104cabb7..cde2c2cba1dd 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -740,7 +740,8 @@ static struct link_encoder *dce80_link_encoder_create(
 	if (!enc110)
 		return NULL;
 
-	if (enc_init_data->connector.id == CONNECTOR_ID_VGA) {
+	if (enc_init_data->connector.id == CONNECTOR_ID_VGA &&
+	    enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) {
 		dce110_link_encoder_construct(enc110,
 			enc_init_data,
 			&link_enc_feature,
-- 
2.52.0

[PATCH 03/14] drm/amd/display: Only use analog stream encoder with analog engine

[Timur Kristóf]

Some GPUs have analog connectors that work with a DP bridge chip
and don't actually have an internal DAC: Those should not use
the analog stream encoders.

Fixes: 5834c33fd3f6 ("drm/amd/display: Add concept of analog encoders (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index a916872db7bd..83b9abb64bfc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -979,7 +979,10 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
 	struct dc_link *link = stream->link;
 	enum engine_id preferred_engine = link->link_enc->preferred_engine;
 
-	if (dc_is_rgb_signal(stream->signal))
+	/* Prefer analog engine if the link encoder has one.
+	 * Otherwise, it's an external encoder.
+	 */
+	if (dc_is_rgb_signal(stream->signal) && link->link_enc->analog_engine != ENGINE_ID_UNKNOWN)
 		preferred_engine = link->link_enc->analog_engine;
 
 	for (i = 0; i < pool->stream_enc_count; i++) {
-- 
2.52.0

[PATCH 04/14] drm/amd/display: Add color depth helper function to BIOS parser

[Timur Kristóf]

To improve consistency and avoid duplicating the same code.
Also, properly handle all enum values where they weren't
handled correctly before.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../drm/amd/display/dc/bios/command_table.c   | 101 +++++-------------
 1 file changed, 26 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 76a3559f0ddc..b638cb5adb92 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -226,6 +226,28 @@ static enum bp_result encoder_control_dig2_v1(
 	return result;
 }
 
+static uint8_t dc_color_depth_to_atom(enum dc_color_depth color_depth)
+{
+	switch (color_depth) {
+	case COLOR_DEPTH_UNDEFINED:
+		return PANEL_BPC_UNDEFINE;
+	case COLOR_DEPTH_666:
+		return PANEL_6BIT_PER_COLOR;
+	default:
+	case COLOR_DEPTH_888:
+		return PANEL_8BIT_PER_COLOR;
+	case COLOR_DEPTH_101010:
+		return PANEL_10BIT_PER_COLOR;
+	case COLOR_DEPTH_121212:
+		return PANEL_12BIT_PER_COLOR;
+	case COLOR_DEPTH_141414:
+		dm_error("14-bit color not supported by ATOMBIOS\n");
+		return PANEL_BPC_UNDEFINE;
+	case COLOR_DEPTH_161616:
+		return PANEL_16BIT_PER_COLOR;
+	}
+}
+
 static enum bp_result encoder_control_digx_v3(
 	struct bios_parser *bp,
 	struct bp_encoder_control *cntl)
@@ -248,23 +270,7 @@ static enum bp_result encoder_control_digx_v3(
 					cntl->signal,
 					cntl->enable_dp_audio);
 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-
-	switch (cntl->color_depth) {
-	case COLOR_DEPTH_888:
-		params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_101010:
-		params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_121212:
-		params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_161616:
-		params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
-		break;
-	default:
-		break;
-	}
+	params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth);
 
 	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
 		result = BP_RESULT_OK;
@@ -294,23 +300,7 @@ static enum bp_result encoder_control_digx_v4(
 					cntl->signal,
 					cntl->enable_dp_audio));
 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-
-	switch (cntl->color_depth) {
-	case COLOR_DEPTH_888:
-		params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_101010:
-		params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_121212:
-		params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_161616:
-		params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
-		break;
-	default:
-		break;
-	}
+	params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth);
 
 	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
 		result = BP_RESULT_OK;
@@ -334,23 +324,7 @@ static enum bp_result encoder_control_digx_v5(
 					cntl->signal,
 					cntl->enable_dp_audio));
 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-
-	switch (cntl->color_depth) {
-	case COLOR_DEPTH_888:
-		params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_101010:
-		params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_121212:
-		params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_161616:
-		params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
-		break;
-	default:
-		break;
-	}
+	params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth);
 
 	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
 		switch (cntl->color_depth) {
@@ -1797,30 +1771,7 @@ static enum bp_result select_crtc_source_v3(
 		&params.ucEncodeMode))
 		return BP_RESULT_BADINPUT;
 
-	switch (bp_params->color_depth) {
-	case COLOR_DEPTH_UNDEFINED:
-		params.ucDstBpc = PANEL_BPC_UNDEFINE;
-		break;
-	case COLOR_DEPTH_666:
-		params.ucDstBpc = PANEL_6BIT_PER_COLOR;
-		break;
-	default:
-	case COLOR_DEPTH_888:
-		params.ucDstBpc = PANEL_8BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_101010:
-		params.ucDstBpc = PANEL_10BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_121212:
-		params.ucDstBpc = PANEL_12BIT_PER_COLOR;
-		break;
-	case COLOR_DEPTH_141414:
-		dm_error("14-bit color not supported by SelectCRTC_Source v3\n");
-		break;
-	case COLOR_DEPTH_161616:
-		params.ucDstBpc = PANEL_16BIT_PER_COLOR;
-		break;
-	}
+	params.ucDstBpc = dc_color_depth_to_atom(bp_params->color_depth);
 
 	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
 		result = BP_RESULT_OK;
-- 
2.52.0

[PATCH 05/14] drm/amd/display: Refactor DAC load detection, move to HWSS

[Timur Kristóf]

Slightly refactor and simplify DAC load detection.
This prepares the code to be used for also executing DAC
load detection on external DP bridge encoders.

DAC load detection belongs better in the hardware sequencer
code because the implementation is HW dependent and not all
chips support the functionality. The code is cleaner when
link detection probably doesn't call the VBIOS directly.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/dc/bios/bios_parser.c | 25 ++++++++-----------
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |  4 +--
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 12 +++++++++
 .../drm/amd/display/dc/hwss/hw_sequencer.h    |  1 +
 .../drm/amd/display/dc/link/link_detection.c  | 24 +++---------------
 5 files changed, 28 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 9f11e6ca4051..e2b74dda00fc 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -782,26 +782,17 @@ static enum bp_result bios_parser_encoder_control(
 
 static enum bp_result bios_parser_dac_load_detection(
 	struct dc_bios *dcb,
-	enum engine_id engine_id,
-	enum dal_device_type device_type,
-	uint32_t enum_id)
+	enum engine_id engine_id)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct dc_context *ctx = dcb->ctx;
 	struct bp_load_detection_parameters bp_params = {0};
-	enum bp_result bp_result;
+	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
 	uint32_t bios_0_scratch;
 	uint32_t device_id_mask = 0;
 
-	bp_params.engine_id = engine_id;
-	bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id);
-
-	if (engine_id != ENGINE_ID_DACA &&
-	    engine_id != ENGINE_ID_DACB)
-		return BP_RESULT_UNSUPPORTED;
-
-	if (!bp->cmd_tbl.dac_load_detection)
-		return BP_RESULT_UNSUPPORTED;
+	bp_params.device_id = get_support_mask_for_device_id(
+		DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
 
 	if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT)
 		device_id_mask = ATOM_S0_CRT1_MASK;
@@ -815,7 +806,13 @@ static enum bp_result bios_parser_dac_load_detection(
 	bios_0_scratch &= ~device_id_mask;
 	dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch);
 
-	bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
+	if (engine_id == ENGINE_ID_DACA || engine_id == ENGINE_ID_DACB) {
+		if (!bp->cmd_tbl.dac_load_detection)
+			return BP_RESULT_UNSUPPORTED;
+
+		bp_params.engine_id = engine_id;
+		bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
+	}
 
 	if (bp_result != BP_RESULT_OK)
 		return bp_result;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 40d7a7d83c40..06fdde281a0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -99,9 +99,7 @@ struct dc_vbios_funcs {
 		struct bp_encoder_control *cntl);
 	enum bp_result (*dac_load_detection)(
 		struct dc_bios *bios,
-		enum engine_id engine_id,
-		enum dal_device_type device_type,
-		uint32_t enum_id);
+		enum engine_id engine_id);
 	enum bp_result (*transmitter_control)(
 		struct dc_bios *bios,
 		struct bp_transmitter_control *cntl);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 4659e1b489ba..4e820020252b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -674,6 +674,17 @@ dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)
 	bios->funcs->encoder_control(bios, &encoder_control);
 }
 
+static bool
+dce110_dac_load_detect(struct dc_link *link)
+{
+	struct dc_bios *bios = link->ctx->dc_bios;
+	struct link_encoder *link_enc = link->link_enc;
+	enum bp_result bp_result = BP_RESULT_FAILURE;
+
+	bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine);
+	return bp_result == BP_RESULT_OK;
+}
+
 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 {
 	enum dc_lane_count lane_count =
@@ -3442,6 +3453,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.enable_tmds_link_output = dce110_enable_tmds_link_output,
 	.enable_dp_link_output = dce110_enable_dp_link_output,
 	.disable_link_output = dce110_disable_link_output,
+	.dac_load_detect = dce110_dac_load_detect,
 };
 
 static const struct hwseq_private_funcs dce110_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 51b0f0fd8fcd..5c9a758fde37 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -1187,6 +1187,7 @@ struct hw_sequencer_funcs {
 	void (*disable_link_output)(struct dc_link *link,
 			const struct link_resource *link_res,
 			enum signal_type signal);
+	bool (*dac_load_detect)(struct dc_link *link);
 
 	void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits);
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 578509e8d0e2..1585cce65b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -932,28 +932,10 @@ static bool link_detect_ddc_probe(struct dc_link *link)
  */
 static bool link_detect_dac_load_detect(struct dc_link *link)
 {
-	struct dc_bios *bios = link->ctx->dc_bios;
-	struct link_encoder *link_enc = link->link_enc;
-	enum engine_id engine_id = link_enc->preferred_engine;
-	enum dal_device_type device_type = DEVICE_TYPE_CRT;
-	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
-	uint32_t enum_id;
-
-	switch (engine_id) {
-	case ENGINE_ID_DACB:
-		enum_id = 2;
-		break;
-	case ENGINE_ID_DACA:
-	default:
-		engine_id = ENGINE_ID_DACA;
-		enum_id = 1;
-		break;
-	}
-
-	if (bios->funcs->dac_load_detection)
-		bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id);
+	if (!link->dc->hwss.dac_load_detect)
+		return false;
 
-	return bp_result == BP_RESULT_OK;
+	return link->dc->hwss.dac_load_detect(link);
 }
 
 /*
-- 
2.52.0

[PATCH 06/14] drm/amd/display: Implement BIOS parser external encoder control

[Timur Kristóf]

The VBIOS has a function called ExternalEncoderControl which
controls the DP bridge encoders that some GPUs use for analog
and LVDS output. Fixup this old functionality.

For reference, see the legacy non-DC amdgpu display code:
amdgpu_atombios_encoder_setup_external_encoder()

- Set same parameters for the ENABLE action as the SETUP action
- Add missing enum values for DDC setup and DAC load detection
- Fix the bits per color field
- Clarify the code that sets the link rate
- Expose the function so that it can be called by rest of DC

A subsequent commit will call this function from DCE HWSS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/dc/bios/bios_parser.c | 14 +++++++++++
 .../drm/amd/display/dc/bios/command_table.c   | 23 +++++++++----------
 .../gpu/drm/amd/display/dc/dc_bios_types.h    |  3 +++
 .../amd/display/include/bios_parser_types.h   |  2 ++
 4 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index e2b74dda00fc..82877f7b3b6f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -780,6 +780,18 @@ static enum bp_result bios_parser_encoder_control(
 	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
 }
 
+static enum bp_result bios_parser_external_encoder_control(
+	struct dc_bios *dcb,
+	struct bp_external_encoder_control *cntl)
+{
+	struct bios_parser *bp = BP_FROM_DCB(dcb);
+
+	if (!bp->cmd_tbl.external_encoder_control)
+		return BP_RESULT_UNSUPPORTED;
+
+	return bp->cmd_tbl.external_encoder_control(bp, cntl);
+}
+
 static enum bp_result bios_parser_dac_load_detection(
 	struct dc_bios *dcb,
 	enum engine_id engine_id)
@@ -2909,6 +2921,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
 
 	.encoder_control = bios_parser_encoder_control,
 
+	.external_encoder_control = bios_parser_external_encoder_control,
+
 	.dac_load_detection = bios_parser_dac_load_detection,
 
 	.transmitter_control = bios_parser_transmitter_control,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index b638cb5adb92..d2d59732d338 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -2521,6 +2521,7 @@ static enum bp_result external_encoder_control_v3(
 				cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
 		break;
 	case EXTERNAL_ENCODER_CONTROL_SETUP:
+	case EXTERNAL_ENCODER_CONTROL_ENABLE:
 		/* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in
 		 * 10KHz
 		 * output display device pixel clock frequency in unit of 10KHz.
@@ -2537,26 +2538,24 @@ static enum bp_result external_encoder_control_v3(
 		if (is_input_signal_dp) {
 			/* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz,
 			 * only valid in encoder setup with DP mode. */
-			if (LINK_RATE_HIGH == cntl->link_rate)
-				cntl_params->ucConfig |= 1;
+			if (cntl->link_rate == LINK_RATE_LOW)
+				cntl_params->ucConfig |=
+					EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ;
+			else if (cntl->link_rate == LINK_RATE_HIGH)
+				cntl_params->ucConfig |=
+					EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
+			else
+				dm_error("Link rate not supported by external encoder");
+
 			/* output color depth Indicate encoder data bpc format
 			 * in DP mode, only valid in encoder setup in DP mode.
 			 */
-			cntl_params->ucBitPerColor =
-					(uint8_t)(cntl->color_depth);
+			cntl_params->ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth);
 		}
 		/* Indicate how many lanes used by external encoder, only valid
 		 * in encoder setup and enableoutput. */
 		cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number);
 		break;
-	case EXTERNAL_ENCODER_CONTROL_ENABLE:
-		cntl_params->usPixelClock =
-				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-		cntl_params->ucEncoderMode =
-				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-						cntl->signal, false);
-		cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;
-		break;
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 06fdde281a0c..6f96c5cf39fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -97,6 +97,9 @@ struct dc_vbios_funcs {
 	enum bp_result (*encoder_control)(
 		struct dc_bios *bios,
 		struct bp_encoder_control *cntl);
+	enum bp_result (*external_encoder_control)(
+		struct dc_bios *bios,
+		struct bp_external_encoder_control *cntl);
 	enum bp_result (*dac_load_detection)(
 		struct dc_bios *bios,
 		enum engine_id engine_id);
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index f40dc612ec73..b5d97b394131 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -93,6 +93,8 @@ enum bp_external_encoder_control_action {
 	EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
 	EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
 	EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
+	EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT = 0x12,
+	EXTERNAL_ENCODER_CONTROL_DDC_SETUP = 0x14,
 };
 
 enum bp_pipe_control_action {
-- 
2.52.0

[PATCH 07/14] drm/amd/display: Implement DDC probe over AUX channel

[Timur Kristóf]

DDC probe means that we use the DDC (Display Data Channel) to
verify whether a display is connected or not.

This was written with mainly analog connectors in mind, so it
didn't work over the AUX channel. However, in order to support
external DP bridge encoders found in CIK APUs, it needs to work
over the AUX channel too.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/link/link_detection.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 1585cce65b0e..e1d568905581 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -903,11 +903,18 @@ static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])
  */
 static bool link_detect_ddc_probe(struct dc_link *link)
 {
+	enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD);
+	enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal);
+
 	if (!link->ddc)
 		return false;
 
+	set_ddc_transaction_type(link->ddc, transaction_type);
+
 	uint8_t edid_header[8] = {0};
-	bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header));
+	uint8_t zero = 0;
+	bool ddc_probed =
+		link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header));
 
 	if (!ddc_probed)
 		return false;
-- 
2.52.0

[PATCH 08/14] drm/amd/display: Add ability for HWSS to prepare the DDC before use

[Timur Kristóf]

Make it possible to add a HWSS function to prepare the DDC
before trying to use it. This is going to be necessary for
external DP bridge encoders.

This commit just adds the function to common DC code.
The actual implementation of this function for DCE is
done in a subsequent commit.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 +++
 drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h        | 1 +
 drivers/gpu/drm/amd/display/dc/link/link_detection.c      | 3 +++
 3 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 1f41d6540b83..3b8b7a4d9dd8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -1016,6 +1016,9 @@ enum dc_edid_status dm_helpers_read_local_edid(
 	else
 		ddc = &aconnector->i2c->base;
 
+	if (link->dc->hwss.prepare_ddc)
+		link->dc->hwss.prepare_ddc(link);
+
 	/* some dongles read edid incorrectly the first time,
 	 * do check sum and retry to make sure read correct edid.
 	 */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 5c9a758fde37..93e171c3a179 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -1188,6 +1188,7 @@ struct hw_sequencer_funcs {
 			const struct link_resource *link_res,
 			enum signal_type signal);
 	bool (*dac_load_detect)(struct dc_link *link);
+	void (*prepare_ddc)(struct dc_link *link);
 
 	void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits);
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index e1d568905581..2ccbca570c77 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -909,6 +909,9 @@ static bool link_detect_ddc_probe(struct dc_link *link)
 	if (!link->ddc)
 		return false;
 
+	if (link->dc->hwss.prepare_ddc)
+		link->dc->hwss.prepare_ddc(link);
+
 	set_ddc_transaction_type(link->ddc, transaction_type);
 
 	uint8_t edid_header[8] = {0};
-- 
2.52.0

[PATCH 09/14] drm/amd/display: Use preferred DP link rate if specified

[Timur Kristóf]

The DisplayPort code already has the concept of preferred link
settings, but it only allows setting a preferred lane count and
link width at the same time. It does not consider the possiblity
that some devices may not work on lower link rates but may
support various lane counts.

Allow specifying a preferred link rate which will be used as
the initial link rate when deciding the DP link settings.

This is necessary to support NUTMEG which only works with HBR
but not with RBR.

For reference, see the legacy non-DC amdgpu display code:
amdgpu_atombios_dp_get_dp_link_config()

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c  | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index cdc7587cf0b6..e12bf3dd3e46 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -743,6 +743,8 @@ static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_setting
 {
 	struct dc_link_settings initial_link_setting = {
 		LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
+	if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
+		initial_link_setting.link_rate = link->preferred_link_setting.link_rate;
 	struct dc_link_settings current_link_setting =
 			initial_link_setting;
 	uint32_t link_bw;
-- 
2.52.0

[PATCH 10/14] drm/amd/display: Add DCE HWSS support for external DP bridge encoders

[Timur Kristóf]

Some GPUs use external DP bridge encoders NUTMEG and TRAVIS
to implement analog and/or LVDS connections. Typically found in
CIK APU based laptops or on FM2 motherboards that have analog
connectors. These were necessary at the time because Kaveri
didn't have a built-in DAC nor LVDS support.

These devices sadly don't work transparently and need to be
controlled by the driver. Implement the necessary control for
the NUTMEG and TRAVIS encoders in the DCE HWSS.

For reference, see the legacy non-DC amdgpu display code:
amdgpu_atombios_encoder_setup_external_encoder()
amdgpu_atombios_encoder_setup_dig()
amdgpu_atombios_encoder_setup_ext_encoder_ddc()

- Prepare DDC before using it:
  Call the EXTERNAL_ENCODER_CONTROL_DDC_SETUP action so that
  the encoder knows to set up DDC over the AUX channel.

- When a stream is enabled or disabled:
  Call the EXTERNAL_ENCODER_CONTROL_ENABLE/DISABLE actions.

- Before enabling the DP link:
  Call the EXTERNAL_ENCODER_CONTROL_SETUP action.

This commit just hooks up the HWSS support.
Detecting the external DP bridge encoders will be done in
a subsequent commit.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h           |  4 ++
 .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 54 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ff15e5990ec0..11c0fa317f88 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1681,6 +1681,10 @@ struct dc_scratch_space {
 	struct panel_cntl *panel_cntl;
 	struct link_encoder *link_enc;
 	struct graphics_object_id link_id;
+
+	/* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */
+	struct graphics_object_id ext_enc_id;
+
 	/* Endpoint type distinguishes display endpoints which do not have entries
 	 * in the BIOS connector table from those that do. Helps when tracking link
 	 * encoder to display endpoint assignments.
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 4e820020252b..3f5c833ce18a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -660,6 +660,48 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 	}
 }
 
+static void
+dce110_external_encoder_control(enum bp_external_encoder_control_action action,
+				struct dc_link *link,
+				struct dc_crtc_timing *timing)
+{
+	struct dc *dc = link->ctx->dc;
+	struct dc_bios *bios = link->ctx->dc_bios;
+	const struct dc_link_settings *link_settings = &link->cur_link_settings;
+	enum bp_result bp_result = BP_RESULT_OK;
+	struct bp_external_encoder_control ext_cntl = {
+		.action = action,
+		.connector_obj_id = link->link_enc->connector,
+		.encoder_id = link->ext_enc_id,
+		.lanes_number = link_settings->lane_count,
+		.link_rate = link_settings->link_rate,
+
+		/* Use signal type of the real link encoder, ie. DP */
+		.signal = link->connector_signal,
+
+		/* We don't know the timing yet when executing the SETUP action,
+		 * so use a reasonably high default value. It seems that ENABLE
+		 * can change the actual pixel clock but doesn't work with higher
+		 * pixel clocks than what SETUP was called with.
+		 */
+		.pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000,
+		.color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888,
+	};
+	DC_LOGGER_INIT();
+
+	bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl);
+
+	if (bp_result != BP_RESULT_OK)
+		DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action);
+}
+
+static void
+dce110_prepare_ddc(struct dc_link *link)
+{
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL);
+}
+
 static void
 dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)
 {
@@ -717,6 +759,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 
 	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
 		dce110_dac_encoder_control(pipe_ctx, true);
+
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing);
 }
 
 static enum bp_result link_transmitter_control(
@@ -1213,6 +1258,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
 
 	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
 		dce110_dac_encoder_control(pipe_ctx, false);
+
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL);
 }
 
 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
@@ -3362,6 +3410,11 @@ void dce110_enable_dp_link_output(
 		}
 	}
 
+	if (link->ext_enc_id.id) {
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL);
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL);
+	}
+
 	if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
 		if (dc->clk_mgr->funcs->notify_link_rate_change)
 			dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
@@ -3454,6 +3507,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.enable_dp_link_output = dce110_enable_dp_link_output,
 	.disable_link_output = dce110_disable_link_output,
 	.dac_load_detect = dce110_dac_load_detect,
+	.prepare_ddc = dce110_prepare_ddc,
 };
 
 static const struct hwseq_private_funcs dce110_private_funcs = {
-- 
2.52.0

[PATCH 11/14] drm/amd/display: Link detection for external DP bridge encoders

[Timur Kristóf]

Deal with some minor idiosyncracies of TRAVIS and NUTMEG chips.

- Always use DP signal type with these chips so that the
  normal DP code paths can work with them without a major
  refactor of the code base. Properly set this.

- NUTMEG seems to only work with HBR, not RBR, so set a
  preferred link rate for this chip.
  See amdgpu_atombios_dp_get_dp_link_config() for reference.

- NUTMEG is recognized as a DP branch device but reports 0 sinks,
  which is wrong and confuses DC (it hits an early return).
  Fix that by hardcoding the sink count to 1.

- Fixup old DC code selecting a special panel mode necessary
  for NUTMEG and TRAVIS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../drm/amd/display/dc/link/link_detection.c  | 20 +++++++++++--------
 .../link/protocols/link_edp_panel_control.c   |  8 ++------
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 2ccbca570c77..aa3df3a090d5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -150,14 +150,6 @@ static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 		default:
 			return SIGNAL_TYPE_NONE;
 		}
-	} else if (downstream.type == OBJECT_TYPE_ENCODER) {
-		switch (downstream.id) {
-		case ENCODER_ID_EXTERNAL_NUTMEG:
-		case ENCODER_ID_EXTERNAL_TRAVIS:
-			return SIGNAL_TYPE_DISPLAY_PORT;
-		default:
-			return SIGNAL_TYPE_NONE;
-		}
 	}
 
 	return SIGNAL_TYPE_NONE;
@@ -174,6 +166,10 @@ static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
 	struct audio_support *aud_support;
 	struct graphics_object_id enc_id;
 
+	/* External DP bridges should use DP signal regardless of connector type. */
+	if (link->ext_enc_id.id)
+		return SIGNAL_TYPE_DISPLAY_PORT;
+
 	if (link->is_dig_mapping_flexible)
 		enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 	else
@@ -620,6 +616,14 @@ static bool detect_dp(struct dc_link *link,
 		link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;
 	}
 
+	if (link->ext_enc_id.id) {
+		/* Fix number of connected sinks reported by external DP bridge */
+		link->dpcd_caps.sink_count.bits.SINK_COUNT = 1;
+		/* NUTMEG requires that we use HBR, doesn't work with RBR. */
+		if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_00001A)
+			link->preferred_link_setting.link_rate = LINK_RATE_HIGH;
+	}
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index aa02b38e183a..5b2c1a4911cf 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -100,11 +100,7 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
 
 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
 {
-	/* We need to explicitly check that connector
-	 * is not DP. Some Travis_VGA get reported
-	 * by video bios as DP.
-	 */
-	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
+	if (link->ext_enc_id.id) {
 
 		switch (link->dpcd_caps.branch_dev_id) {
 		case DP_BRANCH_DEVICE_ID_0022B9:
@@ -124,7 +120,7 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
 			}
 			break;
 		case DP_BRANCH_DEVICE_ID_00001A:
-			/* alternate scrambler reset is required for Travis
+			/* alternate scrambler reset is required for NUTMEG
 			 * for the case when external chip does not provide
 			 * sink device id, alternate scrambler scheme will
 			 * be overriden later by querying Encoder feature
-- 
2.52.0

[PATCH 12/14] drm/amd/display: Use external DP bridge encoders

[Timur Kristóf]

Implement link creation for external DP bridge encoders
such as NUTMEG and TRAVIS used with CIK APUs such as
Kaveri for supporting analog and LVDS connections.
Typically found in CIK APU based laptops or on FM2
motherboards that have analog connectors.

When we query connector information from the VBIOS and
discover a connector using such an encoder, let's find the
real DisplayPort encoder and use that. Set the connector
signal type to DP, so the pre-existing DP code paths can
work with it without refactoring every signal type check
in the DC code base.

In the DM, make sure to report correct connector type and
also to initialize DP specifics such as the AUX channel.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  9 ++++--
 .../drm/amd/display/dc/link/link_factory.c    | 29 ++++++++++++++++++-
 2 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8b4c45ac3c05..bd76118fab19 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8539,6 +8539,12 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id)
 		return DRM_MODE_CONNECTOR_VGA;
 	case SIGNAL_TYPE_DISPLAY_PORT:
 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
+		/* External DP bridges have a different connector type. */
+		if (connector_id == CONNECTOR_ID_VGA)
+			return DRM_MODE_CONNECTOR_VGA;
+		else if (connector_id == CONNECTOR_ID_LVDS)
+			return DRM_MODE_CONNECTOR_LVDS;
+
 		return DRM_MODE_CONNECTOR_DisplayPort;
 	case SIGNAL_TYPE_DVI_DUAL_LINK:
 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
@@ -9211,8 +9217,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 	    connector_type == DRM_MODE_CONNECTOR_HDMIB)
 		amdgpu_dm_initialize_hdmi_connector(aconnector);
 
-	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
-		|| connector_type == DRM_MODE_CONNECTOR_eDP)
+	if (dc_is_dp_signal(link->connector_signal))
 		amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
 
 out_free:
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 5fbcf04c6251..7d9deb8b9c28 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -367,6 +367,18 @@ static enum transmitter translate_encoder_to_transmitter(
 	}
 }
 
+static bool encoder_is_external_dp(
+		struct graphics_object_id encoder)
+{
+	switch (encoder.id) {
+	case ENCODER_ID_EXTERNAL_NUTMEG:
+	case ENCODER_ID_EXTERNAL_TRAVIS:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static void link_destruct(struct dc_link *link)
 {
 	int i;
@@ -514,6 +526,13 @@ static bool construct_phy(struct dc_link *link,
 	 * so that we avoid initializing DDC and HPD, etc.
 	 */
 	bp_funcs->get_src_obj(bios, link->link_id, 0, &link_encoder);
+
+	if (encoder_is_external_dp(link_encoder)) {
+		/* External DP bridge encoders: find the actual link encoder and use that. */
+		link->ext_enc_id = link_encoder;
+		bp_funcs->get_src_obj(bios, link->ext_enc_id, 0, &link_encoder);
+	}
+
 	transmitter_from_encoder = translate_encoder_to_transmitter(link_encoder);
 	link_analog_engine = find_analog_engine(link, &enc_init_data.analog_encoder);
 
@@ -690,6 +709,13 @@ static bool construct_phy(struct dc_link *link,
 		goto create_fail;
 	}
 
+	/* For external DP bridge encoders:
+	 * Set the connector signal to DisplayPort so that they can work with
+	 * the pre-existing code paths for DP without a lot of code churn.
+	 */
+	if (link->ext_enc_id.id != ENCODER_ID_UNKNOWN)
+		link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
+
 	LINK_INFO("Connector[%d] description: signal: %s\n",
 		  init_params->connector_index,
 		  signal_type_to_string(link->connector_signal));
@@ -734,7 +760,8 @@ static bool construct_phy(struct dc_link *link,
 						      link->device_tag.dev_id))
 			continue;
 		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
-		    link->connector_signal != SIGNAL_TYPE_RGB)
+		    link->connector_signal != SIGNAL_TYPE_RGB &&
+		    link->ext_enc_id.id == ENCODER_ID_UNKNOWN)
 			continue;
 		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
 		    link->connector_signal == SIGNAL_TYPE_RGB)
-- 
2.52.0

[PATCH 13/14] drm/amd/display: Implement DAC load detection on external DP bridge encoders

[Timur Kristóf]

Use the pre-existing implementation in the BIOS parser, but call
the ExternalEncoderControl function for external encoders instead
of the built-in DAC load detection function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c     | 11 ++++++++++-
 drivers/gpu/drm/amd/display/dc/dc_bios_types.h        |  3 ++-
 .../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c |  3 ++-
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 82877f7b3b6f..f56f3ee81a22 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -794,11 +794,13 @@ static enum bp_result bios_parser_external_encoder_control(
 
 static enum bp_result bios_parser_dac_load_detection(
 	struct dc_bios *dcb,
-	enum engine_id engine_id)
+	enum engine_id engine_id,
+	struct graphics_object_id ext_enc_id)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct dc_context *ctx = dcb->ctx;
 	struct bp_load_detection_parameters bp_params = {0};
+	struct bp_external_encoder_control ext_cntl = {0};
 	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
 	uint32_t bios_0_scratch;
 	uint32_t device_id_mask = 0;
@@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection(
 
 		bp_params.engine_id = engine_id;
 		bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
+	} else if (ext_enc_id.id) {
+		if (!bp->cmd_tbl.external_encoder_control)
+			return BP_RESULT_UNSUPPORTED;
+
+		ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT;
+		ext_cntl.encoder_id = ext_enc_id;
+		bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl);
 	}
 
 	if (bp_result != BP_RESULT_OK)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 6f96c5cf39fe..526f71616f94 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -102,7 +102,8 @@ struct dc_vbios_funcs {
 		struct bp_external_encoder_control *cntl);
 	enum bp_result (*dac_load_detection)(
 		struct dc_bios *bios,
-		enum engine_id engine_id);
+		enum engine_id engine_id,
+		struct graphics_object_id ext_enc_id);
 	enum bp_result (*transmitter_control)(
 		struct dc_bios *bios,
 		struct bp_transmitter_control *cntl);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 3f5c833ce18a..83d43b62747d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -723,7 +723,8 @@ dce110_dac_load_detect(struct dc_link *link)
 	struct link_encoder *link_enc = link->link_enc;
 	enum bp_result bp_result = BP_RESULT_FAILURE;
 
-	bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine);
+	bp_result = bios->funcs->dac_load_detection(
+			bios, link_enc->analog_engine, link->ext_enc_id);
 	return bp_result == BP_RESULT_OK;
 }
 
-- 
2.52.0

[PATCH 14/14] drm/amdgpu: Use DC by default on CIK APUs

[Timur Kristóf]

Now that DC supports external DP bridge encoders,
it has reached feature parity with the legacy non-DC display
driver on CIK APUs: Kaveri, Kabini, Mullins.

Use the DC display driver by default on SI dGPUs, unless it is
explicitly disabled using the amdgpu.dc=0 module parameter.

DC brings proper support for DP/HDMI audio, DP MST, VRR,
10-bit colors, some HDR features, atomic modesetting, etc.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 362ab2b34498..fc4656a23158 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4113,17 +4113,6 @@ bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,
 	case CHIP_VERDE:
 	case CHIP_OLAND:
 		return amdgpu_dc != 0 && IS_ENABLED(CONFIG_DRM_AMD_DC_SI);
-	case CHIP_KAVERI:
-	case CHIP_KABINI:
-	case CHIP_MULLINS:
-		/*
-		 * We have systems in the wild with these ASICs that require
-		 * TRAVIS and NUTMEG support which is not supported with DC.
-		 *
-		 * Fallback to the non-DC driver here by default so as not to
-		 * cause regressions.
-		 */
-		return amdgpu_dc > 0;
 	default:
 		return amdgpu_dc != 0;
 #else
-- 
2.52.0

Re: [PATCH 07/14] drm/amd/display: Implement DDC probe over AUX channel

[Alex Hung]

On 1/26/26 14:08, Timur Kristóf wrote:
> DDC probe means that we use the DDC (Display Data Channel) to
> verify whether a display is connected or not.
> 
> This was written with mainly analog connectors in mind, so it
> didn't work over the AUX channel. However, in order to support
> external DP bridge encoders found in CIK APUs, it needs to work
> over the AUX channel too.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>   drivers/gpu/drm/amd/display/dc/link/link_detection.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> index 1585cce65b0e..e1d568905581 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> @@ -903,11 +903,18 @@ static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])
>    */
>   static bool link_detect_ddc_probe(struct dc_link *link)
>   {
> +	enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD);
> +	enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal);
> +
>   	if (!link->ddc)
>   		return false;
>   
> +	set_ddc_transaction_type(link->ddc, transaction_type);
> +
>   	uint8_t edid_header[8] = {0};
> -	bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header));
> +	uint8_t zero = 0;
> +	bool ddc_probed =
> +		link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header));

Please move variable declaration to beginning of the function. Thanks.

>   
>   	if (!ddc_probed)
>   		return false;

Re: [PATCH 05/14] drm/amd/display: Refactor DAC load detection, move to HWSS

[Alex Hung]

On 1/26/26 14:08, Timur Kristóf wrote:
> Slightly refactor and simplify DAC load detection.
> This prepares the code to be used for also executing DAC
> load detection on external DP bridge encoders.
> 
> DAC load detection belongs better in the hardware sequencer
> code because the implementation is HW dependent and not all
> chips support the functionality. The code is cleaner when
> link detection probably doesn't call the VBIOS directly.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>   .../gpu/drm/amd/display/dc/bios/bios_parser.c | 25 ++++++++-----------
>   .../gpu/drm/amd/display/dc/dc_bios_types.h    |  4 +--
>   .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 12 +++++++++
>   .../drm/amd/display/dc/hwss/hw_sequencer.h    |  1 +
>   .../drm/amd/display/dc/link/link_detection.c  | 24 +++---------------
>   5 files changed, 28 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> index 9f11e6ca4051..e2b74dda00fc 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
> @@ -782,26 +782,17 @@ static enum bp_result bios_parser_encoder_control(
>   
>   static enum bp_result bios_parser_dac_load_detection(
>   	struct dc_bios *dcb,
> -	enum engine_id engine_id,
> -	enum dal_device_type device_type,
> -	uint32_t enum_id)
> +	enum engine_id engine_id)
>   {
>   	struct bios_parser *bp = BP_FROM_DCB(dcb);
>   	struct dc_context *ctx = dcb->ctx;
>   	struct bp_load_detection_parameters bp_params = {0};
> -	enum bp_result bp_result;
> +	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
>   	uint32_t bios_0_scratch;
>   	uint32_t device_id_mask = 0;
>   
> -	bp_params.engine_id = engine_id;
> -	bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id);
> -
> -	if (engine_id != ENGINE_ID_DACA &&
> -	    engine_id != ENGINE_ID_DACB)
> -		return BP_RESULT_UNSUPPORTED;
> -
> -	if (!bp->cmd_tbl.dac_load_detection)
> -		return BP_RESULT_UNSUPPORTED;
> +	bp_params.device_id = get_support_mask_for_device_id(
> +		DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
>   
>   	if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT)
>   		device_id_mask = ATOM_S0_CRT1_MASK;
> @@ -815,7 +806,13 @@ static enum bp_result bios_parser_dac_load_detection(
>   	bios_0_scratch &= ~device_id_mask;
>   	dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch);
>   
> -	bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
> +	if (engine_id == ENGINE_ID_DACA || engine_id == ENGINE_ID_DACB) {
> +		if (!bp->cmd_tbl.dac_load_detection)
> +			return BP_RESULT_UNSUPPORTED;
> +
> +		bp_params.engine_id = engine_id;
> +		bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
> +	}
>   
>   	if (bp_result != BP_RESULT_OK)
>   		return bp_result;
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> index 40d7a7d83c40..06fdde281a0c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
> @@ -99,9 +99,7 @@ struct dc_vbios_funcs {
>   		struct bp_encoder_control *cntl);
>   	enum bp_result (*dac_load_detection)(
>   		struct dc_bios *bios,
> -		enum engine_id engine_id,
> -		enum dal_device_type device_type,
> -		uint32_t enum_id);
> +		enum engine_id engine_id);
>   	enum bp_result (*transmitter_control)(
>   		struct dc_bios *bios,
>   		struct bp_transmitter_control *cntl);
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> index 4659e1b489ba..4e820020252b 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
> @@ -674,6 +674,17 @@ dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)
>   	bios->funcs->encoder_control(bios, &encoder_control);
>   }
>   
> +static bool
> +dce110_dac_load_detect(struct dc_link *link)
> +{
> +	struct dc_bios *bios = link->ctx->dc_bios;
> +	struct link_encoder *link_enc = link->link_enc;
> +	enum bp_result bp_result = BP_RESULT_FAILURE;

Nitpick - bp_result is assigned below right away so it doesn't have to 
be assigned here <-- complained by Coverity.

> +
> +	bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine);
> +	return bp_result == BP_RESULT_OK;
> +}
> +
>   void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
>   {
>   	enum dc_lane_count lane_count =
> @@ -3442,6 +3453,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
>   	.enable_tmds_link_output = dce110_enable_tmds_link_output,
>   	.enable_dp_link_output = dce110_enable_dp_link_output,
>   	.disable_link_output = dce110_disable_link_output,
> +	.dac_load_detect = dce110_dac_load_detect,
>   };
>   
>   static const struct hwseq_private_funcs dce110_private_funcs = {
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
> index 51b0f0fd8fcd..5c9a758fde37 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
> @@ -1187,6 +1187,7 @@ struct hw_sequencer_funcs {
>   	void (*disable_link_output)(struct dc_link *link,
>   			const struct link_resource *link_res,
>   			enum signal_type signal);
> +	bool (*dac_load_detect)(struct dc_link *link);
>   
>   	void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits);
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> index 578509e8d0e2..1585cce65b0e 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
> @@ -932,28 +932,10 @@ static bool link_detect_ddc_probe(struct dc_link *link)
>    */
>   static bool link_detect_dac_load_detect(struct dc_link *link)
>   {
> -	struct dc_bios *bios = link->ctx->dc_bios;
> -	struct link_encoder *link_enc = link->link_enc;
> -	enum engine_id engine_id = link_enc->preferred_engine;
> -	enum dal_device_type device_type = DEVICE_TYPE_CRT;
> -	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
> -	uint32_t enum_id;
> -
> -	switch (engine_id) {
> -	case ENGINE_ID_DACB:
> -		enum_id = 2;
> -		break;
> -	case ENGINE_ID_DACA:
> -	default:
> -		engine_id = ENGINE_ID_DACA;
> -		enum_id = 1;
> -		break;
> -	}
> -
> -	if (bios->funcs->dac_load_detection)
> -		bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id);
> +	if (!link->dc->hwss.dac_load_detect)
> +		return false;
>   
> -	return bp_result == BP_RESULT_OK;
> +	return link->dc->hwss.dac_load_detect(link);
>   }
>   
>   /*

Re: [PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[Rodrigo Siqueira]

On 01/26, Timur Kristóf wrote:
> Some GPUs use external DP bridge encoders NUTMEG and TRAVIS
> to implement analog and/or LVDS connections. Typically found in
> CIK APU based laptops or on FM2 motherboards that have analog
> connectors. These were necessary at the time because Kaveri
> didn't have a built-in DAC nor LVDS support.
> 
> These devices sadly don't work transparently and need to be
> controlled by the driver. This series implements that.
> 
> The first half of the series contains some minor fixes and
> refactoring necessary for these external encoders to work.
> The second half then adds the actual external encoder support.
> 
> When we query connector information from the VBIOS and
> discover a connector using such an encoder, let's find the
> real DisplayPort encoder and use that. Set the connector
> signal type to DP, so the pre-existing DP code paths can
> work with it without refactoring every signal type check
> in the DC code base.
> 
> With that, we can now enable DC by default on CIK APUs too.
> DC brings proper support for DP/HDMI audio, DP MST, VRR,
> 10-bit colors, some HDR features, atomic modesetting, etc.
> without any loss of functionality.
> 
> Timur Kristóf (14):
>   drm/amd/display: Use DCE 6 link encoder for DCE 6 analog connectors
>   drm/amd/display: Only use analog link encoder with analog engine
>   drm/amd/display: Only use analog stream encoder with analog engine
>   drm/amd/display: Add color depth helper function to BIOS parser
>   drm/amd/display: Refactor DAC load detection, move to HWSS
>   drm/amd/display: Implement BIOS parser external encoder control
>   drm/amd/display: Implement DDC probe over AUX channel
>   drm/amd/display: Add ability for HWSS to prepare the DDC before use
>   drm/amd/display: Use preferred DP link rate if specified
>   drm/amd/display: Add DCE HWSS support for external DP bridge encoders
>   drm/amd/display: Link detection for external DP bridge encoders
>   drm/amd/display: Use external DP bridge encoders
>   drm/amd/display: Implement DAC load detection on external DP bridge
>     encoders
>   drm/amdgpu: Use DC by default on CIK APUs
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  11 --
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   9 +-
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |   3 +
>  .../gpu/drm/amd/display/dc/bios/bios_parser.c |  46 +++++--
>  .../drm/amd/display/dc/bios/command_table.c   | 124 ++++++------------
>  drivers/gpu/drm/amd/display/dc/dc.h           |   4 +
>  .../gpu/drm/amd/display/dc/dc_bios_types.h    |   6 +-
>  .../amd/display/dc/hwss/dce110/dce110_hwseq.c |  67 ++++++++++
>  .../drm/amd/display/dc/hwss/hw_sequencer.h    |   2 +
>  .../drm/amd/display/dc/link/link_detection.c  |  56 ++++----
>  .../drm/amd/display/dc/link/link_factory.c    |  29 +++-
>  .../dc/link/protocols/link_dp_capability.c    |   2 +
>  .../link/protocols/link_edp_panel_control.c   |   8 +-
>  .../dc/resource/dce100/dce100_resource.c      |   8 +-
>  .../dc/resource/dce60/dce60_resource.c        |   5 +-
>  .../dc/resource/dce80/dce80_resource.c        |   3 +-
>  .../amd/display/include/bios_parser_types.h   |   2 +
>  17 files changed, 228 insertions(+), 157 deletions(-)
> 
> -- 
> 2.52.0
>

Hi Alex, Dan, Tom,

This series is the last to enable amdgpu as the default for all GFX7
GPUs. In this sense, could you include this series in the weekly
promotion to check whether everything looks ok from a feature
perspective?

Thanks

-- 
Rodrigo Siqueira

Re: [PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[Alex Hung]

On 2/9/26 08:35, Rodrigo Siqueira wrote:
> On 01/26, Timur Kristóf wrote:
>> Some GPUs use external DP bridge encoders NUTMEG and TRAVIS
>> to implement analog and/or LVDS connections. Typically found in
>> CIK APU based laptops or on FM2 motherboards that have analog
>> connectors. These were necessary at the time because Kaveri
>> didn't have a built-in DAC nor LVDS support.
>>
>> These devices sadly don't work transparently and need to be
>> controlled by the driver. This series implements that.
>>
>> The first half of the series contains some minor fixes and
>> refactoring necessary for these external encoders to work.
>> The second half then adds the actual external encoder support.
>>
>> When we query connector information from the VBIOS and
>> discover a connector using such an encoder, let's find the
>> real DisplayPort encoder and use that. Set the connector
>> signal type to DP, so the pre-existing DP code paths can
>> work with it without refactoring every signal type check
>> in the DC code base.
>>
>> With that, we can now enable DC by default on CIK APUs too.
>> DC brings proper support for DP/HDMI audio, DP MST, VRR,
>> 10-bit colors, some HDR features, atomic modesetting, etc.
>> without any loss of functionality.
>>
>> Timur Kristóf (14):
>>    drm/amd/display: Use DCE 6 link encoder for DCE 6 analog connectors
>>    drm/amd/display: Only use analog link encoder with analog engine
>>    drm/amd/display: Only use analog stream encoder with analog engine
>>    drm/amd/display: Add color depth helper function to BIOS parser
>>    drm/amd/display: Refactor DAC load detection, move to HWSS
>>    drm/amd/display: Implement BIOS parser external encoder control
>>    drm/amd/display: Implement DDC probe over AUX channel
>>    drm/amd/display: Add ability for HWSS to prepare the DDC before use
>>    drm/amd/display: Use preferred DP link rate if specified
>>    drm/amd/display: Add DCE HWSS support for external DP bridge encoders
>>    drm/amd/display: Link detection for external DP bridge encoders
>>    drm/amd/display: Use external DP bridge encoders
>>    drm/amd/display: Implement DAC load detection on external DP bridge
>>      encoders
>>    drm/amdgpu: Use DC by default on CIK APUs
>>
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  11 --
>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   9 +-
>>   .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |   3 +
>>   .../gpu/drm/amd/display/dc/bios/bios_parser.c |  46 +++++--
>>   .../drm/amd/display/dc/bios/command_table.c   | 124 ++++++------------
>>   drivers/gpu/drm/amd/display/dc/dc.h           |   4 +
>>   .../gpu/drm/amd/display/dc/dc_bios_types.h    |   6 +-
>>   .../amd/display/dc/hwss/dce110/dce110_hwseq.c |  67 ++++++++++
>>   .../drm/amd/display/dc/hwss/hw_sequencer.h    |   2 +
>>   .../drm/amd/display/dc/link/link_detection.c  |  56 ++++----
>>   .../drm/amd/display/dc/link/link_factory.c    |  29 +++-
>>   .../dc/link/protocols/link_dp_capability.c    |   2 +
>>   .../link/protocols/link_edp_panel_control.c   |   8 +-
>>   .../dc/resource/dce100/dce100_resource.c      |   8 +-
>>   .../dc/resource/dce60/dce60_resource.c        |   5 +-
>>   .../dc/resource/dce80/dce80_resource.c        |   3 +-
>>   .../amd/display/include/bios_parser_types.h   |   2 +
>>   17 files changed, 228 insertions(+), 157 deletions(-)
>>
>> -- 
>> 2.52.0
>>
> 
> Hi Alex, Dan, Tom,
> 
> This series is the last to enable amdgpu as the default for all GFX7
> GPUs. In this sense, could you include this series in the weekly
> promotion to check whether everything looks ok from a feature
> perspective?

This series was included in promotion test in previous week and no 
issues were found. However, it breaks CI tests and we will figure out 
what the causes are.

> 
> Thanks
> 

Re: [PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[Timur Kristóf]

On Monday, February 9, 2026 7:12:23 PM Central European Standard Time Alex 
Hung wrote:
> On 2/9/26 08:35, Rodrigo Siqueira wrote:
> > 
> > Hi Alex, Dan, Tom,
> > 
> > This series is the last to enable amdgpu as the default for all GFX7
> > GPUs. In this sense, could you include this series in the weekly
> > promotion to check whether everything looks ok from a feature
> > perspective?
> 
> This series was included in promotion test in previous week and no
> issues were found. However, it breaks CI tests and we will figure out
> what the causes are.
> 

Hi,

Can you say which tests are broken, and on which GPUs?
And which patch of the series is responsible?

Thanks,
Timur

Re: [PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[Alex Hung]

On 2/9/26 15:10, Timur Kristóf wrote:
> On Monday, February 9, 2026 7:12:23 PM Central European Standard Time Alex
> Hung wrote:
>> On 2/9/26 08:35, Rodrigo Siqueira wrote:
>>>
>>> Hi Alex, Dan, Tom,
>>>
>>> This series is the last to enable amdgpu as the default for all GFX7
>>> GPUs. In this sense, could you include this series in the weekly
>>> promotion to check whether everything looks ok from a feature
>>> perspective?
>>
>> This series was included in promotion test in previous week and no
>> issues were found. However, it breaks CI tests and we will figure out
>> what the causes are.
>>
> 
> Hi,
> 
> Can you say which tests are broken, and on which GPUs?
> And which patch of the series is responsible?

Some internal diag tests failed so we will into them ourselves. I don't 
know which patches are the cause and I will provide updates later.

> 
> Thanks,
> Timur
> 
> 
> 
> 
> 

Re: [PATCH 00/14] drm/amd/display: Add support for external DP bridge encoders in DC

[Alex Hung]

On 2/9/26 16:14, Alex Hung wrote:
> 
> 
> On 2/9/26 15:10, Timur Kristóf wrote:
>> On Monday, February 9, 2026 7:12:23 PM Central European Standard Time 
>> Alex
>> Hung wrote:
>>> On 2/9/26 08:35, Rodrigo Siqueira wrote:
>>>>
>>>> Hi Alex, Dan, Tom,
>>>>
>>>> This series is the last to enable amdgpu as the default for all GFX7
>>>> GPUs. In this sense, could you include this series in the weekly
>>>> promotion to check whether everything looks ok from a feature
>>>> perspective?
>>>
>>> This series was included in promotion test in previous week and no
>>> issues were found. However, it breaks CI tests and we will figure out
>>> what the causes are.
>>>
>>
>> Hi,
>>
>> Can you say which tests are broken, and on which GPUs?
>> And which patch of the series is responsible?
> 
> Some internal diag tests failed so we will into them ourselves. I don't 
> know which patches are the cause and I will provide updates later.

They are from changes of function definitions where the tools use. We 
should be able to change them accordingly.

This series is Reviewed-by: Alex Hung <alex.hung@amd.com>

> 
>>
>> Thanks,
>> Timur
>>
>>
>>
>>
>>
>